diff mbox

[U-Boot] m68k: add board stmark2, mcf5441x based

Message ID 20170714214502.14327-1-angelo@sysam.it
State Superseded
Delegated to: Jason Jin
Headers show

Commit Message

Angelo Dureghello July 14, 2017, 9:45 p.m. UTC 
Signed-off-by: Angelo Dureghello <angelo@sysam.it>
---
 arch/m68k/Kconfig                   |   5 +
 board/sysam/stmark2/Kconfig         |  15 +++
 board/sysam/stmark2/MAINTAINERS     |   6 ++
 board/sysam/stmark2/Makefile        |   8 ++
 board/sysam/stmark2/sbf_dram_init.S | 119 +++++++++++++++++++++
 board/sysam/stmark2/stmark2.c       |  47 +++++++++
 configs/stmark2_defconfig           |  26 +++++
 include/configs/stmark2.h           | 202 ++++++++++++++++++++++++++++++++++++
 scripts/config_whitelist.txt        |   1 +
 9 files changed, 429 insertions(+)
 create mode 100644 board/sysam/stmark2/Kconfig
 create mode 100644 board/sysam/stmark2/MAINTAINERS
 create mode 100644 board/sysam/stmark2/Makefile
 create mode 100644 board/sysam/stmark2/sbf_dram_init.S
 create mode 100644 board/sysam/stmark2/stmark2.c
 create mode 100644 configs/stmark2_defconfig
 create mode 100644 include/configs/stmark2.h

Comments

Christophe Leroy Aug. 5, 2017, 12:58 p.m. UTC | #1 
Le 14/07/2017 à 23:45, Angelo Dureghello a écrit :
> Signed-off-by: Angelo Dureghello <angelo@sysam.it>
> ---
>  arch/m68k/Kconfig                   |   5 +
>  board/sysam/stmark2/Kconfig         |  15 +++
>  board/sysam/stmark2/MAINTAINERS     |   6 ++
>  board/sysam/stmark2/Makefile        |   8 ++
>  board/sysam/stmark2/sbf_dram_init.S | 119 +++++++++++++++++++++
>  board/sysam/stmark2/stmark2.c       |  47 +++++++++
>  configs/stmark2_defconfig           |  26 +++++
>  include/configs/stmark2.h           | 202 ++++++++++++++++++++++++++++++++++++
>  scripts/config_whitelist.txt        |   1 +
>  9 files changed, 429 insertions(+)
>  create mode 100644 board/sysam/stmark2/Kconfig
>  create mode 100644 board/sysam/stmark2/MAINTAINERS
>  create mode 100644 board/sysam/stmark2/Makefile
>  create mode 100644 board/sysam/stmark2/sbf_dram_init.S
>  create mode 100644 board/sysam/stmark2/stmark2.c
>  create mode 100644 configs/stmark2_defconfig
>  create mode 100644 include/configs/stmark2.h
>

[...]

> diff --git a/include/configs/stmark2.h b/include/configs/stmark2.h
> new file mode 100644
> index 0000000000..bd1f64bc8f
> --- /dev/null
> +++ b/include/configs/stmark2.h
> @@ -0,0 +1,202 @@
> +/*
> + * Sysam stmark2 board configuration
> + *
> + * (C) Copyright 2016  Angelo Dureghello <angelo@sysam.it>
> + *
> + * SPDX-License-Identifier:     GPL-2.0+
> + */
> +
> +#ifndef __STMARK2_CONFIG_H
> +#define __STMARK2_CONFIG_H
> +
> +#define CONFIG_STMARK2
> +#define CONFIG_HOSTNAME			stmark2
> +
> +#define CONFIG_MCFUART
> +#define CONFIG_SYS_UART_PORT		0
> +#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600 , 19200 , 38400 , 57600, 115200 }
> +
> +#define LDS_BOARD_TEXT 						\
> +	board/sysam/stmark2/sbf_dram_init.o (.text*)
> +
> +#define CONFIG_TIMESTAMP
> +
> +/* commands */
> +#define CONFIG_CMD_REGINFO

CMD_REGINFO is only on PowerPC 8xx, 85xx and 86xx

Christophe

> +
> +#define CONFIG_BOOTARGS						\
> +	"console=ttyS0,115200 root=/dev/ram0 rw "		\
> +		"rootfstype=ramfs "				\
> +		"rdinit=/bin/init "				\
> +		"devtmpfs.mount=1"
> +
> +#define CONFIG_BOOTCOMMAND					\
> +	"sf probe 0:1 50000000; "				\
> +	"sf read ${loadaddr} 0x100000 ${kern_size}; "		\
> +	"bootm ${loadaddr}"
> +
> +#define CONFIG_EXTRA_ENV_SETTINGS				\
> +	"kern_size=0x700000\0"					\
> +	"loadaddr=0x40001000\0"					\
> +		"-(rootfs)\0"					\
> +	"update_uboot=loady ${loadaddr}; "			\
> +		"sf probe 0:1 50000000; "			\
> +		"sf erase 0 0x80000; "				\
> +		"sf write ${loadaddr} 0 ${filesize}\0"		\
> +	"update_kernel=loady ${loadaddr}; "			\
> +		"setenv kern_size ${filesize}; saveenv; "	\
> +		"sf probe 0:1 50000000; "			\
> +		"sf erase 0x100000 0x700000; "			\
> +		"sf write ${loadaddr} 0x100000 ${filesize}\0"	\
> +	"update_rootfs=loady ${loadaddr}; "			\
> +		"sf probe 0:1 50000000; "			\
> +		"sf erase 0x00800000 0x100000; "		\
> +		"sf write ${loadaddr} 0x00800000 ${filesize}\0"	\
> +	""
> +
> +/* Realtime clock */
> +#undef CONFIG_MCFRTC
> +#define CONFIG_RTC_MCFRRTC
> +#define CONFIG_SYS_MCFRRTC_BASE		0xFC0A8000
> +
> +/* spi not partitions */
> +#define CONFIG_CMD_MTDPARTS
> +#define CONFIG_MTD_DEVICE
> +#define CONFIG_JFFS2_CMDLINE
> +#define CONFIG_JFFS2_DEV		"nor0"
> +#define MTDIDS_DEFAULT			"nor0=spi-flash.0"
> +#define MTDPARTS_DEFAULT 					\
> +	"mtdparts=spi-flash.0:" 				\
> +		"1m(u-boot),"					\
> +		"7m(kernel),"					\
> +		"-(rootfs)"
> +
> +/* Timer */
> +#define CONFIG_MCFTMR
> +#undef CONFIG_MCFPIT
> +
> +/* DSPI and Serial Flash */
> +#define CONFIG_CF_SPI
> +#define CONFIG_CF_DSPI
> +#define CONFIG_SF_DEFAULT_SPEED		50000000
> +#define CONFIG_SERIAL_FLASH
> +#define CONFIG_HARD_SPI
> +#define CONFIG_SPI_FLASH_ISSI
> +#define CONFIG_ENV_SPI_BUS		0
> +#define CONFIG_ENV_SPI_CS		1
> +
> +#define CONFIG_SYS_SBFHDR_SIZE		0x7
> +
> +#define CONFIG_SYS_DSPI_CTAR0		(DSPI_CTAR_TRSZ(7) | \
> +					DSPI_CTAR_PCSSCK_1CLK | \
> +					DSPI_CTAR_PASC(0) | \
> +					DSPI_CTAR_PDT(0) | \
> +					DSPI_CTAR_CSSCK(0) | \
> +					DSPI_CTAR_ASC(0) | \
> +					DSPI_CTAR_DT(1) | \
> +					DSPI_CTAR_BR(6))
> +#define CONFIG_SYS_DSPI_CTAR1		(CONFIG_SYS_DSPI_CTAR0)
> +#define CONFIG_SYS_DSPI_CTAR2		(CONFIG_SYS_DSPI_CTAR0)
> +
> +/* Input, PCI, Flexbus, and VCO */
> +#define CONFIG_EXTRA_CLOCK
> +
> +#define CONFIG_PRAM			2048	/* 2048 KB */
> +#define CONFIG_SYS_LONGHELP
> +#define CONFIG_AUTO_COMPLETE
> +#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
> +
> +/* Print Buffer Size */
> +#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
> +					sizeof(CONFIG_SYS_PROMPT) + 16)
> +#define CONFIG_SYS_MAXARGS		16
> +/* Boot Argument Buffer Size    */
> +#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
> +
> +#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x10000)
> +#define CONFIG_SYS_MBAR			0xFC000000
> +
> +/*
> + * Definitions for initial stack pointer and data area (in internal SRAM)
> + */
> +#define CONFIG_SYS_INIT_RAM_ADDR	0x80000000
> +/* End of used area in internal SRAM */
> +#define CONFIG_SYS_INIT_RAM_SIZE	0x10000
> +#define CONFIG_SYS_INIT_RAM_CTRL	0x221
> +#define CONFIG_SYS_GBL_DATA_OFFSET	((CONFIG_SYS_INIT_RAM_SIZE - \
> +					GENERATED_GBL_DATA_SIZE) - 32)
> +#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
> +#define CONFIG_SYS_SBFHDR_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - 32)
> +
> +/*
> + * Start addresses for the final memory configuration
> + * (Set up by the startup code)
> + * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
> + */
> +#define CONFIG_SYS_SDRAM_BASE		0x40000000
> +#define CONFIG_SYS_SDRAM_SIZE		128	/* SDRAM size in MB */
> +
> +#define CONFIG_SYS_MEMTEST_START	(CONFIG_SYS_SDRAM_BASE + 0x400)
> +#define CONFIG_SYS_MEMTEST_END		((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
> +#define CONFIG_SYS_DRAM_TEST
> +
> +#if defined(CONFIG_CF_SBF)
> +#define CONFIG_SERIAL_BOOT
> +#endif
> +
> +#if defined(CONFIG_SERIAL_BOOT)
> +#define CONFIG_SYS_MONITOR_BASE		(CONFIG_SYS_TEXT_BASE + 0x400)
> +#else
> +#define CONFIG_SYS_MONITOR_BASE		(CONFIG_SYS_FLASH_BASE + 0x400)
> +#endif
> +
> +#define CONFIG_SYS_BOOTPARAMS_LEN	(64 * 1024)
> +/* Reserve 256 kB for Monitor */
> +#define CONFIG_SYS_MONITOR_LEN		(256 << 10)
> +/* Reserve 256 kB for malloc() */
> +#define CONFIG_SYS_MALLOC_LEN		(256 << 10)
> +
> +/*
> + * For booting Linux, the board info and command line data
> + * have to be in the first 8 MB of memory, since this is
> + * the maximum mapped by the Linux kernel during initialization ??
> + */
> +/* Initial Memory map for Linux */
> +#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + \
> +					(CONFIG_SYS_SDRAM_SIZE << 20))
> +
> +/* Configuration for environment
> + * Environment is embedded in u-boot in the second sector of the flash
> + */
> +
> +#if defined(CONFIG_CF_SBF)
> +#define CONFIG_ENV_IS_IN_SPI_FLASH	1
> +#define CONFIG_ENV_SPI_CS		1
> +#define CONFIG_ENV_OFFSET		0x40000
> +#define CONFIG_ENV_SIZE			0x2000
> +#define CONFIG_ENV_SECT_SIZE		0x10000
> +#endif
> +
> +#undef CONFIG_ENV_OVERWRITE
> +
> +/* Cache Configuration */
> +#define CONFIG_SYS_CACHELINE_SIZE	16
> +#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
> +					 CONFIG_SYS_INIT_RAM_SIZE - 8)
> +#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
> +					 CONFIG_SYS_INIT_RAM_SIZE - 4)
> +#define CONFIG_SYS_ICACHE_INV		(CF_CACR_BCINVA + CF_CACR_ICINVA)
> +#define CONFIG_SYS_DCACHE_INV		(CF_CACR_DCINVA)
> +#define CONFIG_SYS_CACHE_ACR2		(CONFIG_SYS_SDRAM_BASE | \
> +					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
> +					 CF_ACR_EN | CF_ACR_SM_ALL)
> +#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_BEC | CF_CACR_IEC | \
> +					 CF_CACR_ICINVA | CF_CACR_EUSP)
> +#define CONFIG_SYS_CACHE_DCACR		((CONFIG_SYS_CACHE_ICACR | \
> +					 CF_CACR_DEC | CF_CACR_DDCM_P | \
> +					 CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
> +
> +#define CACR_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
> +					CONFIG_SYS_INIT_RAM_SIZE - 12)
> +
> +#endif /* __STMARK2_CONFIG_H */
> diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
> index e8f49ebe5d..e6faf3450e 100644
> --- a/scripts/config_whitelist.txt
> +++ b/scripts/config_whitelist.txt
> @@ -2696,6 +2696,7 @@ CONFIG_STM32_GPIO
>  CONFIG_STM32_HSE_HZ
>  CONFIG_STM32_HZ
>  CONFIG_STM32_SERIAL
> +CONFIG_STMARK2
>  CONFIG_STRESS
>  CONFIG_STRIDER
>  CONFIG_STRIDER_CON
>

---
L'absence de virus dans ce courrier électronique a été vérifiée par le logiciel antivirus Avast.
https://www.avast.com/antivirus
Bin Meng Aug. 5, 2017, 1:19 p.m. UTC | #2 
Hi Angelo,

On Sat, Jul 15, 2017 at 5:45 AM, Angelo Dureghello <angelo@sysam.it> wrote:
> Signed-off-by: Angelo Dureghello <angelo@sysam.it>

Can you please write something about your board in the commit message?

> ---
>  arch/m68k/Kconfig                   |   5 +
>  board/sysam/stmark2/Kconfig         |  15 +++
>  board/sysam/stmark2/MAINTAINERS     |   6 ++
>  board/sysam/stmark2/Makefile        |   8 ++
>  board/sysam/stmark2/sbf_dram_init.S | 119 +++++++++++++++++++++
>  board/sysam/stmark2/stmark2.c       |  47 +++++++++
>  configs/stmark2_defconfig           |  26 +++++
>  include/configs/stmark2.h           | 202 ++++++++++++++++++++++++++++++++++++
>  scripts/config_whitelist.txt        |   1 +
>  9 files changed, 429 insertions(+)
>  create mode 100644 board/sysam/stmark2/Kconfig
>  create mode 100644 board/sysam/stmark2/MAINTAINERS
>  create mode 100644 board/sysam/stmark2/Makefile
>  create mode 100644 board/sysam/stmark2/sbf_dram_init.S
>  create mode 100644 board/sysam/stmark2/stmark2.c
>  create mode 100644 configs/stmark2_defconfig
>  create mode 100644 include/configs/stmark2.h
>
> diff --git a/arch/m68k/Kconfig b/arch/m68k/Kconfig
> index 26509b73c6..42fb91539a 100644
> --- a/arch/m68k/Kconfig
> +++ b/arch/m68k/Kconfig
> @@ -200,6 +200,10 @@ config TARGET_AMCORE
>         bool "Support AMCORE"
>         select M5307
>
> +config TARGET_STMARK2
> +        bool "Support stmark2"
> +        select M54418
> +
>  endchoice
>
>  source "board/BuS/eb_cpu5282/Kconfig"
> @@ -223,5 +227,6 @@ source "board/freescale/m54455evb/Kconfig"
>  source "board/freescale/m547xevb/Kconfig"
>  source "board/freescale/m548xevb/Kconfig"
>  source "board/sysam/amcore/Kconfig"
> +source "board/sysam/stmark2/Kconfig"
>
>  endmenu
> diff --git a/board/sysam/stmark2/Kconfig b/board/sysam/stmark2/Kconfig
> new file mode 100644
> index 0000000000..87ab7ab7b5
> --- /dev/null
> +++ b/board/sysam/stmark2/Kconfig
> @@ -0,0 +1,15 @@
> +if TARGET_STMARK2
> +
> +config SYS_CPU
> +       default "mcf5445x"
> +
> +config SYS_BOARD
> +       default "stmark2"
> +
> +config SYS_VENDOR
> +       default "sysam"
> +
> +config SYS_CONFIG_NAME
> +       default "stmark2"
> +
> +endif
> diff --git a/board/sysam/stmark2/MAINTAINERS b/board/sysam/stmark2/MAINTAINERS
> new file mode 100644
> index 0000000000..b87f432bb3
> --- /dev/null
> +++ b/board/sysam/stmark2/MAINTAINERS
> @@ -0,0 +1,6 @@
> +STMARK2 BOARD
> +M:     Angelo Dureghello <angelo@sysam.it>
> +S:     Maintained
> +F:     board/sysam/stmark2/
> +F:     include/configs/stmark2.h
> +F:     configs/stmark2_defconfig
> diff --git a/board/sysam/stmark2/Makefile b/board/sysam/stmark2/Makefile
> new file mode 100644
> index 0000000000..064a57ea05
> --- /dev/null
> +++ b/board/sysam/stmark2/Makefile
> @@ -0,0 +1,8 @@
> +#
> +# (C) Copyright 2014  Angelo Dureghello <angelo@sysam.it>
> +#
> +# SPDX-License-Identifier:     GPL-2.0+
> +#
> +
> +obj-y = stmark2.o
> +extra-y += sbf_dram_init.o
> diff --git a/board/sysam/stmark2/sbf_dram_init.S b/board/sysam/stmark2/sbf_dram_init.S
> new file mode 100644
> index 0000000000..52abda5c3c
> --- /dev/null
> +++ b/board/sysam/stmark2/sbf_dram_init.S
> @@ -0,0 +1,119 @@
> +/*
> + * Board-specific early ddr/sdram init.
> + *
> + * (C) Copyright 2017 Angelo Dureghello <angelo@sysam.it>
> + *
> + * SPDX-License-Identifier:    GPL-2.0+
> + */
> +
> +.equ   PPMCR0,         0xfc04002d
> +.equ   MSCR_SDRAMC,    0xec094060
> +.equ   MISCCR2,        0xec09001a
> +.equ   DDR_RCR,        0xfc0b8180
> +.equ   DDR_PADCR,      0xfc0b81ac
> +.equ   DDR_CR00,       0xfc0b8000
> +.equ   DDR_CR06,       0xfc0b8018
> +.equ   DDR_CR09,       0xfc0b8024
> +.equ   DDR_CR40,       0xfc0b80a0
> +.equ   DDR_CR45,       0xfc0b80b4
> +.equ   DDR_CR56,       0xfc0b80e0
> +
> +.global sbf_dram_init
> +.text
> +
> +sbf_dram_init:
> +       /* CD46 = DDR on */
> +       move.l  #PPMCR0, %a1
> +       move.b  #46, (%a1)
> +
> +       /* stmark 2, max drive strength */
> +       move.l  #MSCR_SDRAMC, %a1
> +       move.b  #1, (%a1)
> +
> +       /*
> +        * use cpu clock, seems more realiable
> +        *
> +        * DDR2 clock is serviced from DDR controller as input clock / 2
> +        * so, if clock comes from
> +        *   vco, i.e. 480(vco) / 2, so ddr clock is 240 Mhz (measured)
> +        *   cpu, i.e. 250(cpu) / 2, so ddr clock is 125 Mhz (measured)
> +        *
> +        *     .
> +        *    / \    DDR2 can't be clocked lower than 125Mhz
> +        *   / ! \   DDR2 init must pass further i/dcache enable test
> +        *  /_____\
> +        *  WARNING
> +        */
> +
> +       /* cpu / 2 = 125 Mhz for 480 Mhz pll */
> +       move.l  #MISCCR2, %a1
> +       move.w  #0xa01d, (%a1)
> +
> +       /* DDR force sw reset settings */
> +       move.l  #DDR_RCR, %a1
> +       move.l  #0x00000000, (%a1)
> +       move.l  #0x40000000, (%a1)
> +
> +       /*
> +        * PAD_ODT_CS: for us seems both 1(75 ohm) and 2(150ohm) are good,
> +        * 500/700 mV are ok
> +        */
> +       move.l  #DDR_PADCR, %a1
> +       move.l  #0x01030203, (%a1)      /* as freescale tower */
> +
> +       move.l  #DDR_CR00, %a1
> +       move.l  #0x01010101, (%a1)+     /* 0x00 */
> +       move.l  #0x00000101, (%a1)+     /* 0x04 */
> +       move.l  #0x01010100, (%a1)+     /* 0x08 */
> +       move.l  #0x01010000, (%a1)+     /* 0x0C */
> +       move.l  #0x00010101, (%a1)+     /* 0x10 */
> +       move.l  #DDR_CR06, %a1
> +       move.l  #0x00010100, (%a1)+     /* 0x18 */
> +       move.l  #0x00000001, (%a1)+     /* 0x1C */
> +       move.l  #0x01000001, (%a1)+     /* 0x20 */
> +       move.l  #0x00000100, (%a1)+     /* 0x24 */
> +       move.l  #0x00010001, (%a1)+     /* 0x28 */
> +       move.l  #0x00000200, (%a1)+     /* 0x2C */
> +       move.l  #0x01000002, (%a1)+     /* 0x30 */
> +       move.l  #0x00000000, (%a1)+     /* 0x34 */
> +       move.l  #0x00000100, (%a1)+     /* 0x38 */
> +       move.l  #0x02000100, (%a1)+     /* 0x3C */
> +       move.l  #0x02000407, (%a1)+     /* 0x40 */
> +       move.l  #0x02030007, (%a1)+     /* 0x44 */
> +       move.l  #0x02000100, (%a1)+     /* 0x48 */
> +       move.l  #0x0A030203, (%a1)+     /* 0x4C */
> +       move.l  #0x00020708, (%a1)+     /* 0x50 */
> +       move.l  #0x00050008, (%a1)+     /* 0x54 */
> +       move.l  #0x04030002, (%a1)+     /* 0x58 */
> +       move.l  #0x00000004, (%a1)+     /* 0x5C */
> +       move.l  #0x020A0000, (%a1)+     /* 0x60 */
> +       move.l  #0x0C00000E, (%a1)+     /* 0x64 */
> +       move.l  #0x00002004, (%a1)+     /* 0x68 */
> +       move.l  #0x00000000, (%a1)+     /* 0x6C */
> +       move.l  #0x00100010, (%a1)+     /* 0x70 */
> +       move.l  #0x00100010, (%a1)+     /* 0x74 */
> +       move.l  #0x00000000, (%a1)+     /* 0x78 */
> +       move.l  #0x07990000, (%a1)+     /* 0x7C */
> +       move.l  #DDR_CR40, %a1
> +       move.l  #0x00000000, (%a1)+     /* 0xA0 */
> +       move.l  #0x00C80064, (%a1)+     /* 0xA4 */
> +       move.l  #0x44520002, (%a1)+     /* 0xA8 */
> +       move.l  #0x00C80023, (%a1)+     /* 0xAC */
> +       move.l  #DDR_CR45, %a1
> +       move.l  #0x0000C350, (%a1)      /* 0xB4 */
> +       move.l  #DDR_CR56, %a1
> +       move.l  #0x04000000, (%a1)+     /* 0xE0 */
> +       move.l  #0x03000304, (%a1)+     /* 0xE4 */
> +       move.l  #0x40040000, (%a1)+     /* 0xE8 */
> +       move.l  #0xC0004004, (%a1)+     /* 0xEC */
> +       move.l  #0x0642C000, (%a1)+     /* 0xF0 */
> +       move.l  #0x00000642, (%a1)+     /* 0xF4 */
> +       move.l  #DDR_CR09, %a1
> +       tpf
> +       move.l  #0x01000100, (%a1)      /* 0x24 */
> +
> +       move.l  #0x2000, %d1
> +       bsr     asm_delay
> +
> +
> +       rts
> diff --git a/board/sysam/stmark2/stmark2.c b/board/sysam/stmark2/stmark2.c
> new file mode 100644
> index 0000000000..4f291ab6d6
> --- /dev/null
> +++ b/board/sysam/stmark2/stmark2.c
> @@ -0,0 +1,47 @@
> +/*
> + * Board-specific init.
> + *
> + * (C) Copyright 2017 Angelo Dureghello <angelo@sysam.it>
> + *
> + * SPDX-License-Identifier:    GPL-2.0+
> + */
> +
> +#include <common.h>
> +#include <spi.h>
> +#include <asm/io.h>
> +#include <asm/immap.h>
> +#include <mmc.h>
> +#include <fsl_esdhc.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +int checkboard(void)
> +{
> +       /*
> +        * need to to:
> +        * Check serial flash size. if 2mb evb, else 8mb demo
> +        */
> +       puts("Board: ");
> +       puts("Sysam stmark2\n");
> +       return 0;
> +}
> +
> +int dram_init(void)
> +{
> +       u32 dramsize;
> +
> +       /*
> +        * Serial Boot: The dram is already initialized in start.S
> +        * only require to return DRAM size
> +        */
> +       dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
> +
> +       gd->ram_size = dramsize;
> +
> +       return 0;
> +}
> +
> +int testdram(void)
> +{
> +       return 0;
> +}
> diff --git a/configs/stmark2_defconfig b/configs/stmark2_defconfig
> new file mode 100644
> index 0000000000..cf3625c281
> --- /dev/null
> +++ b/configs/stmark2_defconfig
> @@ -0,0 +1,26 @@
> +CONFIG_M68K=y
> +CONFIG_SYS_TEXT_BASE=0x47E00000
> +CONFIG_TARGET_STMARK2=y
> +CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_SERIAL_BOOT,SYS_INPUT_CLKSRC=30000000"
> +# CONFIG_DISPLAY_BOARDINFO is not set
> +# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
> +CONFIG_HUSH_PARSER=y
> +CONFIG_SYS_PROMPT="stmark2 $ "
> +# CONFIG_CMD_BDI is not set
> +# CONFIG_CMD_CONSOLE is not set
> +# CONFIG_CMD_IMLS is not set
> +# CONFIG_CMD_EXPORTENV is not set
> +# CONFIG_CMD_IMPORTENV is not set
> +CONFIG_CMD_LOADB=y
> +# CONFIG_CMD_LOADS is not set
> +# CONFIG_CMD_FLASH is not set
> +CONFIG_CMD_SF=y
> +CONFIG_CMD_SPI=y
> +# CONFIG_CMD_FPGA is not set
> +# CONFIG_CMD_SETEXPR is not set
> +# CONFIG_CMD_NET is not set
> +# CONFIG_CMD_NFS is not set
> +CONFIG_CMD_CACHE=y
> +CONFIG_SPI_FLASH=y
> +CONFIG_SPI_FLASH_MTD=y
> +CONFIG_REGEX=y
> diff --git a/include/configs/stmark2.h b/include/configs/stmark2.h
> new file mode 100644
> index 0000000000..bd1f64bc8f
> --- /dev/null
> +++ b/include/configs/stmark2.h
> @@ -0,0 +1,202 @@
> +/*
> + * Sysam stmark2 board configuration
> + *
> + * (C) Copyright 2016  Angelo Dureghello <angelo@sysam.it>
> + *
> + * SPDX-License-Identifier:     GPL-2.0+
> + */
> +
> +#ifndef __STMARK2_CONFIG_H
> +#define __STMARK2_CONFIG_H
> +
> +#define CONFIG_STMARK2
> +#define CONFIG_HOSTNAME                        stmark2
> +
> +#define CONFIG_MCFUART
> +#define CONFIG_SYS_UART_PORT           0
> +#define CONFIG_SYS_BAUDRATE_TABLE      { 9600 , 19200 , 38400 , 57600, 115200 }
> +
> +#define LDS_BOARD_TEXT                                                 \
> +       board/sysam/stmark2/sbf_dram_init.o (.text*)
> +
> +#define CONFIG_TIMESTAMP
> +
> +/* commands */
> +#define CONFIG_CMD_REGINFO
> +
> +#define CONFIG_BOOTARGS                                                \
> +       "console=ttyS0,115200 root=/dev/ram0 rw "               \
> +               "rootfstype=ramfs "                             \
> +               "rdinit=/bin/init "                             \
> +               "devtmpfs.mount=1"
> +
> +#define CONFIG_BOOTCOMMAND                                     \
> +       "sf probe 0:1 50000000; "                               \
> +       "sf read ${loadaddr} 0x100000 ${kern_size}; "           \
> +       "bootm ${loadaddr}"
> +
> +#define CONFIG_EXTRA_ENV_SETTINGS                              \
> +       "kern_size=0x700000\0"                                  \
> +       "loadaddr=0x40001000\0"                                 \
> +               "-(rootfs)\0"                                   \
> +       "update_uboot=loady ${loadaddr}; "                      \
> +               "sf probe 0:1 50000000; "                       \
> +               "sf erase 0 0x80000; "                          \
> +               "sf write ${loadaddr} 0 ${filesize}\0"          \
> +       "update_kernel=loady ${loadaddr}; "                     \
> +               "setenv kern_size ${filesize}; saveenv; "       \
> +               "sf probe 0:1 50000000; "                       \
> +               "sf erase 0x100000 0x700000; "                  \
> +               "sf write ${loadaddr} 0x100000 ${filesize}\0"   \
> +       "update_rootfs=loady ${loadaddr}; "                     \
> +               "sf probe 0:1 50000000; "                       \
> +               "sf erase 0x00800000 0x100000; "                \
> +               "sf write ${loadaddr} 0x00800000 ${filesize}\0" \
> +       ""
> +
> +/* Realtime clock */
> +#undef CONFIG_MCFRTC
> +#define CONFIG_RTC_MCFRRTC
> +#define CONFIG_SYS_MCFRRTC_BASE                0xFC0A8000
> +
> +/* spi not partitions */
> +#define CONFIG_CMD_MTDPARTS
> +#define CONFIG_MTD_DEVICE
> +#define CONFIG_JFFS2_CMDLINE
> +#define CONFIG_JFFS2_DEV               "nor0"
> +#define MTDIDS_DEFAULT                 "nor0=spi-flash.0"
> +#define MTDPARTS_DEFAULT                                       \
> +       "mtdparts=spi-flash.0:"                                 \
> +               "1m(u-boot),"                                   \
> +               "7m(kernel),"                                   \
> +               "-(rootfs)"
> +
> +/* Timer */
> +#define CONFIG_MCFTMR
> +#undef CONFIG_MCFPIT
> +
> +/* DSPI and Serial Flash */
> +#define CONFIG_CF_SPI
> +#define CONFIG_CF_DSPI
> +#define CONFIG_SF_DEFAULT_SPEED                50000000
> +#define CONFIG_SERIAL_FLASH
> +#define CONFIG_HARD_SPI
> +#define CONFIG_SPI_FLASH_ISSI
> +#define CONFIG_ENV_SPI_BUS             0
> +#define CONFIG_ENV_SPI_CS              1
> +
> +#define CONFIG_SYS_SBFHDR_SIZE         0x7
> +
> +#define CONFIG_SYS_DSPI_CTAR0          (DSPI_CTAR_TRSZ(7) | \
> +                                       DSPI_CTAR_PCSSCK_1CLK | \
> +                                       DSPI_CTAR_PASC(0) | \
> +                                       DSPI_CTAR_PDT(0) | \
> +                                       DSPI_CTAR_CSSCK(0) | \
> +                                       DSPI_CTAR_ASC(0) | \
> +                                       DSPI_CTAR_DT(1) | \
> +                                       DSPI_CTAR_BR(6))
> +#define CONFIG_SYS_DSPI_CTAR1          (CONFIG_SYS_DSPI_CTAR0)
> +#define CONFIG_SYS_DSPI_CTAR2          (CONFIG_SYS_DSPI_CTAR0)
> +
> +/* Input, PCI, Flexbus, and VCO */
> +#define CONFIG_EXTRA_CLOCK
> +
> +#define CONFIG_PRAM                    2048    /* 2048 KB */
> +#define CONFIG_SYS_LONGHELP
> +#define CONFIG_AUTO_COMPLETE
> +#define CONFIG_SYS_CBSIZE              256     /* Console I/O Buffer Size */
> +
> +/* Print Buffer Size */
> +#define CONFIG_SYS_PBSIZE              (CONFIG_SYS_CBSIZE + \
> +                                       sizeof(CONFIG_SYS_PROMPT) + 16)
> +#define CONFIG_SYS_MAXARGS             16
> +/* Boot Argument Buffer Size    */
> +#define CONFIG_SYS_BARGSIZE            CONFIG_SYS_CBSIZE
> +
> +#define CONFIG_SYS_LOAD_ADDR           (CONFIG_SYS_SDRAM_BASE + 0x10000)
> +#define CONFIG_SYS_MBAR                        0xFC000000
> +
> +/*
> + * Definitions for initial stack pointer and data area (in internal SRAM)
> + */
> +#define CONFIG_SYS_INIT_RAM_ADDR       0x80000000
> +/* End of used area in internal SRAM */
> +#define CONFIG_SYS_INIT_RAM_SIZE       0x10000
> +#define CONFIG_SYS_INIT_RAM_CTRL       0x221
> +#define CONFIG_SYS_GBL_DATA_OFFSET     ((CONFIG_SYS_INIT_RAM_SIZE - \
> +                                       GENERATED_GBL_DATA_SIZE) - 32)
> +#define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
> +#define CONFIG_SYS_SBFHDR_DATA_OFFSET  (CONFIG_SYS_INIT_RAM_SIZE - 32)
> +
> +/*
> + * Start addresses for the final memory configuration
> + * (Set up by the startup code)
> + * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
> + */
> +#define CONFIG_SYS_SDRAM_BASE          0x40000000
> +#define CONFIG_SYS_SDRAM_SIZE          128     /* SDRAM size in MB */
> +
> +#define CONFIG_SYS_MEMTEST_START       (CONFIG_SYS_SDRAM_BASE + 0x400)
> +#define CONFIG_SYS_MEMTEST_END         ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
> +#define CONFIG_SYS_DRAM_TEST
> +
> +#if defined(CONFIG_CF_SBF)
> +#define CONFIG_SERIAL_BOOT
> +#endif
> +
> +#if defined(CONFIG_SERIAL_BOOT)
> +#define CONFIG_SYS_MONITOR_BASE                (CONFIG_SYS_TEXT_BASE + 0x400)
> +#else
> +#define CONFIG_SYS_MONITOR_BASE                (CONFIG_SYS_FLASH_BASE + 0x400)
> +#endif
> +
> +#define CONFIG_SYS_BOOTPARAMS_LEN      (64 * 1024)
> +/* Reserve 256 kB for Monitor */
> +#define CONFIG_SYS_MONITOR_LEN         (256 << 10)
> +/* Reserve 256 kB for malloc() */
> +#define CONFIG_SYS_MALLOC_LEN          (256 << 10)
> +
> +/*
> + * For booting Linux, the board info and command line data
> + * have to be in the first 8 MB of memory, since this is
> + * the maximum mapped by the Linux kernel during initialization ??
> + */
> +/* Initial Memory map for Linux */
> +#define CONFIG_SYS_BOOTMAPSZ           (CONFIG_SYS_SDRAM_BASE + \
> +                                       (CONFIG_SYS_SDRAM_SIZE << 20))
> +
> +/* Configuration for environment
> + * Environment is embedded in u-boot in the second sector of the flash
> + */
> +
> +#if defined(CONFIG_CF_SBF)
> +#define CONFIG_ENV_IS_IN_SPI_FLASH     1

This is now in Kconfig.

> +#define CONFIG_ENV_SPI_CS              1
> +#define CONFIG_ENV_OFFSET              0x40000
> +#define CONFIG_ENV_SIZE                        0x2000
> +#define CONFIG_ENV_SECT_SIZE           0x10000
> +#endif
> +
> +#undef CONFIG_ENV_OVERWRITE
> +
> +/* Cache Configuration */
> +#define CONFIG_SYS_CACHELINE_SIZE      16
> +#define ICACHE_STATUS                  (CONFIG_SYS_INIT_RAM_ADDR + \
> +                                        CONFIG_SYS_INIT_RAM_SIZE - 8)
> +#define DCACHE_STATUS                  (CONFIG_SYS_INIT_RAM_ADDR + \
> +                                        CONFIG_SYS_INIT_RAM_SIZE - 4)
> +#define CONFIG_SYS_ICACHE_INV          (CF_CACR_BCINVA + CF_CACR_ICINVA)
> +#define CONFIG_SYS_DCACHE_INV          (CF_CACR_DCINVA)
> +#define CONFIG_SYS_CACHE_ACR2          (CONFIG_SYS_SDRAM_BASE | \
> +                                        CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
> +                                        CF_ACR_EN | CF_ACR_SM_ALL)
> +#define CONFIG_SYS_CACHE_ICACR         (CF_CACR_BEC | CF_CACR_IEC | \
> +                                        CF_CACR_ICINVA | CF_CACR_EUSP)
> +#define CONFIG_SYS_CACHE_DCACR         ((CONFIG_SYS_CACHE_ICACR | \
> +                                        CF_CACR_DEC | CF_CACR_DDCM_P | \
> +                                        CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
> +
> +#define CACR_STATUS                    (CONFIG_SYS_INIT_RAM_ADDR + \
> +                                       CONFIG_SYS_INIT_RAM_SIZE - 12)
> +
> +#endif /* __STMARK2_CONFIG_H */
> diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
> index e8f49ebe5d..e6faf3450e 100644
> --- a/scripts/config_whitelist.txt
> +++ b/scripts/config_whitelist.txt
> @@ -2696,6 +2696,7 @@ CONFIG_STM32_GPIO
>  CONFIG_STM32_HSE_HZ
>  CONFIG_STM32_HZ
>  CONFIG_STM32_SERIAL
> +CONFIG_STMARK2

We should stop adding ad-hoc CONFIG_xxx. Please use Kconfig.

>  CONFIG_STRESS
>  CONFIG_STRIDER
>  CONFIG_STRIDER_CON
> --

Regards,
Bin
Angelo Dureghello Aug. 6, 2017, 7:52 p.m. UTC | #3 
Hi Christophe,

On 05/08/2017 14:58, christophe leroy wrote:
> 
> 
> Le 14/07/2017 à 23:45, Angelo Dureghello a écrit :
>> Signed-off-by: Angelo Dureghello <angelo@sysam.it>
>> ---
>>  arch/m68k/Kconfig                   |   5 +
>>  board/sysam/stmark2/Kconfig         |  15 +++
>>  board/sysam/stmark2/MAINTAINERS     |   6 ++
>>  board/sysam/stmark2/Makefile        |   8 ++
>>  board/sysam/stmark2/sbf_dram_init.S | 119 +++++++++++++++++++++
>>  board/sysam/stmark2/stmark2.c       |  47 +++++++++
>>  configs/stmark2_defconfig           |  26 +++++
>>  include/configs/stmark2.h           | 202 ++++++++++++++++++++++++++++++++++++
>>  scripts/config_whitelist.txt        |   1 +
>>  9 files changed, 429 insertions(+)
>>  create mode 100644 board/sysam/stmark2/Kconfig
>>  create mode 100644 board/sysam/stmark2/MAINTAINERS
>>  create mode 100644 board/sysam/stmark2/Makefile
>>  create mode 100644 board/sysam/stmark2/sbf_dram_init.S
>>  create mode 100644 board/sysam/stmark2/stmark2.c
>>  create mode 100644 configs/stmark2_defconfig
>>  create mode 100644 include/configs/stmark2.h
>>
> 
> [...]
> 
>> diff --git a/include/configs/stmark2.h b/include/configs/stmark2.h
>> new file mode 100644
>> index 0000000000..bd1f64bc8f
>> --- /dev/null
>> +++ b/include/configs/stmark2.h
>> @@ -0,0 +1,202 @@
>> +/*
>> + * Sysam stmark2 board configuration
>> + *
>> + * (C) Copyright 2016  Angelo Dureghello <angelo@sysam.it>
>> + *
>> + * SPDX-License-Identifier:     GPL-2.0+
>> + */
>> +
>> +#ifndef __STMARK2_CONFIG_H
>> +#define __STMARK2_CONFIG_H
>> +
>> +#define CONFIG_STMARK2
>> +#define CONFIG_HOSTNAME            stmark2
>> +
>> +#define CONFIG_MCFUART
>> +#define CONFIG_SYS_UART_PORT        0
>> +#define CONFIG_SYS_BAUDRATE_TABLE    { 9600 , 19200 , 38400 , 57600, 115200 }
>> +
>> +#define LDS_BOARD_TEXT                         \
>> +    board/sysam/stmark2/sbf_dram_init.o (.text*)
>> +
>> +#define CONFIG_TIMESTAMP
>> +
>> +/* commands */
>> +#define CONFIG_CMD_REGINFO
> 
> CMD_REGINFO is only on PowerPC 8xx, 85xx and 86xx
> 

thanks, checking / fixing.

> Christophe
> 
>> +
>> +#define CONFIG_BOOTARGS                        \
>> +    "console=ttyS0,115200 root=/dev/ram0 rw "        \
>> +        "rootfstype=ramfs "                \
>> +        "rdinit=/bin/init "                \
>> +        "devtmpfs.mount=1"
>> +
>> +#define CONFIG_BOOTCOMMAND                    \
>> +    "sf probe 0:1 50000000; "                \
>> +    "sf read ${loadaddr} 0x100000 ${kern_size}; "        \
>> +    "bootm ${loadaddr}"
>> +
>> +#define CONFIG_EXTRA_ENV_SETTINGS                \
>> +    "kern_size=0x700000\0"                    \
>> +    "loadaddr=0x40001000\0"                    \
>> +        "-(rootfs)\0"                    \
>> +    "update_uboot=loady ${loadaddr}; "            \
>> +        "sf probe 0:1 50000000; "            \
>> +        "sf erase 0 0x80000; "                \
>> +        "sf write ${loadaddr} 0 ${filesize}\0"        \
>> +    "update_kernel=loady ${loadaddr}; "            \
>> +        "setenv kern_size ${filesize}; saveenv; "    \
>> +        "sf probe 0:1 50000000; "            \
>> +        "sf erase 0x100000 0x700000; "            \
>> +        "sf write ${loadaddr} 0x100000 ${filesize}\0"    \
>> +    "update_rootfs=loady ${loadaddr}; "            \
>> +        "sf probe 0:1 50000000; "            \
>> +        "sf erase 0x00800000 0x100000; "        \
>> +        "sf write ${loadaddr} 0x00800000 ${filesize}\0"    \
>> +    ""
>> +
>> +/* Realtime clock */
>> +#undef CONFIG_MCFRTC
>> +#define CONFIG_RTC_MCFRRTC
>> +#define CONFIG_SYS_MCFRRTC_BASE        0xFC0A8000
>> +
>> +/* spi not partitions */
>> +#define CONFIG_CMD_MTDPARTS
>> +#define CONFIG_MTD_DEVICE
>> +#define CONFIG_JFFS2_CMDLINE
>> +#define CONFIG_JFFS2_DEV        "nor0"
>> +#define MTDIDS_DEFAULT            "nor0=spi-flash.0"
>> +#define MTDPARTS_DEFAULT                     \
>> +    "mtdparts=spi-flash.0:"                 \
>> +        "1m(u-boot),"                    \
>> +        "7m(kernel),"                    \
>> +        "-(rootfs)"
>> +
>> +/* Timer */
>> +#define CONFIG_MCFTMR
>> +#undef CONFIG_MCFPIT
>> +
>> +/* DSPI and Serial Flash */
>> +#define CONFIG_CF_SPI
>> +#define CONFIG_CF_DSPI
>> +#define CONFIG_SF_DEFAULT_SPEED        50000000
>> +#define CONFIG_SERIAL_FLASH
>> +#define CONFIG_HARD_SPI
>> +#define CONFIG_SPI_FLASH_ISSI
>> +#define CONFIG_ENV_SPI_BUS        0
>> +#define CONFIG_ENV_SPI_CS        1
>> +
>> +#define CONFIG_SYS_SBFHDR_SIZE        0x7
>> +
>> +#define CONFIG_SYS_DSPI_CTAR0        (DSPI_CTAR_TRSZ(7) | \
>> +                    DSPI_CTAR_PCSSCK_1CLK | \
>> +                    DSPI_CTAR_PASC(0) | \
>> +                    DSPI_CTAR_PDT(0) | \
>> +                    DSPI_CTAR_CSSCK(0) | \
>> +                    DSPI_CTAR_ASC(0) | \
>> +                    DSPI_CTAR_DT(1) | \
>> +                    DSPI_CTAR_BR(6))
>> +#define CONFIG_SYS_DSPI_CTAR1        (CONFIG_SYS_DSPI_CTAR0)
>> +#define CONFIG_SYS_DSPI_CTAR2        (CONFIG_SYS_DSPI_CTAR0)
>> +
>> +/* Input, PCI, Flexbus, and VCO */
>> +#define CONFIG_EXTRA_CLOCK
>> +
>> +#define CONFIG_PRAM            2048    /* 2048 KB */
>> +#define CONFIG_SYS_LONGHELP
>> +#define CONFIG_AUTO_COMPLETE
>> +#define CONFIG_SYS_CBSIZE        256    /* Console I/O Buffer Size */
>> +
>> +/* Print Buffer Size */
>> +#define CONFIG_SYS_PBSIZE        (CONFIG_SYS_CBSIZE + \
>> +                    sizeof(CONFIG_SYS_PROMPT) + 16)
>> +#define CONFIG_SYS_MAXARGS        16
>> +/* Boot Argument Buffer Size    */
>> +#define CONFIG_SYS_BARGSIZE        CONFIG_SYS_CBSIZE
>> +
>> +#define CONFIG_SYS_LOAD_ADDR        (CONFIG_SYS_SDRAM_BASE + 0x10000)
>> +#define CONFIG_SYS_MBAR            0xFC000000
>> +
>> +/*
>> + * Definitions for initial stack pointer and data area (in internal SRAM)
>> + */
>> +#define CONFIG_SYS_INIT_RAM_ADDR    0x80000000
>> +/* End of used area in internal SRAM */
>> +#define CONFIG_SYS_INIT_RAM_SIZE    0x10000
>> +#define CONFIG_SYS_INIT_RAM_CTRL    0x221
>> +#define CONFIG_SYS_GBL_DATA_OFFSET    ((CONFIG_SYS_INIT_RAM_SIZE - \
>> +                    GENERATED_GBL_DATA_SIZE) - 32)
>> +#define CONFIG_SYS_INIT_SP_OFFSET    CONFIG_SYS_GBL_DATA_OFFSET
>> +#define CONFIG_SYS_SBFHDR_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - 32)
>> +
>> +/*
>> + * Start addresses for the final memory configuration
>> + * (Set up by the startup code)
>> + * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
>> + */
>> +#define CONFIG_SYS_SDRAM_BASE        0x40000000
>> +#define CONFIG_SYS_SDRAM_SIZE        128    /* SDRAM size in MB */
>> +
>> +#define CONFIG_SYS_MEMTEST_START    (CONFIG_SYS_SDRAM_BASE + 0x400)
>> +#define CONFIG_SYS_MEMTEST_END        ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
>> +#define CONFIG_SYS_DRAM_TEST
>> +
>> +#if defined(CONFIG_CF_SBF)
>> +#define CONFIG_SERIAL_BOOT
>> +#endif
>> +
>> +#if defined(CONFIG_SERIAL_BOOT)
>> +#define CONFIG_SYS_MONITOR_BASE        (CONFIG_SYS_TEXT_BASE + 0x400)
>> +#else
>> +#define CONFIG_SYS_MONITOR_BASE        (CONFIG_SYS_FLASH_BASE + 0x400)
>> +#endif
>> +
>> +#define CONFIG_SYS_BOOTPARAMS_LEN    (64 * 1024)
>> +/* Reserve 256 kB for Monitor */
>> +#define CONFIG_SYS_MONITOR_LEN        (256 << 10)
>> +/* Reserve 256 kB for malloc() */
>> +#define CONFIG_SYS_MALLOC_LEN        (256 << 10)
>> +
>> +/*
>> + * For booting Linux, the board info and command line data
>> + * have to be in the first 8 MB of memory, since this is
>> + * the maximum mapped by the Linux kernel during initialization ??
>> + */
>> +/* Initial Memory map for Linux */
>> +#define CONFIG_SYS_BOOTMAPSZ        (CONFIG_SYS_SDRAM_BASE + \
>> +                    (CONFIG_SYS_SDRAM_SIZE << 20))
>> +
>> +/* Configuration for environment
>> + * Environment is embedded in u-boot in the second sector of the flash
>> + */
>> +
>> +#if defined(CONFIG_CF_SBF)
>> +#define CONFIG_ENV_IS_IN_SPI_FLASH    1
>> +#define CONFIG_ENV_SPI_CS        1
>> +#define CONFIG_ENV_OFFSET        0x40000
>> +#define CONFIG_ENV_SIZE            0x2000
>> +#define CONFIG_ENV_SECT_SIZE        0x10000
>> +#endif
>> +
>> +#undef CONFIG_ENV_OVERWRITE
>> +
>> +/* Cache Configuration */
>> +#define CONFIG_SYS_CACHELINE_SIZE    16
>> +#define ICACHE_STATUS            (CONFIG_SYS_INIT_RAM_ADDR + \
>> +                     CONFIG_SYS_INIT_RAM_SIZE - 8)
>> +#define DCACHE_STATUS            (CONFIG_SYS_INIT_RAM_ADDR + \
>> +                     CONFIG_SYS_INIT_RAM_SIZE - 4)
>> +#define CONFIG_SYS_ICACHE_INV        (CF_CACR_BCINVA + CF_CACR_ICINVA)
>> +#define CONFIG_SYS_DCACHE_INV        (CF_CACR_DCINVA)
>> +#define CONFIG_SYS_CACHE_ACR2        (CONFIG_SYS_SDRAM_BASE | \
>> +                     CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
>> +                     CF_ACR_EN | CF_ACR_SM_ALL)
>> +#define CONFIG_SYS_CACHE_ICACR        (CF_CACR_BEC | CF_CACR_IEC | \
>> +                     CF_CACR_ICINVA | CF_CACR_EUSP)
>> +#define CONFIG_SYS_CACHE_DCACR        ((CONFIG_SYS_CACHE_ICACR | \
>> +                     CF_CACR_DEC | CF_CACR_DDCM_P | \
>> +                     CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
>> +
>> +#define CACR_STATUS            (CONFIG_SYS_INIT_RAM_ADDR + \
>> +                    CONFIG_SYS_INIT_RAM_SIZE - 12)
>> +
>> +#endif /* __STMARK2_CONFIG_H */
>> diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
>> index e8f49ebe5d..e6faf3450e 100644
>> --- a/scripts/config_whitelist.txt
>> +++ b/scripts/config_whitelist.txt
>> @@ -2696,6 +2696,7 @@ CONFIG_STM32_GPIO
>>  CONFIG_STM32_HSE_HZ
>>  CONFIG_STM32_HZ
>>  CONFIG_STM32_SERIAL
>> +CONFIG_STMARK2
>>  CONFIG_STRESS
>>  CONFIG_STRIDER
>>  CONFIG_STRIDER_CON
>>
> 
> ---
> L'absence de virus dans ce courrier électronique a été vérifiée par le logiciel antivirus Avast.
> https://www.avast.com/antivirus
> 

Regards,
Angelo Dureghello
Angelo Dureghello Aug. 6, 2017, 7:53 p.m. UTC | #4 
Hi Bin,

On 05/08/2017 15:19, Bin Meng wrote:
> Hi Angelo,
> 
> On Sat, Jul 15, 2017 at 5:45 AM, Angelo Dureghello <angelo@sysam.it> wrote:
>> Signed-off-by: Angelo Dureghello <angelo@sysam.it>
> 
> Can you please write something about your board in the commit message?

sure, sending patch v2.

> 
>> ---
>>   arch/m68k/Kconfig                   |   5 +
>>   board/sysam/stmark2/Kconfig         |  15 +++
>>   board/sysam/stmark2/MAINTAINERS     |   6 ++
>>   board/sysam/stmark2/Makefile        |   8 ++
>>   board/sysam/stmark2/sbf_dram_init.S | 119 +++++++++++++++++++++
>>   board/sysam/stmark2/stmark2.c       |  47 +++++++++
>>   configs/stmark2_defconfig           |  26 +++++
>>   include/configs/stmark2.h           | 202 ++++++++++++++++++++++++++++++++++++
>>   scripts/config_whitelist.txt        |   1 +
>>   9 files changed, 429 insertions(+)
>>   create mode 100644 board/sysam/stmark2/Kconfig
>>   create mode 100644 board/sysam/stmark2/MAINTAINERS
>>   create mode 100644 board/sysam/stmark2/Makefile
>>   create mode 100644 board/sysam/stmark2/sbf_dram_init.S
>>   create mode 100644 board/sysam/stmark2/stmark2.c
>>   create mode 100644 configs/stmark2_defconfig
>>   create mode 100644 include/configs/stmark2.h
>>
>> diff --git a/arch/m68k/Kconfig b/arch/m68k/Kconfig
>> index 26509b73c6..42fb91539a 100644
>> --- a/arch/m68k/Kconfig
>> +++ b/arch/m68k/Kconfig
>> @@ -200,6 +200,10 @@ config TARGET_AMCORE
>>          bool "Support AMCORE"
>>          select M5307
>>
>> +config TARGET_STMARK2
>> +        bool "Support stmark2"
>> +        select M54418
>> +
>>   endchoice
>>
>>   source "board/BuS/eb_cpu5282/Kconfig"
>> @@ -223,5 +227,6 @@ source "board/freescale/m54455evb/Kconfig"
>>   source "board/freescale/m547xevb/Kconfig"
>>   source "board/freescale/m548xevb/Kconfig"
>>   source "board/sysam/amcore/Kconfig"
>> +source "board/sysam/stmark2/Kconfig"
>>
>>   endmenu
>> diff --git a/board/sysam/stmark2/Kconfig b/board/sysam/stmark2/Kconfig
>> new file mode 100644
>> index 0000000000..87ab7ab7b5
>> --- /dev/null
>> +++ b/board/sysam/stmark2/Kconfig
>> @@ -0,0 +1,15 @@
>> +if TARGET_STMARK2
>> +
>> +config SYS_CPU
>> +       default "mcf5445x"
>> +
>> +config SYS_BOARD
>> +       default "stmark2"
>> +
>> +config SYS_VENDOR
>> +       default "sysam"
>> +
>> +config SYS_CONFIG_NAME
>> +       default "stmark2"
>> +
>> +endif
>> diff --git a/board/sysam/stmark2/MAINTAINERS b/board/sysam/stmark2/MAINTAINERS
>> new file mode 100644
>> index 0000000000..b87f432bb3
>> --- /dev/null
>> +++ b/board/sysam/stmark2/MAINTAINERS
>> @@ -0,0 +1,6 @@
>> +STMARK2 BOARD
>> +M:     Angelo Dureghello <angelo@sysam.it>
>> +S:     Maintained
>> +F:     board/sysam/stmark2/
>> +F:     include/configs/stmark2.h
>> +F:     configs/stmark2_defconfig
>> diff --git a/board/sysam/stmark2/Makefile b/board/sysam/stmark2/Makefile
>> new file mode 100644
>> index 0000000000..064a57ea05
>> --- /dev/null
>> +++ b/board/sysam/stmark2/Makefile
>> @@ -0,0 +1,8 @@
>> +#
>> +# (C) Copyright 2014  Angelo Dureghello <angelo@sysam.it>
>> +#
>> +# SPDX-License-Identifier:     GPL-2.0+
>> +#
>> +
>> +obj-y = stmark2.o
>> +extra-y += sbf_dram_init.o
>> diff --git a/board/sysam/stmark2/sbf_dram_init.S b/board/sysam/stmark2/sbf_dram_init.S
>> new file mode 100644
>> index 0000000000..52abda5c3c
>> --- /dev/null
>> +++ b/board/sysam/stmark2/sbf_dram_init.S
>> @@ -0,0 +1,119 @@
>> +/*
>> + * Board-specific early ddr/sdram init.
>> + *
>> + * (C) Copyright 2017 Angelo Dureghello <angelo@sysam.it>
>> + *
>> + * SPDX-License-Identifier:    GPL-2.0+
>> + */
>> +
>> +.equ   PPMCR0,         0xfc04002d
>> +.equ   MSCR_SDRAMC,    0xec094060
>> +.equ   MISCCR2,        0xec09001a
>> +.equ   DDR_RCR,        0xfc0b8180
>> +.equ   DDR_PADCR,      0xfc0b81ac
>> +.equ   DDR_CR00,       0xfc0b8000
>> +.equ   DDR_CR06,       0xfc0b8018
>> +.equ   DDR_CR09,       0xfc0b8024
>> +.equ   DDR_CR40,       0xfc0b80a0
>> +.equ   DDR_CR45,       0xfc0b80b4
>> +.equ   DDR_CR56,       0xfc0b80e0
>> +
>> +.global sbf_dram_init
>> +.text
>> +
>> +sbf_dram_init:
>> +       /* CD46 = DDR on */
>> +       move.l  #PPMCR0, %a1
>> +       move.b  #46, (%a1)
>> +
>> +       /* stmark 2, max drive strength */
>> +       move.l  #MSCR_SDRAMC, %a1
>> +       move.b  #1, (%a1)
>> +
>> +       /*
>> +        * use cpu clock, seems more realiable
>> +        *
>> +        * DDR2 clock is serviced from DDR controller as input clock / 2
>> +        * so, if clock comes from
>> +        *   vco, i.e. 480(vco) / 2, so ddr clock is 240 Mhz (measured)
>> +        *   cpu, i.e. 250(cpu) / 2, so ddr clock is 125 Mhz (measured)
>> +        *
>> +        *     .
>> +        *    / \    DDR2 can't be clocked lower than 125Mhz
>> +        *   / ! \   DDR2 init must pass further i/dcache enable test
>> +        *  /_____\
>> +        *  WARNING
>> +        */
>> +
>> +       /* cpu / 2 = 125 Mhz for 480 Mhz pll */
>> +       move.l  #MISCCR2, %a1
>> +       move.w  #0xa01d, (%a1)
>> +
>> +       /* DDR force sw reset settings */
>> +       move.l  #DDR_RCR, %a1
>> +       move.l  #0x00000000, (%a1)
>> +       move.l  #0x40000000, (%a1)
>> +
>> +       /*
>> +        * PAD_ODT_CS: for us seems both 1(75 ohm) and 2(150ohm) are good,
>> +        * 500/700 mV are ok
>> +        */
>> +       move.l  #DDR_PADCR, %a1
>> +       move.l  #0x01030203, (%a1)      /* as freescale tower */
>> +
>> +       move.l  #DDR_CR00, %a1
>> +       move.l  #0x01010101, (%a1)+     /* 0x00 */
>> +       move.l  #0x00000101, (%a1)+     /* 0x04 */
>> +       move.l  #0x01010100, (%a1)+     /* 0x08 */
>> +       move.l  #0x01010000, (%a1)+     /* 0x0C */
>> +       move.l  #0x00010101, (%a1)+     /* 0x10 */
>> +       move.l  #DDR_CR06, %a1
>> +       move.l  #0x00010100, (%a1)+     /* 0x18 */
>> +       move.l  #0x00000001, (%a1)+     /* 0x1C */
>> +       move.l  #0x01000001, (%a1)+     /* 0x20 */
>> +       move.l  #0x00000100, (%a1)+     /* 0x24 */
>> +       move.l  #0x00010001, (%a1)+     /* 0x28 */
>> +       move.l  #0x00000200, (%a1)+     /* 0x2C */
>> +       move.l  #0x01000002, (%a1)+     /* 0x30 */
>> +       move.l  #0x00000000, (%a1)+     /* 0x34 */
>> +       move.l  #0x00000100, (%a1)+     /* 0x38 */
>> +       move.l  #0x02000100, (%a1)+     /* 0x3C */
>> +       move.l  #0x02000407, (%a1)+     /* 0x40 */
>> +       move.l  #0x02030007, (%a1)+     /* 0x44 */
>> +       move.l  #0x02000100, (%a1)+     /* 0x48 */
>> +       move.l  #0x0A030203, (%a1)+     /* 0x4C */
>> +       move.l  #0x00020708, (%a1)+     /* 0x50 */
>> +       move.l  #0x00050008, (%a1)+     /* 0x54 */
>> +       move.l  #0x04030002, (%a1)+     /* 0x58 */
>> +       move.l  #0x00000004, (%a1)+     /* 0x5C */
>> +       move.l  #0x020A0000, (%a1)+     /* 0x60 */
>> +       move.l  #0x0C00000E, (%a1)+     /* 0x64 */
>> +       move.l  #0x00002004, (%a1)+     /* 0x68 */
>> +       move.l  #0x00000000, (%a1)+     /* 0x6C */
>> +       move.l  #0x00100010, (%a1)+     /* 0x70 */
>> +       move.l  #0x00100010, (%a1)+     /* 0x74 */
>> +       move.l  #0x00000000, (%a1)+     /* 0x78 */
>> +       move.l  #0x07990000, (%a1)+     /* 0x7C */
>> +       move.l  #DDR_CR40, %a1
>> +       move.l  #0x00000000, (%a1)+     /* 0xA0 */
>> +       move.l  #0x00C80064, (%a1)+     /* 0xA4 */
>> +       move.l  #0x44520002, (%a1)+     /* 0xA8 */
>> +       move.l  #0x00C80023, (%a1)+     /* 0xAC */
>> +       move.l  #DDR_CR45, %a1
>> +       move.l  #0x0000C350, (%a1)      /* 0xB4 */
>> +       move.l  #DDR_CR56, %a1
>> +       move.l  #0x04000000, (%a1)+     /* 0xE0 */
>> +       move.l  #0x03000304, (%a1)+     /* 0xE4 */
>> +       move.l  #0x40040000, (%a1)+     /* 0xE8 */
>> +       move.l  #0xC0004004, (%a1)+     /* 0xEC */
>> +       move.l  #0x0642C000, (%a1)+     /* 0xF0 */
>> +       move.l  #0x00000642, (%a1)+     /* 0xF4 */
>> +       move.l  #DDR_CR09, %a1
>> +       tpf
>> +       move.l  #0x01000100, (%a1)      /* 0x24 */
>> +
>> +       move.l  #0x2000, %d1
>> +       bsr     asm_delay
>> +
>> +
>> +       rts
>> diff --git a/board/sysam/stmark2/stmark2.c b/board/sysam/stmark2/stmark2.c
>> new file mode 100644
>> index 0000000000..4f291ab6d6
>> --- /dev/null
>> +++ b/board/sysam/stmark2/stmark2.c
>> @@ -0,0 +1,47 @@
>> +/*
>> + * Board-specific init.
>> + *
>> + * (C) Copyright 2017 Angelo Dureghello <angelo@sysam.it>
>> + *
>> + * SPDX-License-Identifier:    GPL-2.0+
>> + */
>> +
>> +#include <common.h>
>> +#include <spi.h>
>> +#include <asm/io.h>
>> +#include <asm/immap.h>
>> +#include <mmc.h>
>> +#include <fsl_esdhc.h>
>> +
>> +DECLARE_GLOBAL_DATA_PTR;
>> +
>> +int checkboard(void)
>> +{
>> +       /*
>> +        * need to to:
>> +        * Check serial flash size. if 2mb evb, else 8mb demo
>> +        */
>> +       puts("Board: ");
>> +       puts("Sysam stmark2\n");
>> +       return 0;
>> +}
>> +
>> +int dram_init(void)
>> +{
>> +       u32 dramsize;
>> +
>> +       /*
>> +        * Serial Boot: The dram is already initialized in start.S
>> +        * only require to return DRAM size
>> +        */
>> +       dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
>> +
>> +       gd->ram_size = dramsize;
>> +
>> +       return 0;
>> +}
>> +
>> +int testdram(void)
>> +{
>> +       return 0;
>> +}
>> diff --git a/configs/stmark2_defconfig b/configs/stmark2_defconfig
>> new file mode 100644
>> index 0000000000..cf3625c281
>> --- /dev/null
>> +++ b/configs/stmark2_defconfig
>> @@ -0,0 +1,26 @@
>> +CONFIG_M68K=y
>> +CONFIG_SYS_TEXT_BASE=0x47E00000
>> +CONFIG_TARGET_STMARK2=y
>> +CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_SERIAL_BOOT,SYS_INPUT_CLKSRC=30000000"
>> +# CONFIG_DISPLAY_BOARDINFO is not set
>> +# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
>> +CONFIG_HUSH_PARSER=y
>> +CONFIG_SYS_PROMPT="stmark2 $ "
>> +# CONFIG_CMD_BDI is not set
>> +# CONFIG_CMD_CONSOLE is not set
>> +# CONFIG_CMD_IMLS is not set
>> +# CONFIG_CMD_EXPORTENV is not set
>> +# CONFIG_CMD_IMPORTENV is not set
>> +CONFIG_CMD_LOADB=y
>> +# CONFIG_CMD_LOADS is not set
>> +# CONFIG_CMD_FLASH is not set
>> +CONFIG_CMD_SF=y
>> +CONFIG_CMD_SPI=y
>> +# CONFIG_CMD_FPGA is not set
>> +# CONFIG_CMD_SETEXPR is not set
>> +# CONFIG_CMD_NET is not set
>> +# CONFIG_CMD_NFS is not set
>> +CONFIG_CMD_CACHE=y
>> +CONFIG_SPI_FLASH=y
>> +CONFIG_SPI_FLASH_MTD=y
>> +CONFIG_REGEX=y
>> diff --git a/include/configs/stmark2.h b/include/configs/stmark2.h
>> new file mode 100644
>> index 0000000000..bd1f64bc8f
>> --- /dev/null
>> +++ b/include/configs/stmark2.h
>> @@ -0,0 +1,202 @@
>> +/*
>> + * Sysam stmark2 board configuration
>> + *
>> + * (C) Copyright 2016  Angelo Dureghello <angelo@sysam.it>
>> + *
>> + * SPDX-License-Identifier:     GPL-2.0+
>> + */
>> +
>> +#ifndef __STMARK2_CONFIG_H
>> +#define __STMARK2_CONFIG_H
>> +
>> +#define CONFIG_STMARK2
>> +#define CONFIG_HOSTNAME                        stmark2
>> +
>> +#define CONFIG_MCFUART
>> +#define CONFIG_SYS_UART_PORT           0
>> +#define CONFIG_SYS_BAUDRATE_TABLE      { 9600 , 19200 , 38400 , 57600, 115200 }
>> +
>> +#define LDS_BOARD_TEXT                                                 \
>> +       board/sysam/stmark2/sbf_dram_init.o (.text*)
>> +
>> +#define CONFIG_TIMESTAMP
>> +
>> +/* commands */
>> +#define CONFIG_CMD_REGINFO
>> +
>> +#define CONFIG_BOOTARGS                                                \
>> +       "console=ttyS0,115200 root=/dev/ram0 rw "               \
>> +               "rootfstype=ramfs "                             \
>> +               "rdinit=/bin/init "                             \
>> +               "devtmpfs.mount=1"
>> +
>> +#define CONFIG_BOOTCOMMAND                                     \
>> +       "sf probe 0:1 50000000; "                               \
>> +       "sf read ${loadaddr} 0x100000 ${kern_size}; "           \
>> +       "bootm ${loadaddr}"
>> +
>> +#define CONFIG_EXTRA_ENV_SETTINGS                              \
>> +       "kern_size=0x700000\0"                                  \
>> +       "loadaddr=0x40001000\0"                                 \
>> +               "-(rootfs)\0"                                   \
>> +       "update_uboot=loady ${loadaddr}; "                      \
>> +               "sf probe 0:1 50000000; "                       \
>> +               "sf erase 0 0x80000; "                          \
>> +               "sf write ${loadaddr} 0 ${filesize}\0"          \
>> +       "update_kernel=loady ${loadaddr}; "                     \
>> +               "setenv kern_size ${filesize}; saveenv; "       \
>> +               "sf probe 0:1 50000000; "                       \
>> +               "sf erase 0x100000 0x700000; "                  \
>> +               "sf write ${loadaddr} 0x100000 ${filesize}\0"   \
>> +       "update_rootfs=loady ${loadaddr}; "                     \
>> +               "sf probe 0:1 50000000; "                       \
>> +               "sf erase 0x00800000 0x100000; "                \
>> +               "sf write ${loadaddr} 0x00800000 ${filesize}\0" \
>> +       ""
>> +
>> +/* Realtime clock */
>> +#undef CONFIG_MCFRTC
>> +#define CONFIG_RTC_MCFRRTC
>> +#define CONFIG_SYS_MCFRRTC_BASE                0xFC0A8000
>> +
>> +/* spi not partitions */
>> +#define CONFIG_CMD_MTDPARTS
>> +#define CONFIG_MTD_DEVICE
>> +#define CONFIG_JFFS2_CMDLINE
>> +#define CONFIG_JFFS2_DEV               "nor0"
>> +#define MTDIDS_DEFAULT                 "nor0=spi-flash.0"
>> +#define MTDPARTS_DEFAULT                                       \
>> +       "mtdparts=spi-flash.0:"                                 \
>> +               "1m(u-boot),"                                   \
>> +               "7m(kernel),"                                   \
>> +               "-(rootfs)"
>> +
>> +/* Timer */
>> +#define CONFIG_MCFTMR
>> +#undef CONFIG_MCFPIT
>> +
>> +/* DSPI and Serial Flash */
>> +#define CONFIG_CF_SPI
>> +#define CONFIG_CF_DSPI
>> +#define CONFIG_SF_DEFAULT_SPEED                50000000
>> +#define CONFIG_SERIAL_FLASH
>> +#define CONFIG_HARD_SPI
>> +#define CONFIG_SPI_FLASH_ISSI
>> +#define CONFIG_ENV_SPI_BUS             0
>> +#define CONFIG_ENV_SPI_CS              1
>> +
>> +#define CONFIG_SYS_SBFHDR_SIZE         0x7
>> +
>> +#define CONFIG_SYS_DSPI_CTAR0          (DSPI_CTAR_TRSZ(7) | \
>> +                                       DSPI_CTAR_PCSSCK_1CLK | \
>> +                                       DSPI_CTAR_PASC(0) | \
>> +                                       DSPI_CTAR_PDT(0) | \
>> +                                       DSPI_CTAR_CSSCK(0) | \
>> +                                       DSPI_CTAR_ASC(0) | \
>> +                                       DSPI_CTAR_DT(1) | \
>> +                                       DSPI_CTAR_BR(6))
>> +#define CONFIG_SYS_DSPI_CTAR1          (CONFIG_SYS_DSPI_CTAR0)
>> +#define CONFIG_SYS_DSPI_CTAR2          (CONFIG_SYS_DSPI_CTAR0)
>> +
>> +/* Input, PCI, Flexbus, and VCO */
>> +#define CONFIG_EXTRA_CLOCK
>> +
>> +#define CONFIG_PRAM                    2048    /* 2048 KB */
>> +#define CONFIG_SYS_LONGHELP
>> +#define CONFIG_AUTO_COMPLETE
>> +#define CONFIG_SYS_CBSIZE              256     /* Console I/O Buffer Size */
>> +
>> +/* Print Buffer Size */
>> +#define CONFIG_SYS_PBSIZE              (CONFIG_SYS_CBSIZE + \
>> +                                       sizeof(CONFIG_SYS_PROMPT) + 16)
>> +#define CONFIG_SYS_MAXARGS             16
>> +/* Boot Argument Buffer Size    */
>> +#define CONFIG_SYS_BARGSIZE            CONFIG_SYS_CBSIZE
>> +
>> +#define CONFIG_SYS_LOAD_ADDR           (CONFIG_SYS_SDRAM_BASE + 0x10000)
>> +#define CONFIG_SYS_MBAR                        0xFC000000
>> +
>> +/*
>> + * Definitions for initial stack pointer and data area (in internal SRAM)
>> + */
>> +#define CONFIG_SYS_INIT_RAM_ADDR       0x80000000
>> +/* End of used area in internal SRAM */
>> +#define CONFIG_SYS_INIT_RAM_SIZE       0x10000
>> +#define CONFIG_SYS_INIT_RAM_CTRL       0x221
>> +#define CONFIG_SYS_GBL_DATA_OFFSET     ((CONFIG_SYS_INIT_RAM_SIZE - \
>> +                                       GENERATED_GBL_DATA_SIZE) - 32)
>> +#define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
>> +#define CONFIG_SYS_SBFHDR_DATA_OFFSET  (CONFIG_SYS_INIT_RAM_SIZE - 32)
>> +
>> +/*
>> + * Start addresses for the final memory configuration
>> + * (Set up by the startup code)
>> + * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
>> + */
>> +#define CONFIG_SYS_SDRAM_BASE          0x40000000
>> +#define CONFIG_SYS_SDRAM_SIZE          128     /* SDRAM size in MB */
>> +
>> +#define CONFIG_SYS_MEMTEST_START       (CONFIG_SYS_SDRAM_BASE + 0x400)
>> +#define CONFIG_SYS_MEMTEST_END         ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
>> +#define CONFIG_SYS_DRAM_TEST
>> +
>> +#if defined(CONFIG_CF_SBF)
>> +#define CONFIG_SERIAL_BOOT
>> +#endif
>> +
>> +#if defined(CONFIG_SERIAL_BOOT)
>> +#define CONFIG_SYS_MONITOR_BASE                (CONFIG_SYS_TEXT_BASE + 0x400)
>> +#else
>> +#define CONFIG_SYS_MONITOR_BASE                (CONFIG_SYS_FLASH_BASE + 0x400)
>> +#endif
>> +
>> +#define CONFIG_SYS_BOOTPARAMS_LEN      (64 * 1024)
>> +/* Reserve 256 kB for Monitor */
>> +#define CONFIG_SYS_MONITOR_LEN         (256 << 10)
>> +/* Reserve 256 kB for malloc() */
>> +#define CONFIG_SYS_MALLOC_LEN          (256 << 10)
>> +
>> +/*
>> + * For booting Linux, the board info and command line data
>> + * have to be in the first 8 MB of memory, since this is
>> + * the maximum mapped by the Linux kernel during initialization ??
>> + */
>> +/* Initial Memory map for Linux */
>> +#define CONFIG_SYS_BOOTMAPSZ           (CONFIG_SYS_SDRAM_BASE + \
>> +                                       (CONFIG_SYS_SDRAM_SIZE << 20))
>> +
>> +/* Configuration for environment
>> + * Environment is embedded in u-boot in the second sector of the flash
>> + */
>> +
>> +#if defined(CONFIG_CF_SBF)
>> +#define CONFIG_ENV_IS_IN_SPI_FLASH     1
> 
> This is now in Kconfig.
> 
>> +#define CONFIG_ENV_SPI_CS              1
>> +#define CONFIG_ENV_OFFSET              0x40000
>> +#define CONFIG_ENV_SIZE                        0x2000
>> +#define CONFIG_ENV_SECT_SIZE           0x10000
>> +#endif
>> +
>> +#undef CONFIG_ENV_OVERWRITE
>> +
>> +/* Cache Configuration */
>> +#define CONFIG_SYS_CACHELINE_SIZE      16
>> +#define ICACHE_STATUS                  (CONFIG_SYS_INIT_RAM_ADDR + \
>> +                                        CONFIG_SYS_INIT_RAM_SIZE - 8)
>> +#define DCACHE_STATUS                  (CONFIG_SYS_INIT_RAM_ADDR + \
>> +                                        CONFIG_SYS_INIT_RAM_SIZE - 4)
>> +#define CONFIG_SYS_ICACHE_INV          (CF_CACR_BCINVA + CF_CACR_ICINVA)
>> +#define CONFIG_SYS_DCACHE_INV          (CF_CACR_DCINVA)
>> +#define CONFIG_SYS_CACHE_ACR2          (CONFIG_SYS_SDRAM_BASE | \
>> +                                        CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
>> +                                        CF_ACR_EN | CF_ACR_SM_ALL)
>> +#define CONFIG_SYS_CACHE_ICACR         (CF_CACR_BEC | CF_CACR_IEC | \
>> +                                        CF_CACR_ICINVA | CF_CACR_EUSP)
>> +#define CONFIG_SYS_CACHE_DCACR         ((CONFIG_SYS_CACHE_ICACR | \
>> +                                        CF_CACR_DEC | CF_CACR_DDCM_P | \
>> +                                        CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
>> +
>> +#define CACR_STATUS                    (CONFIG_SYS_INIT_RAM_ADDR + \
>> +                                       CONFIG_SYS_INIT_RAM_SIZE - 12)
>> +
>> +#endif /* __STMARK2_CONFIG_H */
>> diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
>> index e8f49ebe5d..e6faf3450e 100644
>> --- a/scripts/config_whitelist.txt
>> +++ b/scripts/config_whitelist.txt
>> @@ -2696,6 +2696,7 @@ CONFIG_STM32_GPIO
>>   CONFIG_STM32_HSE_HZ
>>   CONFIG_STM32_HZ
>>   CONFIG_STM32_SERIAL
>> +CONFIG_STMARK2
> 
> We should stop adding ad-hoc CONFIG_xxx. Please use Kconfig.
> 
>>   CONFIG_STRESS
>>   CONFIG_STRIDER
>>   CONFIG_STRIDER_CON
>> --
> 
> Regards,
> Bin
> 

Regards,
Angelo Dureghello
diff mbox

Patch

diff --git a/arch/m68k/Kconfig b/arch/m68k/Kconfig
index 26509b73c6..42fb91539a 100644
--- a/arch/m68k/Kconfig
+++ b/arch/m68k/Kconfig
@@ -200,6 +200,10 @@  config TARGET_AMCORE
 	bool "Support AMCORE"
 	select M5307
 
+config TARGET_STMARK2
+        bool "Support stmark2"
+        select M54418
+
 endchoice
 
 source "board/BuS/eb_cpu5282/Kconfig"
@@ -223,5 +227,6 @@  source "board/freescale/m54455evb/Kconfig"
 source "board/freescale/m547xevb/Kconfig"
 source "board/freescale/m548xevb/Kconfig"
 source "board/sysam/amcore/Kconfig"
+source "board/sysam/stmark2/Kconfig"
 
 endmenu
diff --git a/board/sysam/stmark2/Kconfig b/board/sysam/stmark2/Kconfig
new file mode 100644
index 0000000000..87ab7ab7b5
--- /dev/null
+++ b/board/sysam/stmark2/Kconfig
@@ -0,0 +1,15 @@ 
+if TARGET_STMARK2
+
+config SYS_CPU
+	default "mcf5445x"
+
+config SYS_BOARD
+	default "stmark2"
+
+config SYS_VENDOR
+	default "sysam"
+
+config SYS_CONFIG_NAME
+	default "stmark2"
+
+endif
diff --git a/board/sysam/stmark2/MAINTAINERS b/board/sysam/stmark2/MAINTAINERS
new file mode 100644
index 0000000000..b87f432bb3
--- /dev/null
+++ b/board/sysam/stmark2/MAINTAINERS
@@ -0,0 +1,6 @@ 
+STMARK2 BOARD
+M:	Angelo Dureghello <angelo@sysam.it>
+S:	Maintained
+F:	board/sysam/stmark2/
+F:	include/configs/stmark2.h
+F:	configs/stmark2_defconfig
diff --git a/board/sysam/stmark2/Makefile b/board/sysam/stmark2/Makefile
new file mode 100644
index 0000000000..064a57ea05
--- /dev/null
+++ b/board/sysam/stmark2/Makefile
@@ -0,0 +1,8 @@ 
+#
+# (C) Copyright 2014  Angelo Dureghello <angelo@sysam.it>
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y = stmark2.o
+extra-y += sbf_dram_init.o
diff --git a/board/sysam/stmark2/sbf_dram_init.S b/board/sysam/stmark2/sbf_dram_init.S
new file mode 100644
index 0000000000..52abda5c3c
--- /dev/null
+++ b/board/sysam/stmark2/sbf_dram_init.S
@@ -0,0 +1,119 @@ 
+/*
+ * Board-specific early ddr/sdram init.
+ *
+ * (C) Copyright 2017 Angelo Dureghello <angelo@sysam.it>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+.equ	PPMCR0, 	0xfc04002d
+.equ	MSCR_SDRAMC,	0xec094060
+.equ	MISCCR2,	0xec09001a
+.equ	DDR_RCR,	0xfc0b8180
+.equ	DDR_PADCR,	0xfc0b81ac
+.equ	DDR_CR00,	0xfc0b8000
+.equ	DDR_CR06,	0xfc0b8018
+.equ	DDR_CR09,	0xfc0b8024
+.equ	DDR_CR40,	0xfc0b80a0
+.equ	DDR_CR45,	0xfc0b80b4
+.equ	DDR_CR56,	0xfc0b80e0
+
+.global sbf_dram_init
+.text
+
+sbf_dram_init:
+	/* CD46 = DDR on */
+	move.l	#PPMCR0, %a1
+	move.b	#46, (%a1)
+
+	/* stmark 2, max drive strength */
+	move.l	#MSCR_SDRAMC, %a1
+	move.b	#1, (%a1)
+
+	/*
+	 * use cpu clock, seems more realiable
+	 *
+	 * DDR2 clock is serviced from DDR controller as input clock / 2
+	 * so, if clock comes from
+	 *   vco, i.e. 480(vco) / 2, so ddr clock is 240 Mhz (measured)
+	 *   cpu, i.e. 250(cpu) / 2, so ddr clock is 125 Mhz (measured)
+	 *
+	 *     .
+	 *    / \    DDR2 can't be clocked lower than 125Mhz
+	 *   / ! \   DDR2 init must pass further i/dcache enable test
+	 *  /_____\
+	 *  WARNING
+	 */
+
+	/* cpu / 2 = 125 Mhz for 480 Mhz pll */
+	move.l	#MISCCR2, %a1
+	move.w	#0xa01d, (%a1)
+
+	/* DDR force sw reset settings */
+	move.l	#DDR_RCR, %a1
+	move.l	#0x00000000, (%a1)
+	move.l	#0x40000000, (%a1)
+
+	/*
+	 * PAD_ODT_CS: for us seems both 1(75 ohm) and 2(150ohm) are good,
+	 * 500/700 mV are ok
+	 */
+	move.l	#DDR_PADCR, %a1
+	move.l	#0x01030203, (%a1)	/* as freescale tower */
+
+	move.l	#DDR_CR00, %a1
+	move.l	#0x01010101, (%a1)+	/* 0x00 */
+	move.l	#0x00000101, (%a1)+	/* 0x04 */
+	move.l	#0x01010100, (%a1)+	/* 0x08 */
+	move.l	#0x01010000, (%a1)+	/* 0x0C */
+	move.l	#0x00010101, (%a1)+	/* 0x10 */
+	move.l	#DDR_CR06, %a1
+	move.l	#0x00010100, (%a1)+	/* 0x18 */
+	move.l	#0x00000001, (%a1)+	/* 0x1C */
+	move.l	#0x01000001, (%a1)+	/* 0x20 */
+	move.l	#0x00000100, (%a1)+	/* 0x24 */
+	move.l	#0x00010001, (%a1)+	/* 0x28 */
+	move.l	#0x00000200, (%a1)+	/* 0x2C */
+	move.l	#0x01000002, (%a1)+	/* 0x30 */
+	move.l	#0x00000000, (%a1)+	/* 0x34 */
+	move.l	#0x00000100, (%a1)+	/* 0x38 */
+	move.l	#0x02000100, (%a1)+	/* 0x3C */
+	move.l	#0x02000407, (%a1)+	/* 0x40 */
+	move.l	#0x02030007, (%a1)+	/* 0x44 */
+	move.l	#0x02000100, (%a1)+	/* 0x48 */
+	move.l	#0x0A030203, (%a1)+	/* 0x4C */
+	move.l	#0x00020708, (%a1)+	/* 0x50 */
+	move.l	#0x00050008, (%a1)+	/* 0x54 */
+	move.l	#0x04030002, (%a1)+	/* 0x58 */
+	move.l	#0x00000004, (%a1)+	/* 0x5C */
+	move.l	#0x020A0000, (%a1)+	/* 0x60 */
+	move.l	#0x0C00000E, (%a1)+	/* 0x64 */
+	move.l	#0x00002004, (%a1)+	/* 0x68 */
+	move.l	#0x00000000, (%a1)+	/* 0x6C */
+	move.l	#0x00100010, (%a1)+	/* 0x70 */
+	move.l	#0x00100010, (%a1)+	/* 0x74 */
+	move.l	#0x00000000, (%a1)+	/* 0x78 */
+	move.l	#0x07990000, (%a1)+	/* 0x7C */
+	move.l	#DDR_CR40, %a1
+	move.l	#0x00000000, (%a1)+	/* 0xA0 */
+	move.l	#0x00C80064, (%a1)+	/* 0xA4 */
+	move.l	#0x44520002, (%a1)+	/* 0xA8 */
+	move.l	#0x00C80023, (%a1)+	/* 0xAC */
+	move.l	#DDR_CR45, %a1
+	move.l	#0x0000C350, (%a1)	/* 0xB4 */
+	move.l	#DDR_CR56, %a1
+	move.l	#0x04000000, (%a1)+	/* 0xE0 */
+	move.l	#0x03000304, (%a1)+	/* 0xE4 */
+	move.l	#0x40040000, (%a1)+	/* 0xE8 */
+	move.l	#0xC0004004, (%a1)+	/* 0xEC */
+	move.l	#0x0642C000, (%a1)+	/* 0xF0 */
+	move.l	#0x00000642, (%a1)+	/* 0xF4 */
+	move.l	#DDR_CR09, %a1
+	tpf
+	move.l	#0x01000100, (%a1)	/* 0x24 */
+
+	move.l	#0x2000, %d1
+	bsr	asm_delay
+
+
+	rts
diff --git a/board/sysam/stmark2/stmark2.c b/board/sysam/stmark2/stmark2.c
new file mode 100644
index 0000000000..4f291ab6d6
--- /dev/null
+++ b/board/sysam/stmark2/stmark2.c
@@ -0,0 +1,47 @@ 
+/*
+ * Board-specific init.
+ *
+ * (C) Copyright 2017 Angelo Dureghello <angelo@sysam.it>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <spi.h>
+#include <asm/io.h>
+#include <asm/immap.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+	/*
+	 * need to to:
+	 * Check serial flash size. if 2mb evb, else 8mb demo
+	 */
+	puts("Board: ");
+	puts("Sysam stmark2\n");
+	return 0;
+}
+
+int dram_init(void)
+{
+	u32 dramsize;
+
+	/*
+	 * Serial Boot: The dram is already initialized in start.S
+	 * only require to return DRAM size
+	 */
+	dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
+
+	gd->ram_size = dramsize;
+
+	return 0;
+}
+
+int testdram(void)
+{
+	return 0;
+}
diff --git a/configs/stmark2_defconfig b/configs/stmark2_defconfig
new file mode 100644
index 0000000000..cf3625c281
--- /dev/null
+++ b/configs/stmark2_defconfig
@@ -0,0 +1,26 @@ 
+CONFIG_M68K=y
+CONFIG_SYS_TEXT_BASE=0x47E00000
+CONFIG_TARGET_STMARK2=y
+CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_SERIAL_BOOT,SYS_INPUT_CLKSRC=30000000"
+# CONFIG_DISPLAY_BOARDINFO is not set
+# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="stmark2 $ "
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+CONFIG_CMD_LOADB=y
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_CMD_CACHE=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_REGEX=y
diff --git a/include/configs/stmark2.h b/include/configs/stmark2.h
new file mode 100644
index 0000000000..bd1f64bc8f
--- /dev/null
+++ b/include/configs/stmark2.h
@@ -0,0 +1,202 @@ 
+/*
+ * Sysam stmark2 board configuration
+ *
+ * (C) Copyright 2016  Angelo Dureghello <angelo@sysam.it>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef __STMARK2_CONFIG_H
+#define __STMARK2_CONFIG_H
+
+#define CONFIG_STMARK2
+#define CONFIG_HOSTNAME			stmark2
+
+#define CONFIG_MCFUART
+#define CONFIG_SYS_UART_PORT		0
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600 , 19200 , 38400 , 57600, 115200 }
+
+#define LDS_BOARD_TEXT 						\
+	board/sysam/stmark2/sbf_dram_init.o (.text*)
+
+#define CONFIG_TIMESTAMP
+
+/* commands */
+#define CONFIG_CMD_REGINFO
+
+#define CONFIG_BOOTARGS						\
+	"console=ttyS0,115200 root=/dev/ram0 rw "		\
+		"rootfstype=ramfs "				\
+		"rdinit=/bin/init "				\
+		"devtmpfs.mount=1"
+
+#define CONFIG_BOOTCOMMAND					\
+	"sf probe 0:1 50000000; "				\
+	"sf read ${loadaddr} 0x100000 ${kern_size}; "		\
+	"bootm ${loadaddr}"
+
+#define CONFIG_EXTRA_ENV_SETTINGS				\
+	"kern_size=0x700000\0"					\
+	"loadaddr=0x40001000\0"					\
+		"-(rootfs)\0"					\
+	"update_uboot=loady ${loadaddr}; "			\
+		"sf probe 0:1 50000000; "			\
+		"sf erase 0 0x80000; "				\
+		"sf write ${loadaddr} 0 ${filesize}\0"		\
+	"update_kernel=loady ${loadaddr}; "			\
+		"setenv kern_size ${filesize}; saveenv; "	\
+		"sf probe 0:1 50000000; "			\
+		"sf erase 0x100000 0x700000; "			\
+		"sf write ${loadaddr} 0x100000 ${filesize}\0"	\
+	"update_rootfs=loady ${loadaddr}; "			\
+		"sf probe 0:1 50000000; "			\
+		"sf erase 0x00800000 0x100000; "		\
+		"sf write ${loadaddr} 0x00800000 ${filesize}\0"	\
+	""
+
+/* Realtime clock */
+#undef CONFIG_MCFRTC
+#define CONFIG_RTC_MCFRRTC
+#define CONFIG_SYS_MCFRRTC_BASE		0xFC0A8000
+
+/* spi not partitions */
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE
+#define CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV		"nor0"
+#define MTDIDS_DEFAULT			"nor0=spi-flash.0"
+#define MTDPARTS_DEFAULT 					\
+	"mtdparts=spi-flash.0:" 				\
+		"1m(u-boot),"					\
+		"7m(kernel),"					\
+		"-(rootfs)"
+
+/* Timer */
+#define CONFIG_MCFTMR
+#undef CONFIG_MCFPIT
+
+/* DSPI and Serial Flash */
+#define CONFIG_CF_SPI
+#define CONFIG_CF_DSPI
+#define CONFIG_SF_DEFAULT_SPEED		50000000
+#define CONFIG_SERIAL_FLASH
+#define CONFIG_HARD_SPI
+#define CONFIG_SPI_FLASH_ISSI
+#define CONFIG_ENV_SPI_BUS		0
+#define CONFIG_ENV_SPI_CS		1
+
+#define CONFIG_SYS_SBFHDR_SIZE		0x7
+
+#define CONFIG_SYS_DSPI_CTAR0		(DSPI_CTAR_TRSZ(7) | \
+					DSPI_CTAR_PCSSCK_1CLK | \
+					DSPI_CTAR_PASC(0) | \
+					DSPI_CTAR_PDT(0) | \
+					DSPI_CTAR_CSSCK(0) | \
+					DSPI_CTAR_ASC(0) | \
+					DSPI_CTAR_DT(1) | \
+					DSPI_CTAR_BR(6))
+#define CONFIG_SYS_DSPI_CTAR1		(CONFIG_SYS_DSPI_CTAR0)
+#define CONFIG_SYS_DSPI_CTAR2		(CONFIG_SYS_DSPI_CTAR0)
+
+/* Input, PCI, Flexbus, and VCO */
+#define CONFIG_EXTRA_CLOCK
+
+#define CONFIG_PRAM			2048	/* 2048 KB */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS		16
+/* Boot Argument Buffer Size    */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x10000)
+#define CONFIG_SYS_MBAR			0xFC000000
+
+/*
+ * Definitions for initial stack pointer and data area (in internal SRAM)
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR	0x80000000
+/* End of used area in internal SRAM */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x10000
+#define CONFIG_SYS_INIT_RAM_CTRL	0x221
+#define CONFIG_SYS_GBL_DATA_OFFSET	((CONFIG_SYS_INIT_RAM_SIZE - \
+					GENERATED_GBL_DATA_SIZE) - 32)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+#define CONFIG_SYS_SBFHDR_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - 32)
+
+/*
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
+ */
+#define CONFIG_SYS_SDRAM_BASE		0x40000000
+#define CONFIG_SYS_SDRAM_SIZE		128	/* SDRAM size in MB */
+
+#define CONFIG_SYS_MEMTEST_START	(CONFIG_SYS_SDRAM_BASE + 0x400)
+#define CONFIG_SYS_MEMTEST_END		((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
+#define CONFIG_SYS_DRAM_TEST
+
+#if defined(CONFIG_CF_SBF)
+#define CONFIG_SERIAL_BOOT
+#endif
+
+#if defined(CONFIG_SERIAL_BOOT)
+#define CONFIG_SYS_MONITOR_BASE		(CONFIG_SYS_TEXT_BASE + 0x400)
+#else
+#define CONFIG_SYS_MONITOR_BASE		(CONFIG_SYS_FLASH_BASE + 0x400)
+#endif
+
+#define CONFIG_SYS_BOOTPARAMS_LEN	(64 * 1024)
+/* Reserve 256 kB for Monitor */
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)
+/* Reserve 256 kB for malloc() */
+#define CONFIG_SYS_MALLOC_LEN		(256 << 10)
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization ??
+ */
+/* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + \
+					(CONFIG_SYS_SDRAM_SIZE << 20))
+
+/* Configuration for environment
+ * Environment is embedded in u-boot in the second sector of the flash
+ */
+
+#if defined(CONFIG_CF_SBF)
+#define CONFIG_ENV_IS_IN_SPI_FLASH	1
+#define CONFIG_ENV_SPI_CS		1
+#define CONFIG_ENV_OFFSET		0x40000
+#define CONFIG_ENV_SIZE			0x2000
+#define CONFIG_ENV_SECT_SIZE		0x10000
+#endif
+
+#undef CONFIG_ENV_OVERWRITE
+
+/* Cache Configuration */
+#define CONFIG_SYS_CACHELINE_SIZE	16
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_BCINVA + CF_CACR_ICINVA)
+#define CONFIG_SYS_DCACHE_INV		(CF_CACR_DCINVA)
+#define CONFIG_SYS_CACHE_ACR2		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_BEC | CF_CACR_IEC | \
+					 CF_CACR_ICINVA | CF_CACR_EUSP)
+#define CONFIG_SYS_CACHE_DCACR		((CONFIG_SYS_CACHE_ICACR | \
+					 CF_CACR_DEC | CF_CACR_DDCM_P | \
+					 CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
+
+#define CACR_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					CONFIG_SYS_INIT_RAM_SIZE - 12)
+
+#endif /* __STMARK2_CONFIG_H */
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index e8f49ebe5d..e6faf3450e 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -2696,6 +2696,7 @@  CONFIG_STM32_GPIO
 CONFIG_STM32_HSE_HZ
 CONFIG_STM32_HZ
 CONFIG_STM32_SERIAL
+CONFIG_STMARK2
 CONFIG_STRESS
 CONFIG_STRIDER
 CONFIG_STRIDER_CON