| Message ID | 1500046768-24405-9-git-send-email-arbab@linux.vnet.ibm.com |
|---|---|
| State | Superseded |
| Headers | show |
Looks good ... although have you run some of the sanity tests against this on the released 4.12 kernel? We didn't start trying to suppress flushes until then so we should probably verify things still actually work after enabling it. - Alistair On Fri, 14 Jul 2017 10:39:27 AM Reza Arbab wrote: > POWER9 DD2 has added a new bit we'd like to set: > > "XTS_CONFIG2_NO_FLUSH_ENA: if enabled, allows MMIO ATSDs to suppress the > flush" > > Cc: Alistair Popple <alistair@popple.id.au> > Signed-off-by: Reza Arbab <arbab@linux.vnet.ibm.com> > --- > hw/npu2.c | 5 +++++ > include/npu2-regs.h | 1 + > 2 files changed, 6 insertions(+) > > diff --git a/hw/npu2.c b/hw/npu2.c > index d3fa930..dfe8622 100644 > --- a/hw/npu2.c > +++ b/hw/npu2.c > @@ -795,6 +795,11 @@ static void npu2_hw_init(struct npu2 *p) > val = npu2_read(p, NPU2_XTS_CFG); > npu2_write(p, NPU2_XTS_CFG, val | NPU2_XTS_CFG_MMIOSD | NPU2_XTS_CFG_TRY_ATR_RO); > > + if (!is_p9dd1()) { > + val = npu2_read(p, NPU2_XTS_CFG2); > + npu2_write(p, NPU2_XTS_CFG2, val | NPU2_XTS_CFG2_NO_FLUSH_ENA); > + } > + > /* Init memory cache directory (MCD) registers. */ > phys_map_get(p->chip_id, GPU_MEM, NPU2_LINKS_PER_CHIP - 1, > &gpu_min_addr, NULL); > diff --git a/include/npu2-regs.h b/include/npu2-regs.h > index 737b380..960792f 100644 > --- a/include/npu2-regs.h > +++ b/include/npu2-regs.h > @@ -403,6 +403,7 @@ void npu2_write_mask(struct npu2 *p, uint64_t reg, uint64_t val, uint64_t mask); > #define NPU2_XTS_CFG_MMIOSD PPC_BIT(1) > #define NPU2_XTS_CFG_TRY_ATR_RO PPC_BIT(6) > #define NPU2_XTS_CFG2 NPU2_REG_OFFSET(NPU2_STACK_MISC, NPU2_BLOCK_XTS, 0x028) > +#define NPU2_XTS_CFG2_NO_FLUSH_ENA PPC_BIT(49) > #define NPU2_XTS_DBG_CFG0 NPU2_REG_OFFSET(NPU2_STACK_MISC, NPU2_BLOCK_XTS, 0x030) > #define NPU2_XTS_DBG_CFG1 NPU2_REG_OFFSET(NPU2_STACK_MISC, NPU2_BLOCK_XTS, 0x038) > #define NPU2_XTS_PMU_CNT NPU2_REG_OFFSET(NPU2_STACK_MISC, NPU2_BLOCK_XTS, 0x040) >
On Mon, Jul 17, 2017 at 01:50:53PM +1000, Alistair Popple wrote: >Looks good ... although have you run some of the sanity tests against this on >the released 4.12 kernel? We didn't start trying to suppress flushes until then >so we should probably verify things still actually work after enabling it. Didn't know about the sanity tests. I'll look into it and make sure we're no worse off than before.
diff --git a/hw/npu2.c b/hw/npu2.c index d3fa930..dfe8622 100644 --- a/hw/npu2.c +++ b/hw/npu2.c @@ -795,6 +795,11 @@ static void npu2_hw_init(struct npu2 *p) val = npu2_read(p, NPU2_XTS_CFG); npu2_write(p, NPU2_XTS_CFG, val | NPU2_XTS_CFG_MMIOSD | NPU2_XTS_CFG_TRY_ATR_RO); + if (!is_p9dd1()) { + val = npu2_read(p, NPU2_XTS_CFG2); + npu2_write(p, NPU2_XTS_CFG2, val | NPU2_XTS_CFG2_NO_FLUSH_ENA); + } + /* Init memory cache directory (MCD) registers. */ phys_map_get(p->chip_id, GPU_MEM, NPU2_LINKS_PER_CHIP - 1, &gpu_min_addr, NULL); diff --git a/include/npu2-regs.h b/include/npu2-regs.h index 737b380..960792f 100644 --- a/include/npu2-regs.h +++ b/include/npu2-regs.h @@ -403,6 +403,7 @@ void npu2_write_mask(struct npu2 *p, uint64_t reg, uint64_t val, uint64_t mask); #define NPU2_XTS_CFG_MMIOSD PPC_BIT(1) #define NPU2_XTS_CFG_TRY_ATR_RO PPC_BIT(6) #define NPU2_XTS_CFG2 NPU2_REG_OFFSET(NPU2_STACK_MISC, NPU2_BLOCK_XTS, 0x028) +#define NPU2_XTS_CFG2_NO_FLUSH_ENA PPC_BIT(49) #define NPU2_XTS_DBG_CFG0 NPU2_REG_OFFSET(NPU2_STACK_MISC, NPU2_BLOCK_XTS, 0x030) #define NPU2_XTS_DBG_CFG1 NPU2_REG_OFFSET(NPU2_STACK_MISC, NPU2_BLOCK_XTS, 0x038) #define NPU2_XTS_PMU_CNT NPU2_REG_OFFSET(NPU2_STACK_MISC, NPU2_BLOCK_XTS, 0x040)
POWER9 DD2 has added a new bit we'd like to set: "XTS_CONFIG2_NO_FLUSH_ENA: if enabled, allows MMIO ATSDs to suppress the flush" Cc: Alistair Popple <alistair@popple.id.au> Signed-off-by: Reza Arbab <arbab@linux.vnet.ibm.com> --- hw/npu2.c | 5 +++++ include/npu2-regs.h | 1 + 2 files changed, 6 insertions(+)