[1/4] powerpc/mm/radix: Don't iterate all sets when flushing the PWC

Message ID 20170714015258.7933-1-benh@kernel.crashing.org
State Superseded
Headers show

Commit Message

Benjamin Herrenschmidt July 14, 2017, 1:52 a.m.
The PWC flush only needs a single set call, just like the
full (RIC=2) flush.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
 arch/powerpc/mm/tlb-radix.c | 11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

Comments

Aneesh Kumar K.V July 14, 2017, 5:41 a.m. | #1
Benjamin Herrenschmidt <benh@kernel.crashing.org> writes:

> The PWC flush only needs a single set call, just like the
> full (RIC=2) flush.
>
> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> ---
>  arch/powerpc/mm/tlb-radix.c | 11 +++++++----
>  1 file changed, 7 insertions(+), 4 deletions(-)
>
> diff --git a/arch/powerpc/mm/tlb-radix.c b/arch/powerpc/mm/tlb-radix.c
> index 02e7140..5403419 100644
> --- a/arch/powerpc/mm/tlb-radix.c
> +++ b/arch/powerpc/mm/tlb-radix.c
> @@ -52,12 +52,15 @@ static inline void _tlbiel_pid(unsigned long pid, unsigned long ric)
>  	 */
>  	__tlbiel_pid(pid, 0, ric);
>
> -	if (ric == RIC_FLUSH_ALL)
> -		/* For the remaining sets, just flush the TLB */
> -		ric = RIC_FLUSH_TLB;
> +	/* For PWC, only one flush is needed */
> +	if (ric == RIC_FLUSH_PWC) {
> +		asm volatile("ptesync": : :"memory");
> +		return;
> +	}
>
> +	/* For the remaining sets, just flush the TLB */
>  	for (set = 1; set < POWER9_TLB_SETS_RADIX ; set++)
> -		__tlbiel_pid(pid, set, ric);
> +		__tlbiel_pid(pid, set, RIC_FLUSH_TLB);
>
>  	asm volatile("ptesync": : :"memory");
>  	asm volatile(PPC_INVALIDATE_ERAT "; isync" : : :"memory");


With the current code, we use tlbiel_pwc() for doing a pwc flush.
and that does what is done this patch. May be we can update this patch
such that we drop tlbiel_pwc and switch all those instance to
tlbiel_pid(pid, RIC_FLUSH_PWC) ?

You already do this in a later patch.

-aneesh
Benjamin Herrenschmidt July 14, 2017, 6:21 a.m. | #2
On Fri, 2017-07-14 at 11:11 +0530, Aneesh Kumar K.V wrote:
> With the current code, we use tlbiel_pwc() for doing a pwc flush.
> and that does what is done this patch. May be we can update this patch
> such that we drop tlbiel_pwc and switch all those instance to
> tlbiel_pid(pid, RIC_FLUSH_PWC) ?
> 
> You already do this in a later patch.

Right, I do it in a later latch and I prefer to keep it this way, to
avoid doing too many changes in a single patch.

Ben.
Aneesh Kumar K.V July 14, 2017, 7:03 a.m. | #3
Benjamin Herrenschmidt <benh@kernel.crashing.org> writes:

> On Fri, 2017-07-14 at 11:11 +0530, Aneesh Kumar K.V wrote:
>> With the current code, we use tlbiel_pwc() for doing a pwc flush.
>> and that does what is done this patch. May be we can update this patch
>> such that we drop tlbiel_pwc and switch all those instance to
>> tlbiel_pid(pid, RIC_FLUSH_PWC) ?
>> 
>> You already do this in a later patch.
>
> Right, I do it in a later latch and I prefer to keep it this way, to
> avoid doing too many changes in a single patch.

The commit message do indicate that we don't do flushing correctly for
PWC flush with the current code. That is not correct. May be update the
commit message then ?

-aneesh
Benjamin Herrenschmidt July 14, 2017, 7:21 a.m. | #4
On Fri, 2017-07-14 at 12:33 +0530, Aneesh Kumar K.V wrote:
> Benjamin Herrenschmidt <benh@kernel.crashing.org> writes:
> 
> > On Fri, 2017-07-14 at 11:11 +0530, Aneesh Kumar K.V wrote:
> > > With the current code, we use tlbiel_pwc() for doing a pwc flush.
> > > and that does what is done this patch. May be we can update this patch
> > > such that we drop tlbiel_pwc and switch all those instance to
> > > tlbiel_pid(pid, RIC_FLUSH_PWC) ?
> > > 
> > > You already do this in a later patch.
> > 
> > Right, I do it in a later latch and I prefer to keep it this way, to
> > avoid doing too many changes in a single patch.
> 
> The commit message do indicate that we don't do flushing correctly for
> PWC flush with the current code. That is not correct. May be update the
> commit message then ?

Yeah ok.

Ben.

Patch

diff --git a/arch/powerpc/mm/tlb-radix.c b/arch/powerpc/mm/tlb-radix.c
index 02e7140..5403419 100644
--- a/arch/powerpc/mm/tlb-radix.c
+++ b/arch/powerpc/mm/tlb-radix.c
@@ -52,12 +52,15 @@  static inline void _tlbiel_pid(unsigned long pid, unsigned long ric)
 	 */
 	__tlbiel_pid(pid, 0, ric);
 
-	if (ric == RIC_FLUSH_ALL)
-		/* For the remaining sets, just flush the TLB */
-		ric = RIC_FLUSH_TLB;
+	/* For PWC, only one flush is needed */
+	if (ric == RIC_FLUSH_PWC) {
+		asm volatile("ptesync": : :"memory");
+		return;
+	}
 
+	/* For the remaining sets, just flush the TLB */
 	for (set = 1; set < POWER9_TLB_SETS_RADIX ; set++)
-		__tlbiel_pid(pid, set, ric);
+		__tlbiel_pid(pid, set, RIC_FLUSH_TLB);
 
 	asm volatile("ptesync": : :"memory");
 	asm volatile(PPC_INVALIDATE_ERAT "; isync" : : :"memory");