[2/2] net: ethernet: nixge: Add support for National Instruments XGE netdev

Add support for the National Instruments XGE 1/10G network device.

It uses the EEPROM on the board via NVMEM.

Signed-off-by: Moritz Fischer <mdf@kernel.org>
---
 drivers/net/ethernet/Kconfig     |    1 +
 drivers/net/ethernet/Makefile    |    1 +
 drivers/net/ethernet/ni/Kconfig  |   26 +
 drivers/net/ethernet/ni/Makefile |    1 +
 drivers/net/ethernet/ni/nixge.c  | 1246 ++++++++++++++++++++++++++++++++++++++
 5 files changed, 1275 insertions(+)
 create mode 100644 drivers/net/ethernet/ni/Kconfig
 create mode 100644 drivers/net/ethernet/ni/Makefile
 create mode 100644 drivers/net/ethernet/ni/nixge.c

> +++ b/drivers/net/ethernet/ni/nixge.c
> @@ -0,0 +1,1246 @@
> +/*
> + * Copyright (c) 2016-2017, National Instruments Corp.
> + *
> + * Network Driver for Ettus Research XGE MAC
> + *
> + * This is largely based on the Xilinx AXI Ethernet Driver,
> + * and uses the same DMA engine in the FPGA

Hi Moritz 

Is the DMA code the same as in the AXI driver? Should it be pulled out
into a library and shared?

> +struct nixge_priv {
> +	struct net_device *ndev;
> +	struct device *dev;
> +
> +	/* Connection to PHY device */
> +	struct phy_device *phy_dev;
> +	phy_interface_t		phy_interface;

> +	/* protecting link parameters */
> +	spinlock_t              lock;
> +	int link;
> +	int speed;
> +	int duplex;

All these seem to be pointless. They are set, but never used.

> +
> +static inline void nixge_dma_write_reg(struct nixge_priv *priv, off_t offset,
> +				       u32 val)

Please leave it up to the compile to inline.

> +static void __nixge_device_reset(struct nixge_priv *priv, off_t offset)
> +{
> +	u32 timeout;
> +	/* Reset Axi DMA. This would reset NIXGE Ethernet core as well.
> +	 * The reset process of Axi DMA takes a while to complete as all
> +	 * pending commands/transfers will be flushed or completed during
> +	 * this reset process.
> +	 */
> +	nixge_dma_write_reg(priv, offset, XAXIDMA_CR_RESET_MASK);
> +	timeout = DELAY_OF_ONE_MILLISEC;
> +	while (nixge_dma_read_reg(priv, offset) & XAXIDMA_CR_RESET_MASK) {
> +		udelay(1);

There is a link between the 1 and the value of DELAY_OF_ONE_MILLISEC.
It would be good to try to link these two together.

> +		if (--timeout == 0) {
> +			netdev_err(priv->ndev, "%s: DMA reset timeout!\n",
> +				   __func__);
> +			break;
> +		}
> +	}
> +}
> +

> +static void nixge_handle_link_change(struct net_device *ndev)
> +{
> +	struct nixge_priv *priv = netdev_priv(ndev);
> +	struct phy_device *phydev = ndev->phydev;
> +	unsigned long flags;
> +	int status_change = 0;
> +
> +	spin_lock_irqsave(&priv->lock, flags);
> +
> +	if (phydev->link != priv->link) {
> +		if (!phydev->link) {
> +			priv->speed = 0;
> +			priv->duplex = -1;
> +		}
> +		priv->link = phydev->link;
> +
> +		status_change = 1;
> +	}
> +
> +	spin_unlock_irqrestore(&priv->lock, flags);
> +
> +	if (status_change) {
> +		if (phydev->link) {
> +			netif_carrier_on(ndev);
> +			netdev_info(ndev, "link up (%d/%s)\n",
> +				    phydev->speed,
> +				    phydev->duplex == DUPLEX_FULL ?
> +				    "Full" : "Half");
> +		} else {
> +			netif_carrier_off(ndev);
> +			netdev_info(ndev, "link down\n");
> +		}

phy_print_status() should be used.

Also, the phylib will handle netif_carrier_off/on for you.

> +static int nixge_open(struct net_device *ndev)
> +{
> +	struct nixge_priv *priv = netdev_priv(ndev);
> +	int ret;
> +
> +	nixge_device_reset(ndev);
> +
> +	/* start netif carrier down */
> +	netif_carrier_off(ndev);
> +
> +	if (!ndev->phydev)
> +		netdev_err(ndev, "no phy, phy_start() failed\n");

Not really correct. You don't call phy_start(). And phy_start() cannot
indicate a failure, it is a void function.

It would be a lot better to bail out if there is no phy. Probably
during probe.

> +static s32 __nixge_set_mac_address(struct net_device *ndev, const void *addr)
> +{
> +	struct nixge_priv *priv = netdev_priv(ndev);
> +
> +	if (addr)
> +		memcpy(ndev->dev_addr, addr, ETH_ALEN);
> +	if (!is_valid_ether_addr(ndev->dev_addr))
> +		eth_random_addr(ndev->dev_addr);

Messy. I would change this. Make addr mandatory. If it is invalid,
return an error. That will make nixge_net_set_mac_address() do the
right thing. When called from nixge_probe() should verify what it gets
from the nvmem, and if it is invalid, pass a random MAC address.

> +
> +	nixge_ctrl_write_reg(priv, NIXGE_REG_MAC_LSB,
> +			     (ndev->dev_addr[2]) << 24 |
> +			     (ndev->dev_addr[3] << 16) |
> +			     (ndev->dev_addr[4] << 8) |
> +			     (ndev->dev_addr[5] << 0));
> +
> +	nixge_ctrl_write_reg(priv, NIXGE_REG_MAC_MSB,
> +			     (ndev->dev_addr[1] | (ndev->dev_addr[0] << 8)));
> +
> +	return 0;
> +}
> +

> +static void nixge_ethtools_get_drvinfo(struct net_device *ndev,
> +				       struct ethtool_drvinfo *ed)
> +{
> +	strlcpy(ed->driver, "nixge", sizeof(ed->driver));
> +	strlcpy(ed->version, "1.00a", sizeof(ed->version));

Driver version is pretty pointless. What does 1.00a mean? Say it gets
backported into F26. Is it still 1.00a even though lots of things
around it have changed?


> +int nixge_mdio_read(struct mii_bus *bus, int phy_id, int reg)
> +{
> +	struct nixge_priv *priv = bus->priv;
> +	u32 status, tmp;
> +	int err;
> +	u16 device;
> +
> +	if (reg & MII_ADDR_C45) {
> +		device = (reg >> 16) & 0x1f;
> +
> +		nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_ADDR, reg & 0xffff);
> +
> +		tmp = NIXGE_MDIO_CLAUSE45 | NIXGE_MDIO_OP(NIXGE_MDIO_OP_ADDRESS)
> +			| NIXGE_MDIO_ADDR(phy_id) | NIXGE_MDIO_MMD(device);
> +
> +		nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_OP, tmp);
> +		nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_CTRL, 1);
> +
> +		err = nixge_ctrl_poll_timeout(priv, NIXGE_REG_MDIO_CTRL, status,
> +					      !status, 10, 1000);
> +		if (err) {
> +			dev_err(priv->dev, "timeout setting address");
> +			return -ETIMEDOUT;

Better to return err.

> +		}
> +
> +		tmp = NIXGE_MDIO_CLAUSE45 | NIXGE_MDIO_OP(NIXGE_MDIO_OP_READ) |
> +			NIXGE_MDIO_ADDR(phy_id) | NIXGE_MDIO_MMD(device);
> +	} else {
> +		device = reg & 0x1f;
> +
> +		tmp = NIXGE_MDIO_CLAUSE22 | NIXGE_MDIO_OP(MDIO_C22_READ) |
> +			NIXGE_MDIO_ADDR(phy_id) | NIXGE_MDIO_MMD(device);
> +	}
> +
> +	nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_OP, tmp);
> +	nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_CTRL, 1);
> +
> +	err = nixge_ctrl_poll_timeout(priv, NIXGE_REG_MDIO_CTRL, status,
> +				      !status, 10, 1000);
> +	if (err) {
> +		dev_err(priv->dev, "timeout setting read command");
> +		return -ETIMEDOUT;

Again, return err.

> +	}
> +
> +	status = nixge_ctrl_read_reg(priv, NIXGE_REG_MDIO_DATA);
> +
> +	dev_dbg(priv->dev, "%s: phy_id = %x reg = %x got %x\n", __func__,
> +		phy_id, reg & 0xffff, status);
> +
> +	return status;
> +}
> +
> +int nixge_mdio_write(struct mii_bus *bus, int phy_id, int reg, u16 val)
> +{
> +	struct nixge_priv *priv = bus->priv;
> +	u32 status, tmp;
> +	int err;
> +	u16 device;
> +
> +	/* FIXME: Currently don't do writes */
> +	if (reg & MII_ADDR_C45)
> +		return 0;

-EOPNOTSUPP would be better.

> +
> +	device = reg & 0x1f;
> +
> +	tmp = NIXGE_MDIO_CLAUSE22 | NIXGE_MDIO_OP(MDIO_C22_WRITE) |
> +		NIXGE_MDIO_ADDR(phy_id) | NIXGE_MDIO_MMD(device);
> +
> +	nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_DATA, val);
> +	nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_OP, tmp);
> +	nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_CTRL, 1);
> +
> +	err = nixge_ctrl_poll_timeout(priv, NIXGE_REG_MDIO_CTRL, status,
> +				      !status, 10, 1000);
> +	if (err) {
> +		dev_err(priv->dev, "timeout setting write command");
> +		return -ETIMEDOUT;
> +	}
> +
> +	dev_dbg(priv->dev, "%x %x <- %x\n", phy_id, reg, val);
> +
> +	return 0;
> +}
> +
> +int nixge_mdio_setup(struct nixge_priv *priv, struct device_node *np)
> +{
> +	struct mii_bus *bus;
> +	struct resource res;
> +	int err;
> +
> +	bus = mdiobus_alloc();
> +	if (!bus)
> +		return -ENOMEM;
> +
> +	of_address_to_resource(np, 0, &res);
> +	snprintf(bus->id, MII_BUS_ID_SIZE, "%.8llx",
> +		 (unsigned long long)res.start);

There are more meaningful things you could use, e.g. dev_name(priv->dev)

> +	bus->priv = priv;
> +	bus->name = "NIXGE_MAC_mii_bus";
> +	bus->read = nixge_mdio_read;
> +	bus->write = nixge_mdio_write;
> +	bus->parent = priv->dev;
> +
> +	priv->mii_bus = bus;
> +	err = of_mdiobus_register(bus, np);
> +	if (err)
> +		goto err_register;
> +
> +	dev_info(priv->dev, "MDIO bus registered\n");
> +
> +	return 0;
> +
> +err_register:
> +	mdiobus_free(bus);
> +	return err;
> +}
> +
> +static void *nixge_get_nvmem_address(struct device *dev)
> +{
> +	struct nvmem_cell *cell;
> +	size_t cell_size;
> +	char *mac;
> +
> +	cell = nvmem_cell_get(dev, "address");
> +	if (IS_ERR(cell))
> +		return cell;
> +
> +	mac = nvmem_cell_read(cell, &cell_size);
> +	nvmem_cell_put(cell);
> +
> +	if (IS_ERR(mac))
> +		return mac;
> +
> +	return mac;

Pointless if()

> +}
> +
> +static int nixge_probe(struct platform_device *pdev)
> +{
> +	int err;
> +	struct nixge_priv *priv;
> +	struct net_device *ndev;
> +	struct resource *dmares;
> +	const char *mac_addr;
> +
> +	ndev = alloc_etherdev(sizeof(*priv));
> +	if (!ndev)
> +		return -ENOMEM;
> +
> +	platform_set_drvdata(pdev, ndev);
> +	SET_NETDEV_DEV(ndev, &pdev->dev);
> +
> +	ndev->flags &= ~IFF_MULTICAST;  /* clear multicast */
> +	ndev->features = NETIF_F_SG;
> +	ndev->netdev_ops = &nixge_netdev_ops;
> +	ndev->ethtool_ops = &nixge_ethtool_ops;
> +
> +	/* MTU range: 64 - 9000 */
> +	ndev->min_mtu = 64;
> +	ndev->max_mtu = NIXGE_JUMBO_MTU;
> +
> +	mac_addr = nixge_get_nvmem_address(&pdev->dev);
> +	if (mac_addr)
> +		ether_addr_copy(ndev->dev_addr, mac_addr);
> +	else
> +		eth_hw_addr_random(ndev);
> +
> +	priv = netdev_priv(ndev);
> +	priv->ndev = ndev;
> +	priv->dev = &pdev->dev;
> +
> +	priv->features = 0;
> +	/* default to this for now ... */
> +	priv->rxmem = 10000;
> +
> +	dmares = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +	priv->dma_regs = devm_ioremap_resource(&pdev->dev, dmares);
> +	if (IS_ERR(priv->dma_regs)) {
> +		dev_err(&pdev->dev, "failed to map dma regs\n");
> +		return PTR_ERR(priv->dma_regs);
> +	}
> +	priv->ctrl_regs = priv->dma_regs + 0x4000;
> +	__nixge_set_mac_address(ndev, mac_addr);
> +
> +	priv->tx_irq = platform_get_irq_byname(pdev, "tx-irq");
> +	if (priv->tx_irq < 0) {
> +		dev_err(&pdev->dev, "no tx irq available");
> +		return priv->tx_irq;
> +	}
> +
> +	priv->rx_irq = platform_get_irq_byname(pdev, "rx-irq");
> +	if (priv->rx_irq < 0) {
> +		dev_err(&pdev->dev, "no rx irq available");
> +		return priv->rx_irq;
> +	}
> +
> +	priv->coalesce_count_rx = XAXIDMA_DFT_RX_THRESHOLD;
> +	priv->coalesce_count_tx = XAXIDMA_DFT_TX_THRESHOLD;
> +
> +	spin_lock_init(&priv->lock);
> +
> +	err = nixge_mdio_setup(priv, pdev->dev.of_node);
> +	if (err) {
> +		dev_warn(&pdev->dev, "error registering mdio bus");
> +		goto free_netdev;
> +	}
> +
> +	priv->phy_dev = phy_find_first(priv->mii_bus);
> +	if (!priv->phy_dev) {
> +		dev_err(&pdev->dev, "error finding a phy ...");
> +		goto free_netdev;
> +	}

I don't recommend this. Enforce the binding has a phy-handle.

> +
> +	err = register_netdev(priv->ndev);
> +	if (err) {
> +		dev_err(priv->dev, "register_netdev() error (%i)\n", err);
> +		goto free_netdev;
> +	}
> +
> +	err = phy_connect_direct(ndev, priv->phy_dev, &nixge_handle_link_change,
> +				 priv->phy_interface);

and here use of_phy_connect().

And where do you set phy_interface? You should be reading it from
device tree.

> +	if (err) {
> +		dev_err(&pdev->dev, "failed to attach to phy ...");
> +		goto unregister_mdio;
> +	}
> +
> +	/* not sure if this is the correct way of dealing with this ... */
> +	ndev->phydev->supported &= ~(SUPPORTED_Autoneg);
> +	ndev->phydev->advertising = ndev->phydev->supported;
> +	ndev->phydev->autoneg = AUTONEG_DISABLE;

What are you trying to achieve?

     Andrew

Hi Andrew,

thanks for the quick response.

On Fri, Jul 14, 2017 at 12:36:36AM +0200, Andrew Lunn wrote:
> > +++ b/drivers/net/ethernet/ni/nixge.c
> > @@ -0,0 +1,1246 @@
> > +/*
> > + * Copyright (c) 2016-2017, National Instruments Corp.
> > + *
> > + * Network Driver for Ettus Research XGE MAC
> > + *
> > + * This is largely based on the Xilinx AXI Ethernet Driver,
> > + * and uses the same DMA engine in the FPGA
> 
> Hi Moritz 
> 
> Is the DMA code the same as in the AXI driver? Should it be pulled out
> into a library and shared?

Mostly, I'll see what I can do. At least the register definitions and
common structures can be pulled out into a common header file.

> 
> > +struct nixge_priv {
> > +	struct net_device *ndev;
> > +	struct device *dev;
> > +
> > +	/* Connection to PHY device */
> > +	struct phy_device *phy_dev;
> > +	phy_interface_t		phy_interface;
> 
> > +	/* protecting link parameters */
> > +	spinlock_t              lock;
> > +	int link;
> > +	int speed;
> > +	int duplex;
> 
> All these seem to be pointless. They are set, but never used.

Will fix.
> 
> > +
> > +static inline void nixge_dma_write_reg(struct nixge_priv *priv, off_t offset,
> > +				       u32 val)
> 
> Please leave it up to the compile to inline.

Will fix.
> 
> > +static void __nixge_device_reset(struct nixge_priv *priv, off_t offset)
> > +{
> > +	u32 timeout;
> > +	/* Reset Axi DMA. This would reset NIXGE Ethernet core as well.
> > +	 * The reset process of Axi DMA takes a while to complete as all
> > +	 * pending commands/transfers will be flushed or completed during
> > +	 * this reset process.
> > +	 */
> > +	nixge_dma_write_reg(priv, offset, XAXIDMA_CR_RESET_MASK);
> > +	timeout = DELAY_OF_ONE_MILLISEC;
> > +	while (nixge_dma_read_reg(priv, offset) & XAXIDMA_CR_RESET_MASK) {
> > +		udelay(1);
> 
> There is a link between the 1 and the value of DELAY_OF_ONE_MILLISEC.
> It would be good to try to link these two together.

D'oh ... Seems like a good candidate for iopoll ...
> 
> > +		if (--timeout == 0) {
> > +			netdev_err(priv->ndev, "%s: DMA reset timeout!\n",
> > +				   __func__);
> > +			break;
> > +		}
> > +	}
> > +}
> > +
> 
> > +static void nixge_handle_link_change(struct net_device *ndev)
> > +{
> > +	struct nixge_priv *priv = netdev_priv(ndev);
> > +	struct phy_device *phydev = ndev->phydev;
> > +	unsigned long flags;
> > +	int status_change = 0;
> > +
> > +	spin_lock_irqsave(&priv->lock, flags);
> > +
> > +	if (phydev->link != priv->link) {
> > +		if (!phydev->link) {
> > +			priv->speed = 0;
> > +			priv->duplex = -1;
> > +		}
> > +		priv->link = phydev->link;
> > +
> > +		status_change = 1;
> > +	}
> > +
> > +	spin_unlock_irqrestore(&priv->lock, flags);
> > +
> > +	if (status_change) {
> > +		if (phydev->link) {
> > +			netif_carrier_on(ndev);
> > +			netdev_info(ndev, "link up (%d/%s)\n",
> > +				    phydev->speed,
> > +				    phydev->duplex == DUPLEX_FULL ?
> > +				    "Full" : "Half");
> > +		} else {
> > +			netif_carrier_off(ndev);
> > +			netdev_info(ndev, "link down\n");
> > +		}
> 
> phy_print_status() should be used.

Will do.
> 
> Also, the phylib will handle netif_carrier_off/on for you.

Good to know :)
> 
> > +static int nixge_open(struct net_device *ndev)
> > +{
> > +	struct nixge_priv *priv = netdev_priv(ndev);
> > +	int ret;
> > +
> > +	nixge_device_reset(ndev);
> > +
> > +	/* start netif carrier down */
> > +	netif_carrier_off(ndev);
> > +
> > +	if (!ndev->phydev)
> > +		netdev_err(ndev, "no phy, phy_start() failed\n");
> 
> Not really correct. You don't call phy_start(). And phy_start() cannot
> indicate a failure, it is a void function.

Will fix.
> 
> It would be a lot better to bail out if there is no phy. Probably
> during probe.

Yeah.
> 
> > +static s32 __nixge_set_mac_address(struct net_device *ndev, const void *addr)
> > +{
> > +	struct nixge_priv *priv = netdev_priv(ndev);
> > +
> > +	if (addr)
> > +		memcpy(ndev->dev_addr, addr, ETH_ALEN);
> > +	if (!is_valid_ether_addr(ndev->dev_addr))
> > +		eth_random_addr(ndev->dev_addr);
> 
> Messy. I would change this. Make addr mandatory. If it is invalid,
> return an error. That will make nixge_net_set_mac_address() do the
> right thing. When called from nixge_probe() should verify what it gets
> from the nvmem, and if it is invalid, pass a random MAC address.

Will fix.
> 
> > +
> > +	nixge_ctrl_write_reg(priv, NIXGE_REG_MAC_LSB,
> > +			     (ndev->dev_addr[2]) << 24 |
> > +			     (ndev->dev_addr[3] << 16) |
> > +			     (ndev->dev_addr[4] << 8) |
> > +			     (ndev->dev_addr[5] << 0));
> > +
> > +	nixge_ctrl_write_reg(priv, NIXGE_REG_MAC_MSB,
> > +			     (ndev->dev_addr[1] | (ndev->dev_addr[0] << 8)));
> > +
> > +	return 0;
> > +}
> > +
> 
> > +static void nixge_ethtools_get_drvinfo(struct net_device *ndev,
> > +				       struct ethtool_drvinfo *ed)
> > +{
> > +	strlcpy(ed->driver, "nixge", sizeof(ed->driver));
> > +	strlcpy(ed->version, "1.00a", sizeof(ed->version));
> 
> Driver version is pretty pointless. What does 1.00a mean? Say it gets
> backported into F26. Is it still 1.00a even though lots of things
> around it have changed?

Maybe I can just drop drvinfo?
> 
> 
> > +int nixge_mdio_read(struct mii_bus *bus, int phy_id, int reg)
> > +{
> > +	struct nixge_priv *priv = bus->priv;
> > +	u32 status, tmp;
> > +	int err;
> > +	u16 device;
> > +
> > +	if (reg & MII_ADDR_C45) {
> > +		device = (reg >> 16) & 0x1f;
> > +
> > +		nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_ADDR, reg & 0xffff);
> > +
> > +		tmp = NIXGE_MDIO_CLAUSE45 | NIXGE_MDIO_OP(NIXGE_MDIO_OP_ADDRESS)
> > +			| NIXGE_MDIO_ADDR(phy_id) | NIXGE_MDIO_MMD(device);
> > +
> > +		nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_OP, tmp);
> > +		nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_CTRL, 1);
> > +
> > +		err = nixge_ctrl_poll_timeout(priv, NIXGE_REG_MDIO_CTRL, status,
> > +					      !status, 10, 1000);
> > +		if (err) {
> > +			dev_err(priv->dev, "timeout setting address");
> > +			return -ETIMEDOUT;
> 
> Better to return err.

Agreed.
> 
> > +		}
> > +
> > +		tmp = NIXGE_MDIO_CLAUSE45 | NIXGE_MDIO_OP(NIXGE_MDIO_OP_READ) |
> > +			NIXGE_MDIO_ADDR(phy_id) | NIXGE_MDIO_MMD(device);
> > +	} else {
> > +		device = reg & 0x1f;
> > +
> > +		tmp = NIXGE_MDIO_CLAUSE22 | NIXGE_MDIO_OP(MDIO_C22_READ) |
> > +			NIXGE_MDIO_ADDR(phy_id) | NIXGE_MDIO_MMD(device);
> > +	}
> > +
> > +	nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_OP, tmp);
> > +	nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_CTRL, 1);
> > +
> > +	err = nixge_ctrl_poll_timeout(priv, NIXGE_REG_MDIO_CTRL, status,
> > +				      !status, 10, 1000);
> > +	if (err) {
> > +		dev_err(priv->dev, "timeout setting read command");
> > +		return -ETIMEDOUT;
> 
> Again, return err.

Agreed.
> 
> > +	}
> > +
> > +	status = nixge_ctrl_read_reg(priv, NIXGE_REG_MDIO_DATA);
> > +
> > +	dev_dbg(priv->dev, "%s: phy_id = %x reg = %x got %x\n", __func__,
> > +		phy_id, reg & 0xffff, status);
> > +
> > +	return status;
> > +}
> > +
> > +int nixge_mdio_write(struct mii_bus *bus, int phy_id, int reg, u16 val)
> > +{
> > +	struct nixge_priv *priv = bus->priv;
> > +	u32 status, tmp;
> > +	int err;
> > +	u16 device;
> > +
> > +	/* FIXME: Currently don't do writes */
> > +	if (reg & MII_ADDR_C45)
> > +		return 0;
> 
> -EOPNOTSUPP would be better.

Agreed, ultimately I wanna implement that.
> 
> > +
> > +	device = reg & 0x1f;
> > +
> > +	tmp = NIXGE_MDIO_CLAUSE22 | NIXGE_MDIO_OP(MDIO_C22_WRITE) |
> > +		NIXGE_MDIO_ADDR(phy_id) | NIXGE_MDIO_MMD(device);
> > +
> > +	nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_DATA, val);
> > +	nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_OP, tmp);
> > +	nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_CTRL, 1);
> > +
> > +	err = nixge_ctrl_poll_timeout(priv, NIXGE_REG_MDIO_CTRL, status,
> > +				      !status, 10, 1000);
> > +	if (err) {
> > +		dev_err(priv->dev, "timeout setting write command");
> > +		return -ETIMEDOUT;
> > +	}
> > +
> > +	dev_dbg(priv->dev, "%x %x <- %x\n", phy_id, reg, val);
> > +
> > +	return 0;
> > +}
> > +
> > +int nixge_mdio_setup(struct nixge_priv *priv, struct device_node *np)
> > +{
> > +	struct mii_bus *bus;
> > +	struct resource res;
> > +	int err;
> > +
> > +	bus = mdiobus_alloc();
> > +	if (!bus)
> > +		return -ENOMEM;
> > +
> > +	of_address_to_resource(np, 0, &res);
> > +	snprintf(bus->id, MII_BUS_ID_SIZE, "%.8llx",
> > +		 (unsigned long long)res.start);
> 
> There are more meaningful things you could use, e.g. dev_name(priv->dev)

Agreed.
> 
> > +	bus->priv = priv;
> > +	bus->name = "NIXGE_MAC_mii_bus";
> > +	bus->read = nixge_mdio_read;
> > +	bus->write = nixge_mdio_write;
> > +	bus->parent = priv->dev;
> > +
> > +	priv->mii_bus = bus;
> > +	err = of_mdiobus_register(bus, np);
> > +	if (err)
> > +		goto err_register;
> > +
> > +	dev_info(priv->dev, "MDIO bus registered\n");
> > +
> > +	return 0;
> > +
> > +err_register:
> > +	mdiobus_free(bus);
> > +	return err;
> > +}
> > +
> > +static void *nixge_get_nvmem_address(struct device *dev)
> > +{
> > +	struct nvmem_cell *cell;
> > +	size_t cell_size;
> > +	char *mac;
> > +
> > +	cell = nvmem_cell_get(dev, "address");
> > +	if (IS_ERR(cell))
> > +		return cell;
> > +
> > +	mac = nvmem_cell_read(cell, &cell_size);
> > +	nvmem_cell_put(cell);
> > +
> > +	if (IS_ERR(mac))
> > +		return mac;
> > +
> > +	return mac;
> 
> Pointless if()

D'oh ... will fix.
> 
> > +}
> > +
> > +static int nixge_probe(struct platform_device *pdev)
> > +{
> > +	int err;
> > +	struct nixge_priv *priv;
> > +	struct net_device *ndev;
> > +	struct resource *dmares;
> > +	const char *mac_addr;
> > +
> > +	ndev = alloc_etherdev(sizeof(*priv));
> > +	if (!ndev)
> > +		return -ENOMEM;
> > +
> > +	platform_set_drvdata(pdev, ndev);
> > +	SET_NETDEV_DEV(ndev, &pdev->dev);
> > +
> > +	ndev->flags &= ~IFF_MULTICAST;  /* clear multicast */
> > +	ndev->features = NETIF_F_SG;
> > +	ndev->netdev_ops = &nixge_netdev_ops;
> > +	ndev->ethtool_ops = &nixge_ethtool_ops;
> > +
> > +	/* MTU range: 64 - 9000 */
> > +	ndev->min_mtu = 64;
> > +	ndev->max_mtu = NIXGE_JUMBO_MTU;
> > +
> > +	mac_addr = nixge_get_nvmem_address(&pdev->dev);
> > +	if (mac_addr)
> > +		ether_addr_copy(ndev->dev_addr, mac_addr);
> > +	else
> > +		eth_hw_addr_random(ndev);
> > +
> > +	priv = netdev_priv(ndev);
> > +	priv->ndev = ndev;
> > +	priv->dev = &pdev->dev;
> > +
> > +	priv->features = 0;
> > +	/* default to this for now ... */
> > +	priv->rxmem = 10000;
> > +
> > +	dmares = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > +	priv->dma_regs = devm_ioremap_resource(&pdev->dev, dmares);
> > +	if (IS_ERR(priv->dma_regs)) {
> > +		dev_err(&pdev->dev, "failed to map dma regs\n");
> > +		return PTR_ERR(priv->dma_regs);
> > +	}
> > +	priv->ctrl_regs = priv->dma_regs + 0x4000;
> > +	__nixge_set_mac_address(ndev, mac_addr);
> > +
> > +	priv->tx_irq = platform_get_irq_byname(pdev, "tx-irq");
> > +	if (priv->tx_irq < 0) {
> > +		dev_err(&pdev->dev, "no tx irq available");
> > +		return priv->tx_irq;
> > +	}
> > +
> > +	priv->rx_irq = platform_get_irq_byname(pdev, "rx-irq");
> > +	if (priv->rx_irq < 0) {
> > +		dev_err(&pdev->dev, "no rx irq available");
> > +		return priv->rx_irq;
> > +	}
> > +
> > +	priv->coalesce_count_rx = XAXIDMA_DFT_RX_THRESHOLD;
> > +	priv->coalesce_count_tx = XAXIDMA_DFT_TX_THRESHOLD;
> > +
> > +	spin_lock_init(&priv->lock);
> > +
> > +	err = nixge_mdio_setup(priv, pdev->dev.of_node);
> > +	if (err) {
> > +		dev_warn(&pdev->dev, "error registering mdio bus");
> > +		goto free_netdev;
> > +	}
> > +
> > +	priv->phy_dev = phy_find_first(priv->mii_bus);
> > +	if (!priv->phy_dev) {
> > +		dev_err(&pdev->dev, "error finding a phy ...");
> > +		goto free_netdev;
> > +	}
> 
> I don't recommend this. Enforce the binding has a phy-handle.

Yeah, will move the of_phy_connect into open() and just check for
phandle here.
> 
> > +
> > +	err = register_netdev(priv->ndev);
> > +	if (err) {
> > +		dev_err(priv->dev, "register_netdev() error (%i)\n", err);
> > +		goto free_netdev;
> > +	}
> > +
> > +	err = phy_connect_direct(ndev, priv->phy_dev, &nixge_handle_link_change,
> > +				 priv->phy_interface);
> 
> and here use of_phy_connect().

I'll probably move that to the open()
> 
> And where do you set phy_interface? You should be reading it from
> device tree.

True.
> 
> > +	if (err) {
> > +		dev_err(&pdev->dev, "failed to attach to phy ...");
> > +		goto unregister_mdio;
> > +	}
> > +
> > +	/* not sure if this is the correct way of dealing with this ... */
> > +	ndev->phydev->supported &= ~(SUPPORTED_Autoneg);
> > +	ndev->phydev->advertising = ndev->phydev->supported;
> > +	ndev->phydev->autoneg = AUTONEG_DISABLE;
> 
> What are you trying to achieve?

Basically can't do Autoneg, I'll need to take a closer look.

> 
>      Andrew

Thanks for your feedback,

Moritz

> > > +	/* not sure if this is the correct way of dealing with this ... */
> > > +	ndev->phydev->supported &= ~(SUPPORTED_Autoneg);
> > > +	ndev->phydev->advertising = ndev->phydev->supported;
> > > +	ndev->phydev->autoneg = AUTONEG_DISABLE;
> > 
> > What are you trying to achieve?
> 
> Basically can't do Autoneg, I'll need to take a closer look.

Hi Moritz

What i actually think you mean, is it can only do 1Gbps. So you could
autoneg, but only advertise 1Gbps. Look at masking out
PHY_10BT_FEATURES and PHY_100BT_FEATURES.

Take a look at:

http://elixir.free-electrons.com/linux/latest/source/drivers/net/ethernet/renesas/ravb_main.c#L1045

It might actually make sense to add a phy_set_min_speed(), a mirror to
phy_set_max_speed().

	Andrew

Hi Andrew,

On Thu, Jul 13, 2017 at 6:34 PM, Andrew Lunn <andrew@lunn.ch> wrote:
>> > > + /* not sure if this is the correct way of dealing with this ... */
>> > > + ndev->phydev->supported &= ~(SUPPORTED_Autoneg);
>> > > + ndev->phydev->advertising = ndev->phydev->supported;
>> > > + ndev->phydev->autoneg = AUTONEG_DISABLE;
>> >
>> > What are you trying to achieve?
>>
>> Basically can't do Autoneg, I'll need to take a closer look.
>
> Hi Moritz
>
> What i actually think you mean, is it can only do 1Gbps. So you could
> autoneg, but only advertise 1Gbps. Look at masking out
> PHY_10BT_FEATURES and PHY_100BT_FEATURES.

It does either 1Gbps or 10Gbps (over SFP+), depending which bitstream is loaded
into the  FPGA. In the current setup I could also just have two
different compatible
strings, since neither setup supports the other rate, but that might change.

It seems getting rid of that part (the default values) now works, too.

I'll need to take a closer look tomorrow (and I need to retest with 1Gbps)

>
> Take a look at:
>
> http://elixir.free-electrons.com/linux/latest/source/drivers/net/ethernet/renesas/ravb_main.c#L1045

Will do.

Thanks for feedback,

Moritz

Hi Moritz,

[auto build test WARNING on net-next/master]
[also build test WARNING on v4.12 next-20170713]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

url:    https://github.com/0day-ci/linux/commits/Moritz-Fischer/dt-bindings-net-Add-bindings-for-National-Instruments-XGE-netdev/20170714-125718
config: ia64-allmodconfig (attached as .config)
compiler: ia64-linux-gcc (GCC) 6.2.0
reproduce:
        wget https://raw.githubusercontent.com/01org/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # save the attached .config to linux build tree
        make.cross ARCH=ia64 

All warnings (new ones prefixed by >>):

   In file included from include/linux/if_ether.h:23:0,
                    from include/linux/etherdevice.h:25,
                    from drivers/net/ethernet/ni/nixge.c:14:
   drivers/net/ethernet/ni/nixge.c: In function 'nixge_dma_bd_release':
>> drivers/net/ethernet/ni/nixge.c:241:17: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
      dev_kfree_skb((struct sk_buff *)
                    ^
   include/linux/skbuff.h:977:38: note: in definition of macro 'dev_kfree_skb'
    #define dev_kfree_skb(a) consume_skb(a)
                                         ^
   drivers/net/ethernet/ni/nixge.c: In function 'nixge_dma_bd_init':
>> drivers/net/ethernet/ni/nixge.c:299:35: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
      priv->rx_bd_v[i].sw_id_offset = (u32)skb;
                                      ^
   drivers/net/ethernet/ni/nixge.c: In function 'nixge_start_xmit_done':
   drivers/net/ethernet/ni/nixge.c:452:22: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
       dev_kfree_skb_irq((struct sk_buff *)cur_p->app4);
                         ^
   drivers/net/ethernet/ni/nixge.c: In function 'nixge_recv':
   drivers/net/ethernet/ni/nixge.c:546:9: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
      skb = (struct sk_buff *)(cur_p->sw_id_offset);
            ^
   drivers/net/ethernet/ni/nixge.c:577:25: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
      cur_p->sw_id_offset = (u32)new_skb;
                            ^
   drivers/net/ethernet/ni/nixge.c: In function 'nixge_dma_err_handler':
   drivers/net/ethernet/ni/nixge.c:687:22: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
       dev_kfree_skb_irq((struct sk_buff *)cur_p->app4);
                         ^

vim +241 drivers/net/ethernet/ni/nixge.c

   228	
   229	#define nixge_ctrl_poll_timeout(priv, addr, val, cond, sleep_us, timeout_us) \
   230		readl_poll_timeout((priv)->ctrl_regs + (addr), (val), cond, \
   231				   (sleep_us), (timeout_us))
   232	
   233	static void nixge_dma_bd_release(struct net_device *ndev)
   234	{
   235		int i;
   236		struct nixge_priv *priv = netdev_priv(ndev);
   237	
   238		for (i = 0; i < RX_BD_NUM; i++) {
   239			dma_unmap_single(ndev->dev.parent, priv->rx_bd_v[i].phys,
   240					 priv->max_frm_size, DMA_FROM_DEVICE);
 > 241			dev_kfree_skb((struct sk_buff *)
   242				      (priv->rx_bd_v[i].sw_id_offset));
   243		}
   244	
   245		if (priv->rx_bd_v) {
   246			dma_free_coherent(ndev->dev.parent,
   247					  sizeof(*priv->rx_bd_v) * RX_BD_NUM,
   248					  priv->rx_bd_v,
   249					  priv->rx_bd_p);
   250		}
   251		if (priv->tx_bd_v) {
   252			dma_free_coherent(ndev->dev.parent,
   253					  sizeof(*priv->tx_bd_v) * TX_BD_NUM,
   254					  priv->tx_bd_v,
   255					  priv->tx_bd_p);
   256		}
   257	}
   258	
   259	static int nixge_dma_bd_init(struct net_device *ndev)
   260	{
   261		u32 cr;
   262		int i;
   263		struct sk_buff *skb;
   264		struct nixge_priv *priv = netdev_priv(ndev);
   265	
   266		/* Reset the indexes which are used for accessing the BDs */
   267		priv->tx_bd_ci = 0;
   268		priv->tx_bd_tail = 0;
   269		priv->rx_bd_ci = 0;
   270	
   271		/* Allocate the Tx and Rx buffer descriptors. */
   272		priv->tx_bd_v = dma_zalloc_coherent(ndev->dev.parent,
   273						  sizeof(*priv->tx_bd_v) * TX_BD_NUM,
   274						  &priv->tx_bd_p, GFP_KERNEL);
   275		if (!priv->tx_bd_v)
   276			goto out;
   277	
   278		priv->rx_bd_v = dma_zalloc_coherent(ndev->dev.parent,
   279						  sizeof(*priv->rx_bd_v) * RX_BD_NUM,
   280						  &priv->rx_bd_p, GFP_KERNEL);
   281		if (!priv->rx_bd_v)
   282			goto out;
   283	
   284		for (i = 0; i < TX_BD_NUM; i++) {
   285			priv->tx_bd_v[i].next = priv->tx_bd_p +
   286					      sizeof(*priv->tx_bd_v) *
   287					      ((i + 1) % TX_BD_NUM);
   288		}
   289	
   290		for (i = 0; i < RX_BD_NUM; i++) {
   291			priv->rx_bd_v[i].next = priv->rx_bd_p +
   292					      sizeof(*priv->rx_bd_v) *
   293					      ((i + 1) % RX_BD_NUM);
   294	
   295			skb = netdev_alloc_skb_ip_align(ndev, priv->max_frm_size);
   296			if (!skb)
   297				goto out;
   298	
 > 299			priv->rx_bd_v[i].sw_id_offset = (u32)skb;
   300			priv->rx_bd_v[i].phys = dma_map_single(ndev->dev.parent,
   301							     skb->data,
   302							     priv->max_frm_size,
   303							     DMA_FROM_DEVICE);
   304			priv->rx_bd_v[i].cntrl = priv->max_frm_size;
   305		}
   306	
   307		/* Start updating the Rx channel control register */
   308		cr = nixge_dma_read_reg(priv, XAXIDMA_RX_CR_OFFSET);
   309		/* Update the interrupt coalesce count */
   310		cr = ((cr & ~XAXIDMA_COALESCE_MASK) |
   311		      ((priv->coalesce_count_rx) << XAXIDMA_COALESCE_SHIFT));
   312		/* Update the delay timer count */
   313		cr = ((cr & ~XAXIDMA_DELAY_MASK) |
   314		      (XAXIDMA_DFT_RX_WAITBOUND << XAXIDMA_DELAY_SHIFT));
   315		/* Enable coalesce, delay timer and error interrupts */
   316		cr |= XAXIDMA_IRQ_ALL_MASK;
   317		/* Write to the Rx channel control register */
   318		nixge_dma_write_reg(priv, XAXIDMA_RX_CR_OFFSET, cr);
   319	
   320		/* Start updating the Tx channel control register */
   321		cr = nixge_dma_read_reg(priv, XAXIDMA_TX_CR_OFFSET);
   322		/* Update the interrupt coalesce count */
   323		cr = (((cr & ~XAXIDMA_COALESCE_MASK)) |
   324		      ((priv->coalesce_count_tx) << XAXIDMA_COALESCE_SHIFT));
   325		/* Update the delay timer count */
   326		cr = (((cr & ~XAXIDMA_DELAY_MASK)) |
   327		      (XAXIDMA_DFT_TX_WAITBOUND << XAXIDMA_DELAY_SHIFT));
   328		/* Enable coalesce, delay timer and error interrupts */
   329		cr |= XAXIDMA_IRQ_ALL_MASK;
   330		/* Write to the Tx channel control register */
   331		nixge_dma_write_reg(priv, XAXIDMA_TX_CR_OFFSET, cr);
   332	
   333		/* Populate the tail pointer and bring the Rx Axi DMA engine out of
   334		 * halted state. This will make the Rx side ready for reception.
   335		 */
   336		nixge_dma_write_reg(priv, XAXIDMA_RX_CDESC_OFFSET, priv->rx_bd_p);
   337		cr = nixge_dma_read_reg(priv, XAXIDMA_RX_CR_OFFSET);
   338		nixge_dma_write_reg(priv, XAXIDMA_RX_CR_OFFSET,
   339				    cr | XAXIDMA_CR_RUNSTOP_MASK);
   340		nixge_dma_write_reg(priv, XAXIDMA_RX_TDESC_OFFSET, priv->rx_bd_p +
   341				    (sizeof(*priv->rx_bd_v) * (RX_BD_NUM - 1)));
   342	
   343		/* Write to the RS (Run-stop) bit in the Tx channel control register.
   344		 * Tx channel is now ready to run. But only after we write to the
   345		 * tail pointer register that the Tx channel will start transmitting.
   346		 */
   347		nixge_dma_write_reg(priv, XAXIDMA_TX_CDESC_OFFSET, priv->tx_bd_p);
   348		cr = nixge_dma_read_reg(priv, XAXIDMA_TX_CR_OFFSET);
   349		nixge_dma_write_reg(priv, XAXIDMA_TX_CR_OFFSET,
   350				    cr | XAXIDMA_CR_RUNSTOP_MASK);
   351	
   352		return 0;
   353	out:
   354		nixge_dma_bd_release(ndev);
   355		return -ENOMEM;
   356	}
   357	

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation

Hi Moritz,

[auto build test ERROR on net-next/master]
[also build test ERROR on v4.12 next-20170714]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

url:    https://github.com/0day-ci/linux/commits/Moritz-Fischer/dt-bindings-net-Add-bindings-for-National-Instruments-XGE-netdev/20170714-125718
config: um-allyesconfig (attached as .config)
compiler: gcc-6 (Debian 6.2.0-3) 6.2.0 20160901
reproduce:
        # save the attached .config to linux build tree
        make ARCH=um 

All errors (new ones prefixed by >>):

   arch/um/drivers/built-in.o: In function `vde_open_real':
   (.text+0xc9f1): warning: Using 'getgrnam' in statically linked applications requires at runtime the shared libraries from the glibc version used for linking
   arch/um/drivers/built-in.o: In function `vde_open_real':
   (.text+0xc83c): warning: Using 'getpwuid' in statically linked applications requires at runtime the shared libraries from the glibc version used for linking
   arch/um/drivers/built-in.o: In function `vde_open_real':
   (.text+0xcb55): warning: Using 'getaddrinfo' in statically linked applications requires at runtime the shared libraries from the glibc version used for linking
   arch/um/drivers/built-in.o: In function `pcap_nametoaddr':
   (.text+0x1d5e5): warning: Using 'gethostbyname' in statically linked applications requires at runtime the shared libraries from the glibc version used for linking
   arch/um/drivers/built-in.o: In function `pcap_nametonetaddr':
   (.text+0x1d685): warning: Using 'getnetbyname' in statically linked applications requires at runtime the shared libraries from the glibc version used for linking
   arch/um/drivers/built-in.o: In function `pcap_nametoproto':
   (.text+0x1d8a5): warning: Using 'getprotobyname' in statically linked applications requires at runtime the shared libraries from the glibc version used for linking
   arch/um/drivers/built-in.o: In function `pcap_nametoport':
   (.text+0x1d6d7): warning: Using 'getservbyname' in statically linked applications requires at runtime the shared libraries from the glibc version used for linking
   drivers/built-in.o: In function `nixge_start_xmit':
>> include/linux/dma-mapping.h:210: undefined reference to `bad_dma_ops'
   drivers/built-in.o: In function `nixge_dma_bd_release':
>> drivers/net/ethernet/ni/nixge.c:234: undefined reference to `bad_dma_ops'
   drivers/built-in.o: In function `nixge_dma_bd_release':
   include/linux/dma-mapping.h:504: undefined reference to `bad_dma_ops'
   include/linux/dma-mapping.h:510: undefined reference to `bad_dma_ops'
   include/linux/dma-mapping.h:504: undefined reference to `bad_dma_ops'
   drivers/built-in.o:drivers/net/ethernet/ni/nixge.c:252: more undefined references to `bad_dma_ops' follow
   drivers/built-in.o: In function `nixge_mdio_setup':
>> drivers/net/ethernet/ni/nixge.c:1039: undefined reference to `of_address_to_resource'
   drivers/built-in.o: In function `nixge_probe':
>> drivers/net/ethernet/ni/nixge.c:1120: undefined reference to `devm_ioremap_resource'
   drivers/built-in.o: In function `img_ascii_lcd_probe':
   drivers/auxdisplay/img-ascii-lcd.c:386: undefined reference to `devm_ioremap_resource'
   collect2: error: ld returned 1 exit status

vim +234 drivers/net/ethernet/ni/nixge.c

   228	
   229	#define nixge_ctrl_poll_timeout(priv, addr, val, cond, sleep_us, timeout_us) \
   230		readl_poll_timeout((priv)->ctrl_regs + (addr), (val), cond, \
   231				   (sleep_us), (timeout_us))
   232	
   233	static void nixge_dma_bd_release(struct net_device *ndev)
 > 234	{
   235		int i;
   236		struct nixge_priv *priv = netdev_priv(ndev);
   237	
   238		for (i = 0; i < RX_BD_NUM; i++) {
   239			dma_unmap_single(ndev->dev.parent, priv->rx_bd_v[i].phys,
   240					 priv->max_frm_size, DMA_FROM_DEVICE);
   241			dev_kfree_skb((struct sk_buff *)
   242				      (priv->rx_bd_v[i].sw_id_offset));
   243		}
   244	
   245		if (priv->rx_bd_v) {
   246			dma_free_coherent(ndev->dev.parent,
   247					  sizeof(*priv->rx_bd_v) * RX_BD_NUM,
   248					  priv->rx_bd_v,
   249					  priv->rx_bd_p);
   250		}
   251		if (priv->tx_bd_v) {
   252			dma_free_coherent(ndev->dev.parent,
   253					  sizeof(*priv->tx_bd_v) * TX_BD_NUM,
   254					  priv->tx_bd_v,
   255					  priv->tx_bd_p);
   256		}
   257	}
   258	

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