Message ID | 1499878547-3452-3-git-send-email-ykaneko0929@gmail.com |
---|---|
State | New |
Headers | show |
Hi Kaneko-san, On Wed, Jul 12, 2017 at 6:55 PM, Yoshihiro Kaneko <ykaneko0929@gmail.com> wrote: > From: Takeshi Kihara <takeshi.kihara.df@renesas.com> > > This patch fixes to set IPSR register when using MSIOF3_SS1_E pin function > is selected. > > This is a correction to the incorrect implementation of IPSR register > pin assignment for R8A7796 SoC specification of R-Car Gen3 Hardware > User's Manual Rev.0.51E or later. > > Fixes: f9aece7344bd ("pinctrl: sh-pfc: Initial R8A7796 PFC support") > Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> > Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Identical to "[PATCH 4/5] pinctrl: sh-pfc: r8a7796: Fix IPSR setting for MSIOF3_SS1_E pin" I sent yesterday. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds -- To unsubscribe from this list: send the line "unsubscribe linux-gpio" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c index b2fb66f..87f21d7b 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c @@ -645,7 +645,7 @@ enum { PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1), PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1), PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1), - PINMUX_IPSR_MSEL(IP0_27_24, MSIOF3_SS1_E, SEL_MSIOF3_4), + PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_SS1_E, SEL_MSIOF3_4), /* IPSR1 */ PINMUX_IPSR_GPSR(IP1_3_0, IRQ2),