| Message ID | 20170711175937.23140-6-alex.bennee@linaro.org |
|---|---|
| State | New |
| Headers | show |
On 07/11/2017 07:59 AM, Alex Bennée wrote: > While an ISB will ensure any raised IRQs happen on the next > instruction it doesn't cause any to get raised by itself. We can > therefor use a simple tb exit for ISB instructions and rely on the > exit_request check at the top of each TB to deal with exiting if > needed. > > Signed-off-by: Alex Bennée<alex.bennee@linaro.org> > --- > target/arm/translate-a64.c | 2 +- > target/arm/translate.c | 4 ++-- > 2 files changed, 3 insertions(+), 3 deletions(-) Reviewed-by: Richard Henderson <rth@twiddle.net> r~
On Tue, Jul 11, 2017 at 18:59:36 +0100, Alex Bennée wrote: > While an ISB will ensure any raised IRQs happen on the next > instruction it doesn't cause any to get raised by itself. We can > therefor use a simple tb exit for ISB instructions and rely on the s/therefor/therefore/ > exit_request check at the top of each TB to deal with exiting if > needed. > > Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Emilio G. Cota <cota@braap.org> E.
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 66139b6046..2ac565eb10 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1393,7 +1393,7 @@ static void handle_sync(DisasContext *s, uint32_t insn, * a self-modified code correctly and also to take * any pending interrupts immediately. */ - s->is_jmp = DISAS_UPDATE; + gen_goto_tb(s, 0, s->pc); return; default: unallocated_encoding(s); diff --git a/target/arm/translate.c b/target/arm/translate.c index 82341ee709..dbf919cce3 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8169,7 +8169,7 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) * self-modifying code correctly and also to take * any pending interrupts immediately. */ - gen_lookup_tb(s); + gen_goto_tb(s, 0, s->pc & ~1); return; default: goto illegal_op; @@ -10562,7 +10562,7 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw * and also to take any pending interrupts * immediately. */ - gen_lookup_tb(s); + gen_goto_tb(s, 0, s->pc & ~1); break; default: goto illegal_op;
While an ISB will ensure any raised IRQs happen on the next instruction it doesn't cause any to get raised by itself. We can therefor use a simple tb exit for ISB instructions and rely on the exit_request check at the top of each TB to deal with exiting if needed. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> --- target/arm/translate-a64.c | 2 +- target/arm/translate.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-)