Message ID | 149943180765.8972.18399158340352150851.stgit@frigg.lan |
---|---|
State | New |
Headers | show |
Lluís Vilanova <vilanova@ac.upc.edu> writes: > Incrementally paves the way towards using the generic instruction translation > loop. > > Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu> > Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> > --- > target/arm/translate.c | 36 +++++++++++++++++++++--------------- > 1 file changed, 21 insertions(+), 15 deletions(-) > > diff --git a/target/arm/translate.c b/target/arm/translate.c > index 22af4e372a..7a1935d4d7 100644 > --- a/target/arm/translate.c > +++ b/target/arm/translate.c > @@ -11896,6 +11896,26 @@ static void arm_tr_tb_start(DisasContextBase *dcbase, CPUState *cpu) > } > } > > +static void arm_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) > +{ > + DisasContext *dc = container_of(dcbase, DisasContext, base); > + > + dc->insn_start_idx = tcg_op_buf_count(); > + tcg_gen_insn_start(dc->pc, > + (dc->condexec_cond << 4) | (dc->condexec_mask >> 1), > + 0); > + > +#ifdef CONFIG_USER_ONLY > + /* Intercept jump to the magic kernel page. */ > + if (dc->pc >= 0xffff0000) { > + /* We always get here via a jump, so know we are not in a > + conditional execution block. */ > + gen_exception_internal(EXCP_KERNEL_TRAP); > + dc->base.is_jmp = DISAS_EXC; > + } > +#endif > +} > + > /* generate intermediate code for basic block 'tb'. */ > void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) > { > @@ -11939,21 +11959,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) > > do { > dc->base.num_insns++; > - dc->insn_start_idx = tcg_op_buf_count(); > - tcg_gen_insn_start(dc->pc, > - (dc->condexec_cond << 4) | (dc->condexec_mask >> 1), > - 0); > - > -#ifdef CONFIG_USER_ONLY > - /* Intercept jump to the magic kernel page. */ > - if (dc->pc >= 0xffff0000) { > - /* We always get here via a jump, so know we are not in a > - conditional execution block. */ > - gen_exception_internal(EXCP_KERNEL_TRAP); > - dc->base.is_jmp = DISAS_EXC; > - break; > - } > -#endif > + arm_tr_insn_start(&dc->base, cs); > > if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { > CPUBreakpoint *bp; -- Alex Bennée
diff --git a/target/arm/translate.c b/target/arm/translate.c index 22af4e372a..7a1935d4d7 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -11896,6 +11896,26 @@ static void arm_tr_tb_start(DisasContextBase *dcbase, CPUState *cpu) } } +static void arm_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *dc = container_of(dcbase, DisasContext, base); + + dc->insn_start_idx = tcg_op_buf_count(); + tcg_gen_insn_start(dc->pc, + (dc->condexec_cond << 4) | (dc->condexec_mask >> 1), + 0); + +#ifdef CONFIG_USER_ONLY + /* Intercept jump to the magic kernel page. */ + if (dc->pc >= 0xffff0000) { + /* We always get here via a jump, so know we are not in a + conditional execution block. */ + gen_exception_internal(EXCP_KERNEL_TRAP); + dc->base.is_jmp = DISAS_EXC; + } +#endif +} + /* generate intermediate code for basic block 'tb'. */ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) { @@ -11939,21 +11959,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) do { dc->base.num_insns++; - dc->insn_start_idx = tcg_op_buf_count(); - tcg_gen_insn_start(dc->pc, - (dc->condexec_cond << 4) | (dc->condexec_mask >> 1), - 0); - -#ifdef CONFIG_USER_ONLY - /* Intercept jump to the magic kernel page. */ - if (dc->pc >= 0xffff0000) { - /* We always get here via a jump, so know we are not in a - conditional execution block. */ - gen_exception_internal(EXCP_KERNEL_TRAP); - dc->base.is_jmp = DISAS_EXC; - break; - } -#endif + arm_tr_insn_start(&dc->base, cs); if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { CPUBreakpoint *bp;