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[ARM] Remove %? string from some Advanced SIMD patterns.

Message ID f60324eb-0c66-124d-9121-4f2f28f6197e@foss.arm.com
State New
Headers show

Commit Message

Ramana Radhakrishnan July 5, 2017, 12:58 p.m. UTC 
Advanced SIMD patterns are not predicable, thus they should not have %? 
in their output templates. Found when auditing the code for something 
else. This has been in my tree for sometime , bootstrapped and 
regression tested on armhf for armv7ve+simd as the architectural base.

Applied to trunk

<DATE>  Ramana Radhakrishnan  <ramana.radhakrishnan@arm.com>

	* config/arm/neon.md (fma<VCVTF:mode>4): Remove %?.
	(fma<VH:mode>4_intrinsic): Likewise.
	(*fmsub<VCVTF:mode>4): Likewise.
	(*fmsub<VH:mode>4_intrinsic): Likewise.

regards
Ramana
commit b510e80f861b97496386fe58e6b6976a94a3afa1
Author: Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
Date:   Mon Jun 26 14:51:30 2017 +0000

    Remove %? from advanced SIMD patterns
    
    * config/arm/neon.md (fma<VCVTF:mode>4): Remove %?
      (fma<VH:mode>4_intrinsic): Likewise.
     (*fmsub<VCVTF:mode>4): Likewise.
     (*fmsub<VH:mode>4_intrinsic): Likewise.
diff mbox

Patch

diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md
index 0ce3fe415e6..33b25ff3c73 100644
--- a/gcc/config/arm/neon.md
+++ b/gcc/config/arm/neon.md
@@ -678,7 +678,7 @@ 
 		 (match_operand:VCVTF 2 "register_operand" "w")
 		 (match_operand:VCVTF 3 "register_operand" "0")))]
   "TARGET_NEON && TARGET_FMA && flag_unsafe_math_optimizations"
-  "vfma%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
+  "vfma.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
   [(set_attr "type" "neon_fp_mla_s<q>")]
 )
 
@@ -688,7 +688,7 @@ 
 		 (match_operand:VCVTF 2 "register_operand" "w")
 		 (match_operand:VCVTF 3 "register_operand" "0")))]
   "TARGET_NEON && TARGET_FMA"
-  "vfma%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
+  "vfma.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
   [(set_attr "type" "neon_fp_mla_s<q>")]
 )
 
@@ -720,7 +720,7 @@ 
 		   (match_operand:VCVTF 2 "register_operand" "w")
 		   (match_operand:VCVTF 3 "register_operand" "0")))]
   "TARGET_NEON && TARGET_FMA && flag_unsafe_math_optimizations"
-  "vfms%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
+  "vfms.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
   [(set_attr "type" "neon_fp_mla_s<q>")]
 )
 
@@ -731,7 +731,7 @@ 
     (match_operand:VCVTF 2 "register_operand" "w")
     (match_operand:VCVTF 3 "register_operand" "0")))]
  "TARGET_NEON && TARGET_FMA"
- "vfms%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
+ "vfms.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
  [(set_attr "type" "neon_fp_mla_s<q>")]
 )
 
@@ -752,7 +752,7 @@ 
 		         "s_register_operand" "w")]
 		NEON_VRINT))]
   "TARGET_NEON && TARGET_FPU_ARMV8"
-  "vrint<nvrint_variant>%?.f32\\t%<V_reg>0, %<V_reg>1"
+  "vrint<nvrint_variant>.f32\\t%<V_reg>0, %<V_reg>1"
   [(set_attr "type" "neon_fp_round_<V_elem_ch><q>")]
 )