Patchwork [5/8] target-arm: Translate with Thumb state from TB flags, not CPUState

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Submitter Peter Maydell
Date Jan. 11, 2011, 10:12 p.m.
Message ID <1294783938-19629-6-git-send-email-peter.maydell@linaro.org>
Download mbox | patch
Permalink /patch/78456/
State New
Headers show

Comments

Peter Maydell - Jan. 11, 2011, 10:12 p.m.
The Thumb/ARM state for the TB being translated should come from
the TB flags, not the CPUState.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target-arm/translate.c |    6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)
Aurelien Jarno - Jan. 12, 2011, 10:21 a.m.
On Tue, Jan 11, 2011 at 10:12:15PM +0000, Peter Maydell wrote:
> The Thumb/ARM state for the TB being translated should come from
> the TB flags, not the CPUState.
> 
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
>  target-arm/translate.c |    6 +++---
>  1 files changed, 3 insertions(+), 3 deletions(-)

Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
 
> diff --git a/target-arm/translate.c b/target-arm/translate.c
> index 624a443..bda5d47 100644
> --- a/target-arm/translate.c
> +++ b/target-arm/translate.c
> @@ -9074,7 +9074,7 @@ static inline void gen_intermediate_code_internal(CPUState *env,
>      dc->pc = pc_start;
>      dc->singlestep_enabled = env->singlestep_enabled;
>      dc->condjmp = 0;
> -    dc->thumb = env->thumb;
> +    dc->thumb = ARM_TBFLAG_THUMB(tb->flags);
>      dc->condexec_mask = (env->condexec_bits & 0xf) << 1;
>      dc->condexec_cond = env->condexec_bits >> 4;
>  #if !defined(CONFIG_USER_ONLY)
> @@ -9161,7 +9161,7 @@ static inline void gen_intermediate_code_internal(CPUState *env,
>          if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
>              gen_io_start();
>  
> -        if (env->thumb) {
> +        if (dc->thumb) {
>              disas_thumb_insn(env, dc);
>              if (dc->condexec_mask) {
>                  dc->condexec_cond = (dc->condexec_cond & 0xe)
> @@ -9275,7 +9275,7 @@ done_generating:
>      if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
>          qemu_log("----------------\n");
>          qemu_log("IN: %s\n", lookup_symbol(pc_start));
> -        log_target_disas(pc_start, dc->pc - pc_start, env->thumb);
> +        log_target_disas(pc_start, dc->pc - pc_start, dc->thumb);
>          qemu_log("\n");
>      }
>  #endif
> -- 
> 1.6.3.3
> 
> 
>

Patch

diff --git a/target-arm/translate.c b/target-arm/translate.c
index 624a443..bda5d47 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -9074,7 +9074,7 @@  static inline void gen_intermediate_code_internal(CPUState *env,
     dc->pc = pc_start;
     dc->singlestep_enabled = env->singlestep_enabled;
     dc->condjmp = 0;
-    dc->thumb = env->thumb;
+    dc->thumb = ARM_TBFLAG_THUMB(tb->flags);
     dc->condexec_mask = (env->condexec_bits & 0xf) << 1;
     dc->condexec_cond = env->condexec_bits >> 4;
 #if !defined(CONFIG_USER_ONLY)
@@ -9161,7 +9161,7 @@  static inline void gen_intermediate_code_internal(CPUState *env,
         if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
             gen_io_start();
 
-        if (env->thumb) {
+        if (dc->thumb) {
             disas_thumb_insn(env, dc);
             if (dc->condexec_mask) {
                 dc->condexec_cond = (dc->condexec_cond & 0xe)
@@ -9275,7 +9275,7 @@  done_generating:
     if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
         qemu_log("----------------\n");
         qemu_log("IN: %s\n", lookup_symbol(pc_start));
-        log_target_disas(pc_start, dc->pc - pc_start, env->thumb);
+        log_target_disas(pc_start, dc->pc - pc_start, dc->thumb);
         qemu_log("\n");
     }
 #endif