Patchwork [7/8] target-arm: Set privileged bit in TB flags correctly for M profile

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Submitter Peter Maydell
Date Jan. 11, 2011, 10:12 p.m.
Message ID <1294783938-19629-8-git-send-email-peter.maydell@linaro.org>
Download mbox | patch
Permalink /patch/78455/
State New
Headers show

Comments

Peter Maydell - Jan. 11, 2011, 10:12 p.m.
M profile ARM cores don't have a CPSR mode field. Set the bit in the
TB flags that indicates non-user mode correctly for these cores.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target-arm/cpu.h |    8 +++++++-
 1 files changed, 7 insertions(+), 1 deletions(-)
Aurelien Jarno - Jan. 12, 2011, 10:22 a.m.
On Tue, Jan 11, 2011 at 10:12:17PM +0000, Peter Maydell wrote:
> M profile ARM cores don't have a CPSR mode field. Set the bit in the
> TB flags that indicates non-user mode correctly for these cores.
> 
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
>  target-arm/cpu.h |    8 +++++++-
>  1 files changed, 7 insertions(+), 1 deletions(-)

Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
 
> diff --git a/target-arm/cpu.h b/target-arm/cpu.h
> index 3adb118..3cd69c4 100644
> --- a/target-arm/cpu.h
> +++ b/target-arm/cpu.h
> @@ -472,13 +472,19 @@ static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
>  static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
>                                          target_ulong *cs_base, int *flags)
>  {
> +    int privmode;
>      *pc = env->regs[15];
>      *cs_base = 0;
>      *flags = (env->thumb << ARM_TBFLAG_THUMB_SHIFT)
>          | (env->vfp.vec_len << ARM_TBFLAG_VECLEN_SHIFT)
>          | (env->vfp.vec_stride << ARM_TBFLAG_VECSTRIDE_SHIFT)
>          | (env->condexec_bits << ARM_TBFLAG_CONDEXEC_SHIFT);
> -    if ((env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
> +    if (arm_feature(env, ARM_FEATURE_M)) {
> +        privmode = !((env->v7m.exception == 0) && (env->v7m.control & 1));
> +    } else {
> +        privmode = (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR;
> +    }
> +    if (privmode) {
>          *flags |= ARM_TBFLAG_PRIV_MASK;
>      }
>      if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) {
> -- 
> 1.6.3.3
> 
> 
>

Patch

diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 3adb118..3cd69c4 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -472,13 +472,19 @@  static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
 static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
                                         target_ulong *cs_base, int *flags)
 {
+    int privmode;
     *pc = env->regs[15];
     *cs_base = 0;
     *flags = (env->thumb << ARM_TBFLAG_THUMB_SHIFT)
         | (env->vfp.vec_len << ARM_TBFLAG_VECLEN_SHIFT)
         | (env->vfp.vec_stride << ARM_TBFLAG_VECSTRIDE_SHIFT)
         | (env->condexec_bits << ARM_TBFLAG_CONDEXEC_SHIFT);
-    if ((env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
+    if (arm_feature(env, ARM_FEATURE_M)) {
+        privmode = !((env->v7m.exception == 0) && (env->v7m.control & 1));
+    } else {
+        privmode = (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR;
+    }
+    if (privmode) {
         *flags |= ARM_TBFLAG_PRIV_MASK;
     }
     if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) {