From patchwork Wed Jul 5 10:38:40 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akshay Adiga X-Patchwork-Id: 784516 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3x2cnJ4R4Fz9s2s for ; Wed, 5 Jul 2017 20:39:32 +1000 (AEST) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3x2cnJ3b5rzDr4w for ; Wed, 5 Jul 2017 20:39:32 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Received: from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3x2cms0jykzDqhn for ; Wed, 5 Jul 2017 20:39:08 +1000 (AEST) Received: from pps.filterd (m0098417.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.20/8.16.0.20) with SMTP id v65AcxoM049390 for ; Wed, 5 Jul 2017 06:39:06 -0400 Received: from e23smtp08.au.ibm.com (e23smtp08.au.ibm.com [202.81.31.141]) by mx0a-001b2d01.pphosted.com with ESMTP id 2bgvxbm07h-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Wed, 05 Jul 2017 06:39:06 -0400 Received: from localhost by e23smtp08.au.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Wed, 5 Jul 2017 20:39:01 +1000 Received: from d23av04.au.ibm.com (d23av04.au.ibm.com [9.190.235.139]) by d23relay07.au.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id v65Ad10h6357344 for ; Wed, 5 Jul 2017 20:39:01 +1000 Received: from d23av04.au.ibm.com (localhost [127.0.0.1]) by d23av04.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id v65AcxUI024207 for ; Wed, 5 Jul 2017 20:38:59 +1000 Received: from aksadiga.in.ibm.com (aksadiga.in.ibm.com [9.124.35.223]) by d23av04.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id v65Aclu6023862; Wed, 5 Jul 2017 20:38:57 +1000 From: Akshay Adiga To: skiboot@lists.ozlabs.org Date: Wed, 5 Jul 2017 16:08:40 +0530 X-Mailer: git-send-email 2.5.5 In-Reply-To: <1499251121-19678-1-git-send-email-akshay.adiga@linux.vnet.ibm.com> References: <1499251121-19678-1-git-send-email-akshay.adiga@linux.vnet.ibm.com> X-TM-AS-MML: disable x-cbid: 17070510-0048-0000-0000-000002507CEC X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 17070510-0049-0000-0000-00004801AE38 Message-Id: <1499251121-19678-6-git-send-email-akshay.adiga@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-07-05_07:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=1 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1703280000 definitions=main-1707050178 Subject: [Skiboot] [PATCHv2 5/6] SLW: Allow deep states if homer address is known X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ego@linux.vnet.ibm.com, shriyak@linux.vnet.ibm.com MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Use a common variable has_wakeup_engine instead of has_slw to tell if the a) SLW image is populated in case of power8 b) CME image is populated in case of power9 Currently we expect CME to be loaded if homer address is known ( except for simulators) Signed-off-by: Akshay Adiga --- hw/slw.c | 23 +++++++++++++++++------ 1 file changed, 17 insertions(+), 6 deletions(-) diff --git a/hw/slw.c b/hw/slw.c index c943d80..288295a 100644 --- a/hw/slw.c +++ b/hw/slw.c @@ -707,7 +707,7 @@ void add_cpu_idle_state_properties(void) int nr_states; bool can_sleep = true; - bool has_slw = true; + bool has_wakeup_engine = true; bool has_stop_inst = false; u8 i; @@ -797,9 +797,20 @@ void add_cpu_idle_state_properties(void) nr_states = ARRAY_SIZE(power7_cpu_idle_states); } - /* Enable deep idle states only if slw image is intact */ - has_slw = (chip->slw_base && chip->slw_bar_size && - chip->slw_image_size); + /* + * Enable deep idle states only if : + * P8 : slw image is intact + * P9 : homer_base is set + */ + if (!(proc_chip_quirks & QUIRK_MAMBO_CALLOUTS)) { + if (proc_gen == proc_gen_p9) + has_wakeup_engine = !!(chip->homer_base); + else /* (proc_gen == proc_gen_p8) */ + has_wakeup_engine = (chip->slw_base && chip->slw_bar_size && + chip->slw_image_size); + } else { + has_wakeup_engine = false; + } /* * Currently we can't append strings and cells to dt properties. @@ -827,7 +838,7 @@ void add_cpu_idle_state_properties(void) if (has_stop_inst) { /* Power 9 / POWER ISA 3.0 */ supported_states_mask = OPAL_PM_STOP_INST_FAST; - if (has_slw) + if (has_wakeup_engine) supported_states_mask |= OPAL_PM_STOP_INST_DEEP; } else { /* Power 7 and Power 8 */ @@ -835,7 +846,7 @@ void add_cpu_idle_state_properties(void) if (can_sleep) supported_states_mask |= OPAL_PM_SLEEP_ENABLED | OPAL_PM_SLEEP_ENABLED_ER1; - if (has_slw) + if (has_wakeup_engine) supported_states_mask |= OPAL_PM_WINKLE_ENABLED; } for (i = 0; i < nr_states; i++) {