[PATCHv2,3/6] SLW: Add opal_slw_set_reg support for power9

Message ID 1499251121-19678-4-git-send-email-akshay.adiga@linux.vnet.ibm.com
State Superseded
Headers show

Commit Message

Akshay Adiga July 5, 2017, 10:38 a.m.
This OPAL call is made from Linux to OPAL to configure values in
various SPRs after wakeup from a deep idle state.

Signed-off-by: Akshay Adiga <akshay.adiga@linux.vnet.ibm.com>
---
 hw/slw.c | 52 ++++++++++++++++++++++++++++++++++------------------
 1 file changed, 34 insertions(+), 18 deletions(-)

Comments

Gautham R Shenoy July 5, 2017, 4:54 p.m. | #1
On Wed, Jul 05, 2017 at 04:08:38PM +0530, Akshay Adiga wrote:
> This OPAL call is made from Linux to OPAL to configure values in
> various SPRs after wakeup from a deep idle state.
> 
> Signed-off-by: Akshay Adiga <akshay.adiga@linux.vnet.ibm.com>

Tested-by: Gautham R. Shenoy <ego@linux.vnet.ibm.com>

Patch

diff --git a/hw/slw.c b/hw/slw.c
index c0ab9de..4600279 100644
--- a/hw/slw.c
+++ b/hw/slw.c
@@ -30,6 +30,7 @@ 
 #include <libfdt/libfdt.h>
 #include <opal-api.h>
 
+#include <p9_stop_api.H>
 #include <p8_pore_table_gen_api.H>
 #include <sbe_xip_image.h>
 
@@ -1301,33 +1302,48 @@  int64_t opal_slw_set_reg(uint64_t cpu_pir, uint64_t sprn, uint64_t val)
 	assert(c);
 	chip = get_chip(c->chip_id);
 	assert(chip);
-	image = (void *) chip->slw_base;
 
-	/* Check of the SPR is supported by libpore */
-	for ( i=0; i < SLW_SPR_REGS_SIZE ; i++)  {
-		if (sprn == SLW_SPR_REGS[i].value)  {
-			spr_is_supported = 1;
-			break;
+	if (chip->type == PROC_CHIP_P9_NIMBUS ||
+	    chip->type == PROC_CHIP_P9_CUMULUS) {
+		if (!chip->homer_base) {
+			log_simple_error(&e_info(OPAL_RC_SLW_REG),
+					 "SLW: HOMER base not set %x\n",
+					 chip->id);
+			return OPAL_INTERNAL_ERROR;
 		}
-	}
-	if (!spr_is_supported) {
-		log_simple_error(&e_info(OPAL_RC_SLW_REG),
+		rc = p9_stop_save_cpureg((void *)chip->homer_base,
+					 sprn, val, cpu_pir);
+
+	} else { /* Assuming its P8 */
+
+		/* Check of the SPR is supported by libpore */
+		for (i = 0; i < SLW_SPR_REGS_SIZE ; i++)  {
+			if (sprn == SLW_SPR_REGS[i].value)  {
+				spr_is_supported = 1;
+				break;
+			}
+		}
+		if (!spr_is_supported) {
+			log_simple_error(&e_info(OPAL_RC_SLW_REG),
 			"SLW: Trying to set unsupported spr for CPU %x\n",
-			c->pir);
-		return OPAL_UNSUPPORTED;
+				c->pir);
+			return OPAL_UNSUPPORTED;
+		}
+		image = (void *)chip->slw_base;
+		rc = p8_pore_gen_cpureg_fixed(image, P8_SLW_MODEBUILD_SRAM,
+					      sprn, val,
+					      cpu_get_core_index(c),
+					      cpu_get_thread_index(c));
 	}
 
-	rc = p8_pore_gen_cpureg_fixed(image, P8_SLW_MODEBUILD_SRAM, sprn,
-						val, cpu_get_core_index(c),
-						cpu_get_thread_index(c));
-
 	if (rc) {
 		log_simple_error(&e_info(OPAL_RC_SLW_REG),
-			"SLW: Failed to set spr for CPU %x\n",
-			c->pir);
+			"SLW: Failed to set spr %llx for CPU %x, RC=0x%x\n",
+			sprn, c->pir, rc);
 		return OPAL_INTERNAL_ERROR;
 	}
-
+	prlog(PR_DEBUG, "SLW: restore spr:0x%llx on c:0x%x with 0x%llx\n",
+	      sprn, c->pir, val);
 	return OPAL_SUCCESS;
 
 }