From patchwork Wed Jul 5 10:38:39 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akshay Adiga X-Patchwork-Id: 784514 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3x2cn55VQzz9s2s for ; Wed, 5 Jul 2017 20:39:21 +1000 (AEST) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3x2cn54pn4zDr3b for ; Wed, 5 Jul 2017 20:39:21 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Received: from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3x2cmq3rNtzDqhn for ; Wed, 5 Jul 2017 20:39:07 +1000 (AEST) Received: from pps.filterd (m0098414.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.20/8.16.0.20) with SMTP id v65Ad2Pm036012 for ; Wed, 5 Jul 2017 06:39:04 -0400 Received: from e23smtp06.au.ibm.com (e23smtp06.au.ibm.com [202.81.31.148]) by mx0b-001b2d01.pphosted.com with ESMTP id 2bgvqjcv7p-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Wed, 05 Jul 2017 06:39:04 -0400 Received: from localhost by e23smtp06.au.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Wed, 5 Jul 2017 20:38:59 +1000 Received: from d23av04.au.ibm.com (d23av04.au.ibm.com [9.190.235.139]) by d23relay06.au.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id v65Acxrt5833092 for ; Wed, 5 Jul 2017 20:38:59 +1000 Received: from d23av04.au.ibm.com (localhost [127.0.0.1]) by d23av04.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id v65AcvtP024149 for ; Wed, 5 Jul 2017 20:38:57 +1000 Received: from aksadiga.in.ibm.com (aksadiga.in.ibm.com [9.124.35.223]) by d23av04.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id v65Aclu5023862; Wed, 5 Jul 2017 20:38:56 +1000 From: Akshay Adiga To: skiboot@lists.ozlabs.org Date: Wed, 5 Jul 2017 16:08:39 +0530 X-Mailer: git-send-email 2.5.5 In-Reply-To: <1499251121-19678-1-git-send-email-akshay.adiga@linux.vnet.ibm.com> References: <1499251121-19678-1-git-send-email-akshay.adiga@linux.vnet.ibm.com> X-TM-AS-MML: disable x-cbid: 17070510-0040-0000-0000-0000033E7145 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 17070510-0041-0000-0000-00000CB99C02 Message-Id: <1499251121-19678-5-git-send-email-akshay.adiga@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-07-05_07:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=1 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1703280000 definitions=main-1707050178 Subject: [Skiboot] [PATCHv2 4/6] SLW: Configure self-restore for HRMOR X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ego@linux.vnet.ibm.com, shriyak@linux.vnet.ibm.com MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Make a stop api call using libpore to restore HRMOR register. HRMOR needs to be cleared so that when thread exits stop, they arrives at linux system_reset vector (0x100). Signed-off-by: Akshay Adiga Tested-by: Gautham R. Shenoy --- hw/slw.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/hw/slw.c b/hw/slw.c index 4600279..c943d80 100644 --- a/hw/slw.c +++ b/hw/slw.c @@ -1145,12 +1145,41 @@ static void slw_patch_regs(struct proc_chip *chip) static void slw_init_chip_p9(struct proc_chip *chip) { struct cpu_thread *c; + int rc; prlog(PR_DEBUG, "SLW: Init chip 0x%x\n", chip->id); /* At power ON setup inits for power-mgt */ for_each_available_core_in_chip(c, chip->id) slw_set_overrides_p9(chip, c); + + if (!chip->homer_base) { + log_simple_error(&e_info(OPAL_RC_SLW_REG), + "SLW: HOMER base not set %x\n", + chip->id); + return; + } + + prlog(PR_NOTICE, "SLW: Configuring self-restore for HRMOR\n"); + + /* Should this be for_each_present_cpu() ? */ + for_each_available_cpu(c) { + if (c->chip_id != chip->id) + continue; + + /* + * Clear HRMOR. Need to update only for thread + * 0 of each core. Doing it anyway for all threads + */ + rc = p9_stop_save_cpureg((void *)chip->homer_base, + P9_STOP_SPR_HRMOR, 0, + c->pir); + if (rc) { + log_simple_error(&e_info(OPAL_RC_SLW_REG), + "SLW: Failed to set HRMOR for CPU %x,RC=0x%x\n", + c->pir, rc); + } + } } static void slw_init_chip(struct proc_chip *chip) {