Patchwork [U-Boot,v3,7/8] powerpc/86xx: Convert SBC8641 to use common SRIO init code

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Submitter Kumar Gala
Date Jan. 11, 2011, 8:10 a.m.
Message ID <1294733436-10264-7-git-send-email-galak@kernel.crashing.org>
Download mbox | patch
Permalink /patch/78291/
State Accepted
Commit 7cee1dfdf6d686a48cd9309ea0e55e2a4b3d2fc4
Delegated to: Kumar Gala
Headers show

Comments

Kumar Gala - Jan. 11, 2011, 8:10 a.m.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Tested-by: Paul Gortmaker <paul.gortmaker@windriver.com>
---
* Renamed CONFIG_SYS_HAS_SRIO -> CONFIG_SYS_SRIO

 board/sbc8641d/law.c       |    1 -
 include/configs/sbc8641d.h |   15 +++++++++------
 2 files changed, 9 insertions(+), 7 deletions(-)
Kumar Gala - Jan. 11, 2011, 2:14 p.m.
On Jan 11, 2011, at 2:10 AM, Kumar Gala wrote:

> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
> Tested-by: Paul Gortmaker <paul.gortmaker@windriver.com>
> ---
> * Renamed CONFIG_SYS_HAS_SRIO -> CONFIG_SYS_SRIO
> 
> board/sbc8641d/law.c       |    1 -
> include/configs/sbc8641d.h |   15 +++++++++------
> 2 files changed, 9 insertions(+), 7 deletions(-)

applied to 85xx

- k

Patch

diff --git a/board/sbc8641d/law.c b/board/sbc8641d/law.c
index a6f60ee..14259d6 100644
--- a/board/sbc8641d/law.c
+++ b/board/sbc8641d/law.c
@@ -51,7 +51,6 @@  struct law_entry law_table[] = {
 #endif
 	SET_LAW(0xf8000000, LAW_SIZE_2M, LAW_TRGT_IF_LBC),
 	SET_LAW(0xfe000000, LAW_SIZE_32M, LAW_TRGT_IF_LBC),
-	SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO)
 };
 
 int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h
index 90d84eb..8d9f931 100644
--- a/include/configs/sbc8641d.h
+++ b/include/configs/sbc8641d.h
@@ -57,6 +57,9 @@ 
  */
 #define CONFIG_SYS_SCRATCH_VA	0xe8000000
 
+#define CONFIG_SYS_SRIO
+#define CONFIG_SRIO1			/* SRIO port 1 */
+
 #define CONFIG_PCI		1	/* Enable PCIE */
 #define CONFIG_PCIE1		1	/* PCIE controler 1 (slot 1) */
 #define CONFIG_PCIE2		1	/* PCIE controler 2 (slot 2) */
@@ -297,9 +300,9 @@ 
 /*
  * RapidIO MMU
  */
-#define CONFIG_SYS_RIO_MEM_BASE	0xc0000000	/* base address */
-#define CONFIG_SYS_RIO_MEM_PHYS	CONFIG_SYS_RIO_MEM_BASE
-#define CONFIG_SYS_RIO_MEM_SIZE	0x20000000	/* 128M */
+#define CONFIG_SYS_SRIO1_MEM_BASE	0xc0000000	/* base address */
+#define CONFIG_SYS_SRIO1_MEM_PHYS	CONFIG_SYS_SRIO1_MEM_BASE
+#define CONFIG_SYS_SRIO1_MEM_SIZE	0x20000000	/* 128M */
 
 /*
  * General PCI
@@ -417,10 +420,10 @@ 
  * BAT2         512M   Cache-inhibited, guarded
  * 0xc000_0000  512M   RapidIO Memory
  */
-#define CONFIG_SYS_DBAT2L	(CONFIG_SYS_RIO_MEM_BASE | BATL_PP_RW \
+#define CONFIG_SYS_DBAT2L	(CONFIG_SYS_SRIO1_MEM_BASE | BATL_PP_RW \
 			| BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT2U	(CONFIG_SYS_RIO_MEM_BASE | BATU_BL_512M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_RIO_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_DBAT2U	(CONFIG_SYS_SRIO1_MEM_BASE | BATU_BL_512M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_SRIO1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
 #define CONFIG_SYS_IBAT2U	CONFIG_SYS_DBAT2U
 
 /*