From patchwork Fri Jun 30 13:56:33 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Preetham Chandru Ramchandra X-Patchwork-Id: 782873 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3wzdQh5nKVz9ryQ for ; Fri, 30 Jun 2017 23:58:04 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751935AbdF3N6E (ORCPT ); Fri, 30 Jun 2017 09:58:04 -0400 Received: from nat-hk.nvidia.com ([203.18.50.4]:20558 "EHLO nat-hk.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751649AbdF3N6D (ORCPT ); Fri, 30 Jun 2017 09:58:03 -0400 Received: from hkpgpgate101.nvidia.com (Not Verified[10.18.92.9]) by nat-hk.nvidia.com id ; Fri, 30 Jun 2017 21:58:03 +0800 Received: from HKMAIL103.nvidia.com ([10.18.16.12]) by hkpgpgate101.nvidia.com (PGP Universal service); Fri, 30 Jun 2017 06:58:01 -0700 X-PGP-Universal: processed; by hkpgpgate101.nvidia.com on Fri, 30 Jun 2017 06:58:01 -0700 Received: from DRBGMAIL103.nvidia.com (10.18.16.22) by HKMAIL103.nvidia.com (10.18.16.12) with Microsoft SMTP Server (TLS) id 15.0.1263.5; Fri, 30 Jun 2017 13:58:00 +0000 Received: from HQMAIL104.nvidia.com (172.18.146.11) by DRBGMAIL103.nvidia.com (10.18.16.22) with Microsoft SMTP Server (TLS) id 15.0.1263.5; Fri, 30 Jun 2017 13:57:59 +0000 Received: from pchandru-ubuntu.nvidia.com (172.20.13.39) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1263.5 via Frontend Transport; Fri, 30 Jun 2017 13:57:56 +0000 From: Preetham Chandru Ramchandra To: , , CC: , , , , , Preetham Chandru R Subject: [PATCH V5 3/3] dt-bindings: tegra: add binding documentation Date: Fri, 30 Jun 2017 19:26:33 +0530 Message-ID: <1498830993-24666-4-git-send-email-pchandru@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1498830993-24666-1-git-send-email-pchandru@nvidia.com> References: <1498830993-24666-1-git-send-email-pchandru@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Preetham Chandru R This adds bindings documentation for the AHCI controller on Tegra210 Signed-off-by: Preetham Chandru R --- v4: * changed the commit message * changed 'sata-cold' reset to mandatory for t210 and t124 * Removed the regulators for T210 since these regulators will be enabled in phy driver. v3: * Add AUX register. v2: * change cml1, pll_e and phy regulators as optional for T210. --- .../bindings/ata/nvidia,tegra124-ahci.txt | 38 ++++++++++++++-------- 1 file changed, 25 insertions(+), 13 deletions(-) diff --git a/Documentation/devicetree/bindings/ata/nvidia,tegra124-ahci.txt b/Documentation/devicetree/bindings/ata/nvidia,tegra124-ahci.txt index 66c83c3..df4dc2c 100644 --- a/Documentation/devicetree/bindings/ata/nvidia,tegra124-ahci.txt +++ b/Documentation/devicetree/bindings/ata/nvidia,tegra124-ahci.txt @@ -1,20 +1,19 @@ -Tegra124 SoC SATA AHCI controller +Tegra SoC SATA AHCI controller Required properties : -- compatible : For Tegra124, must contain "nvidia,tegra124-ahci". Otherwise, - must contain '"nvidia,-ahci", "nvidia,tegra124-ahci"', where - is tegra132. -- reg : Should contain 2 entries: +- compatible : Must be one of: + - Tegra124 : "nvidia,tegra124-ahci" + - Tegra210 : "nvidia,tegra210-ahci" +- reg : Should contain 3 entries: - AHCI register set (SATA BAR5) - SATA register set + - Tegra210 : AUX register set - interrupts : Defines the interrupt used by SATA - clocks : Must contain an entry for each entry in clock-names. See ../clocks/clock-bindings.txt for details. - clock-names : Must include the following entries: - sata - sata-oob - - cml1 - - pll_e - resets : Must contain an entry for each entry in reset-names. See ../reset/reset.txt for details. - reset-names : Must include the following entries: @@ -24,9 +23,22 @@ Required properties : - phys : Must contain an entry for each entry in phy-names. See ../phy/phy-bindings.txt for details. - phy-names : Must include the following entries: - - sata-phy : XUSB PADCTL SATA PHY -- hvdd-supply : Defines the SATA HVDD regulator -- vddio-supply : Defines the SATA VDDIO regulator -- avdd-supply : Defines the SATA AVDD regulator -- target-5v-supply : Defines the SATA 5V power regulator -- target-12v-supply : Defines the SATA 12V power regulator + - For T124: + - sata-phy : XUSB PADCTL SATA PHY + - For T210: + - sata-0 +- For T124: + - hvdd-supply : Defines the SATA HVDD regulator + - vddio-supply : Defines the SATA VDDIO regulator + - avdd-supply : Defines the SATA AVDD regulator + - target-5v-supply : Defines the SATA 5V power regulator + - target-12v-supply : Defines the SATA 12V power regulator + +Optional properties: +- clock-names : + - cml1 : + cml1 clock is required by phy so it is optional to define + here as phy driver will be enabling this clock. + - pll_e : + pll_e is the parent of cml1 clock so it is optional to define + here as phy driver will be enabling this clock.