Patchwork [2/7] tcg-ppc: Implement deposit operation.

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Submitter Richard Henderson
Date Jan. 11, 2011, 3:23 a.m.
Message ID <1294716228-9299-3-git-send-email-rth@twiddle.net>
Download mbox | patch
Permalink /patch/78269/
State New
Headers show

Comments

Richard Henderson - Jan. 11, 2011, 3:23 a.m.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 tcg/ppc/tcg-target.c |   17 ++++++++++++++++-
 tcg/ppc/tcg-target.h |    1 +
 2 files changed, 17 insertions(+), 1 deletions(-)
malc - Jan. 11, 2011, 12:40 p.m.
On Mon, 10 Jan 2011, Richard Henderson wrote:

> Signed-off-by: Richard Henderson <rth@twiddle.net>
> ---
>  tcg/ppc/tcg-target.c |   17 ++++++++++++++++-
>  tcg/ppc/tcg-target.h |    1 +
>  2 files changed, 17 insertions(+), 1 deletions(-)
> 
> diff --git a/tcg/ppc/tcg-target.c b/tcg/ppc/tcg-target.c
> index 7970268..39aa4f1 100644
> --- a/tcg/ppc/tcg-target.c
> +++ b/tcg/ppc/tcg-target.c
> @@ -1611,6 +1611,21 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
>          }
>          break;
>  
> +    case INDEX_op_deposit_i32:
> +        {
> +            unsigned len = args[4];
> +            unsigned lsb_ofs = args[3];
> +            unsigned msb_ofs = 31 - lsb_ofs;
> +
> +            tcg_out32 (s, RLWIMI
> +                       | RA(args[0])
> +                       | RS(args[2])
> +                       | SH(lsb_ofs)
> +                       | MB(msb_ofs - len + 1)
> +                       | ME(msb_ofs));
> +        }
> +        break;
> +
>      case INDEX_op_add2_i32:
>          if (args[0] == args[3] || args[0] == args[5]) {
>              tcg_out32 (s, ADDC | TAB (0, args[2], args[4]));
> @@ -1829,9 +1844,9 @@ static const TCGTargetOpDef ppc_op_defs[] = {
>      { INDEX_op_shl_i32, { "r", "r", "ri" } },
>      { INDEX_op_shr_i32, { "r", "r", "ri" } },
>      { INDEX_op_sar_i32, { "r", "r", "ri" } },
> -
>      { INDEX_op_rotl_i32, { "r", "r", "ri" } },
>      { INDEX_op_rotr_i32, { "r", "r", "ri" } },
> +    { INDEX_op_deposit_i32, { "r", "0", "r" } },
>  

Are you sure about "0" constraint?

>      { INDEX_op_brcond_i32, { "r", "ri" } },
>  
> diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
> index a1f8599..bbf38d5 100644
> --- a/tcg/ppc/tcg-target.h
> +++ b/tcg/ppc/tcg-target.h
> @@ -92,6 +92,7 @@ enum {
>  #define TCG_TARGET_HAS_eqv_i32
>  #define TCG_TARGET_HAS_nand_i32
>  #define TCG_TARGET_HAS_nor_i32
> +#define TCG_TARGET_HAS_deposit_i32
>  
>  #define TCG_AREG0 TCG_REG_R27
>  
>
Richard Henderson - Jan. 11, 2011, 4:32 p.m.
On 01/11/2011 04:40 AM, malc wrote:
>> +            tcg_out32 (s, RLWIMI
>> +                       | RA(args[0])
>> +                       | RS(args[2])
>> +                       | SH(lsb_ofs)
>> +                       | MB(msb_ofs - len + 1)
>> +                       | ME(msb_ofs));
>> +        }
...
>> +    { INDEX_op_deposit_i32, { "r", "0", "r" } },
>>  
> 
> Are you sure about "0" constraint?

Yes, rlwimi inserts a value into the destination register.
There is no second source register for the instruction.


r~
malc - Jan. 11, 2011, 7:11 p.m.
On Tue, 11 Jan 2011, Richard Henderson wrote:

> On 01/11/2011 04:40 AM, malc wrote:
> >> +            tcg_out32 (s, RLWIMI
> >> +                       | RA(args[0])
> >> +                       | RS(args[2])
> >> +                       | SH(lsb_ofs)
> >> +                       | MB(msb_ofs - len + 1)
> >> +                       | ME(msb_ofs));
> >> +        }
> ...
> >> +    { INDEX_op_deposit_i32, { "r", "0", "r" } },
> >>  
> > 
> > Are you sure about "0" constraint?
> 
> Yes, rlwimi inserts a value into the destination register.
> There is no second source register for the instruction.
> 

Indeed, nothing else uses "0" in tcg/ppc so it caught my attention.

Patch

diff --git a/tcg/ppc/tcg-target.c b/tcg/ppc/tcg-target.c
index 7970268..39aa4f1 100644
--- a/tcg/ppc/tcg-target.c
+++ b/tcg/ppc/tcg-target.c
@@ -1611,6 +1611,21 @@  static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
         }
         break;
 
+    case INDEX_op_deposit_i32:
+        {
+            unsigned len = args[4];
+            unsigned lsb_ofs = args[3];
+            unsigned msb_ofs = 31 - lsb_ofs;
+
+            tcg_out32 (s, RLWIMI
+                       | RA(args[0])
+                       | RS(args[2])
+                       | SH(lsb_ofs)
+                       | MB(msb_ofs - len + 1)
+                       | ME(msb_ofs));
+        }
+        break;
+
     case INDEX_op_add2_i32:
         if (args[0] == args[3] || args[0] == args[5]) {
             tcg_out32 (s, ADDC | TAB (0, args[2], args[4]));
@@ -1829,9 +1844,9 @@  static const TCGTargetOpDef ppc_op_defs[] = {
     { INDEX_op_shl_i32, { "r", "r", "ri" } },
     { INDEX_op_shr_i32, { "r", "r", "ri" } },
     { INDEX_op_sar_i32, { "r", "r", "ri" } },
-
     { INDEX_op_rotl_i32, { "r", "r", "ri" } },
     { INDEX_op_rotr_i32, { "r", "r", "ri" } },
+    { INDEX_op_deposit_i32, { "r", "0", "r" } },
 
     { INDEX_op_brcond_i32, { "r", "ri" } },
 
diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
index a1f8599..bbf38d5 100644
--- a/tcg/ppc/tcg-target.h
+++ b/tcg/ppc/tcg-target.h
@@ -92,6 +92,7 @@  enum {
 #define TCG_TARGET_HAS_eqv_i32
 #define TCG_TARGET_HAS_nand_i32
 #define TCG_TARGET_HAS_nor_i32
+#define TCG_TARGET_HAS_deposit_i32
 
 #define TCG_AREG0 TCG_REG_R27