@@ -114,5 +114,5 @@
*/
(define_insn_reservation "niag_vis" 8
(and (eq_attr "cpu" "niagara")
- (eq_attr "type" "fga,visl,vismv,fgm_pack,fgm_mul,pdist,edge,edgen,gsr,array,bmask"))
+ (eq_attr "type" "fga,visl,viscmp,vismv,fgm_pack,fgm_mul,pdist,edge,edgen,gsr,array,bmask"))
"niag_pipe*8")
@@ -111,10 +111,10 @@
(define_insn_reservation "niag2_vis" 6
(and (eq_attr "cpu" "niagara2")
- (eq_attr "type" "fga,vismv,visl,fgm_pack,fgm_mul,pdist,edge,edgen,array,bmask,gsr"))
+ (eq_attr "type" "fga,vismv,visl,viscmp,fgm_pack,fgm_mul,pdist,edge,edgen,array,bmask,gsr"))
"niag2_pipe*6")
(define_insn_reservation "niag3_vis" 9
(and (eq_attr "cpu" "niagara3")
- (eq_attr "type" "fga,vismv,visl,fgm_pack,fgm_mul,pdist,pdistn,edge,edgen,array,bmask,gsr"))
+ (eq_attr "type" "fga,vismv,visl,viscmp,fgm_pack,fgm_mul,pdist,pdistn,edge,edgen,array,bmask,gsr"))
"niag2_pipe*9")
@@ -90,8 +90,9 @@
(define_insn_reservation "n4_vis_logical" 3
(and (eq_attr "cpu" "niagara4")
- (and (eq_attr "type" "visl,pdistn")
- (eq_attr "fptype" "double")))
+ (ior (and (eq_attr "type" "visl,pdistn")
+ (eq_attr "fptype" "double"))
+ (eq_attr "type" "viscmp")))
"n4_slot1, nothing*2")
(define_insn_reservation "n4_vis_logical_11cycle" 11
@@ -123,13 +123,13 @@
(define_insn_reservation "n7_vis_logical_v3pipe" 11
(and (eq_attr "cpu" "niagara7")
- (and (eq_attr "type" "visl,pdistn")
+ (and (eq_attr "type" "visl,viscmp,pdistn")
(eq_attr "v3pipe" "true")))
"n7_slot1, nothing*2")
(define_insn_reservation "n7_vis_logical_11cycle" 11
(and (eq_attr "cpu" "niagara7")
- (and (eq_attr "type" "visl")
+ (and (eq_attr "type" "visl,viscmp")
(eq_attr "v3pipe" "false")))
"n7_slot1, nothing*10")
@@ -281,7 +281,8 @@
fpcmp,
fpmul,fpdivs,fpdivd,
fpsqrts,fpsqrtd,
- fga,visl,vismv,fgm_pack,fgm_mul,pdist,pdistn,edge,edgen,gsr,array,bmask,
+ fga,visl,vismv,viscmp,
+ fgm_pack,fgm_mul,pdist,pdistn,edge,edgen,gsr,array,bmask,
cmove,
ialuX,
multi,savew,flushw,iflush,trap,lzd"
@@ -9059,8 +9060,7 @@
UNSPEC_FCMP))]
"TARGET_VIS"
"fcmp<gcond:code><GCM:gcm_name>\t%1, %2, %0"
- [(set_attr "type" "visl")
- (set_attr "fptype" "double")
+ [(set_attr "type" "viscmp")
(set_attr "v3pipe" "true")])
(define_insn "fpcmp<gcond:code>8<P:mode>_vis"
@@ -9070,8 +9070,7 @@
UNSPEC_FCMP))]
"TARGET_VIS4"
"fpcmp<gcond:code>8\t%1, %2, %0"
- [(set_attr "type" "visl")
- (set_attr "fptype" "double")])
+ [(set_attr "type" "viscmp")])
(define_expand "vcond<GCM:mode><GCM:mode>"
[(match_operand:GCM 0 "register_operand" "")
@@ -9427,8 +9426,7 @@
UNSPEC_FUCMP))]
"TARGET_VIS3"
"fucmp<gcond:code>8\t%1, %2, %0"
- [(set_attr "type" "visl")
- (set_attr "v3pipe" "true")])
+ [(set_attr "type" "viscmp")])
(define_insn "fpcmpu<gcond:code><GCM:gcm_name><P:mode>_vis"
[(set (match_operand:P 0 "register_operand" "=r")
@@ -9437,8 +9435,7 @@
UNSPEC_FUCMP))]
"TARGET_VIS4"
"fpcmpu<gcond:code><GCM:gcm_name>\t%1, %2, %0"
- [(set_attr "type" "visl")
- (set_attr "fptype" "double")])
+ [(set_attr "type" "viscmp")])
(define_insn "*naddsf3"
[(set (match_operand:SF 0 "register_operand" "=f")
@@ -263,10 +263,10 @@
(define_insn_reservation "us1_fga_double"
2
- (and (and
- (eq_attr "cpu" "ultrasparc")
- (eq_attr "type" "fga,visl,vismv"))
- (eq_attr "fptype" "double"))
+ (and (eq_attr "cpu" "ultrasparc")
+ (ior (and (eq_attr "type" "fga,visl,vismv")
+ (eq_attr "fptype" "double"))
+ (eq_attr "type" "viscmp")))
"us1_fpa + us1_fp_double + us1_slotany, nothing")
(define_bypass 1 "us1_fga_double" "us1_fga_double")
@@ -176,7 +176,7 @@
(define_insn_reservation "us3_fga"
3
(and (eq_attr "cpu" "ultrasparc3")
- (eq_attr "type" "fga,visl,vismv"))
+ (eq_attr "type" "fga,visl,viscmp,vismv"))
"us3_fpa + us3_slotany, nothing*2")
(define_insn_reservation "us3_fgm"