From patchwork Mon Jan 10 20:31:37 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 78205 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id C84B9B6EDF for ; Tue, 11 Jan 2011 07:33:58 +1100 (EST) Received: (qmail 19572 invoked by alias); 10 Jan 2011 20:32:36 -0000 Received: (qmail 19436 invoked by uid 22791); 10 Jan 2011 20:32:30 -0000 X-SWARE-Spam-Status: No, hits=-1.8 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_NONE X-Spam-Check-By: sourceware.org Received: from a.mail.sonic.net (HELO a.mail.sonic.net) (64.142.16.245) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Mon, 10 Jan 2011 20:32:22 +0000 Received: from are.twiddle.net (are.twiddle.net [75.101.38.216]) by a.mail.sonic.net (8.13.8.Beta0-Sonic/8.13.7) with ESMTP id p0AKWJoa015049 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Mon, 10 Jan 2011 12:32:20 -0800 Received: from anchor.twiddle.home (anchor.twiddle.home [172.31.0.4]) by are.twiddle.net (8.14.4/8.14.4) with ESMTP id p0AKWJoX006763; Mon, 10 Jan 2011 12:32:19 -0800 Received: from anchor.twiddle.home (localhost.localdomain [127.0.0.1]) by anchor.twiddle.home (8.14.4/8.14.4) with ESMTP id p0AKWHlJ019680; Mon, 10 Jan 2011 12:32:17 -0800 Received: (from rth@localhost) by anchor.twiddle.home (8.14.4/8.14.4/Submit) id p0AKWGuD019679; Mon, 10 Jan 2011 12:32:16 -0800 From: Richard Henderson To: gcc-patches@gcc.gnu.org Cc: nickc@redhat.com, law@redhat.com, Richard Henderson Subject: [PATCH 08/28] mn10300: Define the A and D constraints. Date: Mon, 10 Jan 2011 12:31:37 -0800 Message-Id: <1294691517-19580-9-git-send-email-rth@redhat.com> In-Reply-To: <1294691517-19580-1-git-send-email-rth@redhat.com> References: <1294691517-19580-1-git-send-email-rth@redhat.com> X-IsSubscribed: yes Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org From: Richard Henderson This will allow combining am33 and mn103 alternatives without having to resort to the enabled attribute. The existing 'A' constraint renamed to 'c'. Thankfully this existing accumulator constraint doesn't appear in either newlib or eglibc sources. --- gcc/config/mn10300/constraints.md | 11 ++++++++++- gcc/config/mn10300/mn10300.md | 8 ++++---- 2 files changed, 14 insertions(+), 5 deletions(-) diff --git a/gcc/config/mn10300/constraints.md b/gcc/config/mn10300/constraints.md index 509970c..c9863fc 100644 --- a/gcc/config/mn10300/constraints.md +++ b/gcc/config/mn10300/constraints.md @@ -23,6 +23,15 @@ (define_register_constraint "a" "ADDRESS_REGS" "An address register.") +;; This can be used for QI/HImode memory operations, and most arithmetic. +;; AM33 supports these on all registers, where MN103 needs DATA_REGS. +(define_register_constraint "D" "TARGET_AM33 ? GENERAL_REGS : DATA_REGS" + "A general register for AM33, and a data register otherwise.") + +;; Similarly for ADDRESS_REGS vs GENERAL_REGS. +(define_register_constraint "A" "TARGET_AM33 ? GENERAL_REGS : ADDRESS_REGS" + "A general register for AM33, and an address register otherwise.") + (define_register_constraint "y" "SP_REGS" "An SP register (if available).") @@ -32,7 +41,7 @@ (define_register_constraint "f" "TARGET_AM33_2 ? FP_REGS : NO_REGS" "A floating point register.") -(define_register_constraint "A" "TARGET_AM33_2 ? FP_ACC_REGS : NO_REGS" +(define_register_constraint "c" "TARGET_AM33_2 ? FP_ACC_REGS : NO_REGS" "A floating point accumulator register.") (define_memory_constraint "Q" diff --git a/gcc/config/mn10300/mn10300.md b/gcc/config/mn10300/mn10300.md index bfa453f..1773a03 100644 --- a/gcc/config/mn10300/mn10300.md +++ b/gcc/config/mn10300/mn10300.md @@ -2717,7 +2717,7 @@ ) (define_insn "fmasf4" - [(set (match_operand:SF 0 "register_operand" "=A") + [(set (match_operand:SF 0 "register_operand" "=c") (fma:SF (match_operand:SF 1 "register_operand" "f") (match_operand:SF 2 "register_operand" "f") (match_operand:SF 3 "register_operand" "f"))) @@ -2730,7 +2730,7 @@ ) (define_insn "fmssf4" - [(set (match_operand:SF 0 "register_operand" "=A") + [(set (match_operand:SF 0 "register_operand" "=c") (fma:SF (match_operand:SF 1 "register_operand" "f") (match_operand:SF 2 "register_operand" "f") (neg:SF (match_operand:SF 3 "register_operand" "f")))) @@ -2743,7 +2743,7 @@ ) (define_insn "fnmasf4" - [(set (match_operand:SF 0 "register_operand" "=A") + [(set (match_operand:SF 0 "register_operand" "=c") (fma:SF (neg:SF (match_operand:SF 1 "register_operand" "f")) (match_operand:SF 2 "register_operand" "f") (match_operand:SF 3 "register_operand" "f"))) @@ -2756,7 +2756,7 @@ ) (define_insn "fnmssf4" - [(set (match_operand:SF 0 "register_operand" "=A") + [(set (match_operand:SF 0 "register_operand" "=c") (fma:SF (neg:SF (match_operand:SF 1 "register_operand" "f")) (match_operand:SF 2 "register_operand" "f") (neg:SF (match_operand:SF 3 "register_operand" "f"))))