Patchwork [U-Boot,V2,2/5] ARM: Add Support for Marvell Pantheon Familiy SoCs

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Submitter Lei Wen
Date Jan. 10, 2011, 4:01 a.m.
Message ID <1294632087-8025-3-git-send-email-leiwen@marvell.com>
Download mbox | patch
Permalink /patch/78067/
State Superseded
Headers show

Comments

Lei Wen - Jan. 10, 2011, 4:01 a.m.
Pantheon Family processors are highly integrated SoCs
based on Sheeva_88SV331x-v5 PJ1 cpu core.
Ref:
http://www.marvell.com/products/processors/communications/marvell_pantheon_910_920_pb.pdf

SoC versions Supported:
1) PANTHEON920          (TD)
2) PANTHEON910          (TTC)

Signed-off-by: Lei Wen <leiwen@marvell.com>
---
 arch/arm/cpu/arm926ejs/pantheon/Makefile      |   46 ++++++
 arch/arm/cpu/arm926ejs/pantheon/cpu.c         |   78 ++++++++++
 arch/arm/cpu/arm926ejs/pantheon/dram.c        |  130 ++++++++++++++++
 arch/arm/cpu/arm926ejs/pantheon/timer.c       |  204 +++++++++++++++++++++++++
 arch/arm/include/asm/arch-pantheon/config.h   |   44 ++++++
 arch/arm/include/asm/arch-pantheon/cpu.h      |   79 ++++++++++
 arch/arm/include/asm/arch-pantheon/pantheon.h |   54 +++++++
 7 files changed, 635 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/cpu/arm926ejs/pantheon/Makefile
 create mode 100644 arch/arm/cpu/arm926ejs/pantheon/cpu.c
 create mode 100644 arch/arm/cpu/arm926ejs/pantheon/dram.c
 create mode 100644 arch/arm/cpu/arm926ejs/pantheon/timer.c
 create mode 100644 arch/arm/include/asm/arch-pantheon/config.h
 create mode 100644 arch/arm/include/asm/arch-pantheon/cpu.h
 create mode 100644 arch/arm/include/asm/arch-pantheon/pantheon.h
Prafulla Wadaskar - Jan. 10, 2011, 2:33 p.m.
> -----Original Message-----
> From: Lei Wen [mailto:leiwen@marvell.com]
> Sent: Monday, January 10, 2011 9:31 AM
> To: u-boot@lists.denx.de; Prafulla Wadaskar; Yu Tang; Ashish Karkare;
> Prabhanjan Sarnaik; adrian . wenl @ gmail . com "
> Subject: [PATCH V2 2/5] ARM: Add Support for Marvell Pantheon Familiy
> SoCs
> 
> Pantheon Family processors are highly integrated SoCs
> based on Sheeva_88SV331x-v5 PJ1 cpu core.
> Ref:
> http://www.marvell.com/products/processors/communications/marvell_panthe
> on_910_920_pb.pdf
> 
> SoC versions Supported:
> 1) PANTHEON920          (TD)
> 2) PANTHEON910          (TTC)
> 
> Signed-off-by: Lei Wen <leiwen@marvell.com>
> ---
>  arch/arm/cpu/arm926ejs/pantheon/Makefile      |   46 ++++++
>  arch/arm/cpu/arm926ejs/pantheon/cpu.c         |   78 ++++++++++
>  arch/arm/cpu/arm926ejs/pantheon/dram.c        |  130 ++++++++++++++++
>  arch/arm/cpu/arm926ejs/pantheon/timer.c       |  204
> +++++++++++++++++++++++++
>  arch/arm/include/asm/arch-pantheon/config.h   |   44 ++++++
>  arch/arm/include/asm/arch-pantheon/cpu.h      |   79 ++++++++++
>  arch/arm/include/asm/arch-pantheon/pantheon.h |   54 +++++++
>  7 files changed, 635 insertions(+), 0 deletions(-)
>  create mode 100644 arch/arm/cpu/arm926ejs/pantheon/Makefile
>  create mode 100644 arch/arm/cpu/arm926ejs/pantheon/cpu.c
>  create mode 100644 arch/arm/cpu/arm926ejs/pantheon/dram.c
>  create mode 100644 arch/arm/cpu/arm926ejs/pantheon/timer.c
>  create mode 100644 arch/arm/include/asm/arch-pantheon/config.h
>  create mode 100644 arch/arm/include/asm/arch-pantheon/cpu.h
>  create mode 100644 arch/arm/include/asm/arch-pantheon/pantheon.h
> 
> diff --git a/arch/arm/cpu/arm926ejs/pantheon/Makefile
> b/arch/arm/cpu/arm926ejs/pantheon/Makefile
> new file mode 100644
> index 0000000..73644c7
> --- /dev/null
> +++ b/arch/arm/cpu/arm926ejs/pantheon/Makefile
> @@ -0,0 +1,46 @@
> +#
> +# (C) Copyright 2010

2011 ??

Regards..
Prafulla . . .
Wolfgang Denk - Jan. 25, 2011, 9:32 p.m.
Dear Lei Wen,

In message <1294632087-8025-3-git-send-email-leiwen@marvell.com> you wrote:
> Pantheon Family processors are highly integrated SoCs
> based on Sheeva_88SV331x-v5 PJ1 cpu core.
> Ref:
> http://www.marvell.com/products/processors/communications/marvell_pantheon_910_920_pb.pdf
> 
> SoC versions Supported:
> 1) PANTHEON920          (TD)
> 2) PANTHEON910          (TTC)
> 
> Signed-off-by: Lei Wen <leiwen@marvell.com>
...
> +int dram_init(void)
> +{
...
> +	for (; i < CONFIG_NR_DRAM_BANKS; i++) {
> +		/* If above loop terminated prematurely, we need to set
> +		 * remaining banks' start address & size as 0. Otherwise other
> +		 * u-boot functions and Linux kernel gets wrong values which
> +		 * could result in crash */

Incorrect multiline comment style.

> +/* For preventing risk of instability in reading counter value,
> + * first set read request to register cvwr and then read same
> + * register after it captures counter value.
> + */

Ditto.  Please fix globally.

> +	writel(COUNT_RD_REQ, &panthtimers->cvwr);
> +	while (loop--);

Please write:

	while (loop--)
		;


But then - are you sure the compiler does not optimize this out?  You
probably want to use __udelay() instead.

...
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-pantheon/config.h
> @@ -0,0 +1,44 @@
...
> +/*
> + * There is no internal RAM in ARMADA100, using DRAM
> + * TBD: dcache to be used for this
> + */
> +#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_TEXT_BASE - 0x00200000)
> +#define CONFIG_NR_DRAM_BANKS_MAX	2

This looks like board specific code that should not be here.

...
> +struct panthmpmu_registers {
> +	u8 pad0[0x0024];
> +	u32 ccgr;	/*0x0024*/
> +	u8 pad1[0x0200 - 0x024 - 4];
> +	u32 wdtpcr;	/*0x0200*/
> +	u8 pad2[0x1020 - 0x200 - 4];
> +	u32 aprr;	/*0x1020*/
> +	u32 acgr;	/*0x1024*/
> +};

Please use TAB for vertical alignment of variable names.  Please fix
globally.


Best regards,

Wolfgang Denk
Lei Wen - Jan. 26, 2011, 2:01 a.m.
Hi Wolfgang,

On Wed, Jan 26, 2011 at 5:32 AM, Wolfgang Denk <wd@denx.de> wrote:
> Dear Lei Wen,
>
> In message <1294632087-8025-3-git-send-email-leiwen@marvell.com> you wrote:
>> Pantheon Family processors are highly integrated SoCs
>> based on Sheeva_88SV331x-v5 PJ1 cpu core.
>> Ref:
>> http://www.marvell.com/products/processors/communications/marvell_pantheon_910_920_pb.pdf
>>
>> SoC versions Supported:
>> 1) PANTHEON920          (TD)
>> 2) PANTHEON910          (TTC)
>>
>> Signed-off-by: Lei Wen <leiwen@marvell.com>
> ...
>> +int dram_init(void)
>> +{
> ...
>> +     for (; i < CONFIG_NR_DRAM_BANKS; i++) {
>> +             /* If above loop terminated prematurely, we need to set
>> +              * remaining banks' start address & size as 0. Otherwise other
>> +              * u-boot functions and Linux kernel gets wrong values which
>> +              * could result in crash */
>
> Incorrect multiline comment style.
>

This already fix in the v6 patch...
http://patchwork.ozlabs.org/patch/80305/

>> +/* For preventing risk of instability in reading counter value,
>> + * first set read request to register cvwr and then read same
>> + * register after it captures counter value.
>> + */
>
> Ditto.  Please fix globally.
>
>> +     writel(COUNT_RD_REQ, &panthtimers->cvwr);
>> +     while (loop--);
>
> Please write:
>
>        while (loop--)
>                ;

Fixed...
>
> But then - are you sure the compiler does not optimize this out?  You
> probably want to use __udelay() instead.

From the practice, we think this loop is enough to make timer stablize...
Involve the __udelay() may not suitable for the timer functions...

>
> ...
>> --- /dev/null
>> +++ b/arch/arm/include/asm/arch-pantheon/config.h
>> @@ -0,0 +1,44 @@
> ...
>> +/*
>> + * There is no internal RAM in ARMADA100, using DRAM
>> + * TBD: dcache to be used for this
>> + */
>> +#define CONFIG_SYS_INIT_SP_ADDR              (CONFIG_SYS_TEXT_BASE - 0x00200000)
>> +#define CONFIG_NR_DRAM_BANKS_MAX     2
>
> This looks like board specific code that should not be here.

Yep... I would update the patch for it. For V7...

>
> ...
>> +struct panthmpmu_registers {
>> +     u8 pad0[0x0024];
>> +     u32 ccgr;       /*0x0024*/
>> +     u8 pad1[0x0200 - 0x024 - 4];
>> +     u32 wdtpcr;     /*0x0200*/
>> +     u8 pad2[0x1020 - 0x200 - 4];
>> +     u32 aprr;       /*0x1020*/
>> +     u32 acgr;       /*0x1024*/
>> +};
>
> Please use TAB for vertical alignment of variable names.  Please fix
> globally.

In V6 patch , I think I already do like using tab. :)


Best regards,
Lei
Wolfgang Denk - Jan. 26, 2011, 7:50 a.m.
Dear Lei Wen,

In message <AANLkTin0HQKxKiLas8H4_GHmFsdi1Mt3gPbTK0A17r2d@mail.gmail.com> you wrote:
> 
> >> +       while (loop--);
> >
> > Please write:
> >
> >            while (loop--)
> >                        ;
> 
> Fixed...
> >
> > But then - are you sure the compiler does not optimize this out?   You
> > probably want to use __udelay() instead.
>
> From the practice, we think this loop is enough to make timer stablize...

There is nothing in this code to prevent the cmpiler from optimizing
this out.

You can as well delete these lines then.

If you need a delay, then you must do better.

> Involve the __udelay() may not suitable for the timer functions...

Depends...

Best regards,

Wolfgang Denk

Patch

diff --git a/arch/arm/cpu/arm926ejs/pantheon/Makefile b/arch/arm/cpu/arm926ejs/pantheon/Makefile
new file mode 100644
index 0000000..73644c7
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/pantheon/Makefile
@@ -0,0 +1,46 @@ 
+#
+# (C) Copyright 2010
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Lei Wen <leiwen@marvell.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(SOC).o
+
+COBJS-y	= cpu.o timer.o dram.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS-y))
+
+all:	$(obj).depend $(LIB)
+
+$(LIB):	$(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/arm/cpu/arm926ejs/pantheon/cpu.c b/arch/arm/cpu/arm926ejs/pantheon/cpu.c
new file mode 100644
index 0000000..fd006af
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/pantheon/cpu.c
@@ -0,0 +1,78 @@ 
+/*
+ * (C) Copyright 2010
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Lei Wen <leiwen@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <asm/arch/pantheon.h>
+#include <asm/io.h>
+
+#define UARTCLK14745KHZ	(APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1))
+#define SET_MRVL_ID	(1<<8)
+#define L2C_RAM_SEL	(1<<4)
+
+int arch_cpu_init(void)
+{
+	u32 val;
+	struct panthcpu_registers *cpuregs =
+		(struct panthcpu_registers*) PANTHEON_CPU_BASE;
+
+	struct panthapb_registers *apbclkres =
+		(struct panthapb_registers*) PANTHEON_APBC_BASE;
+
+	struct panthmpmu_registers *mpmu =
+		(struct panthmpmu_registers*) PANTHEON_MPMU_BASE;
+
+	/* set SEL_MRVL_ID bit in PANTHEON_CPU_CONF register */
+	val = readl(&cpuregs->cpu_conf);
+	val = val | SET_MRVL_ID;
+	writel(val, &cpuregs->cpu_conf);
+
+	/* Turn on clock gating (PMUM_CCGR) */
+	writel(0xFFFFFFFF, &mpmu->ccgr);
+
+	/* Turn on clock gating (PMUM_ACGR) */
+	writel(0xFFFFFFFF, &mpmu->acgr);
+
+	/* Turn on uart2 clock */
+	writel(UARTCLK14745KHZ, &apbclkres->uart0);
+
+	/* Enable GPIO clock */
+	writel(APBC_APBCLK, &apbclkres->gpio);
+
+	icache_enable();
+
+	return 0;
+}
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
+{
+	u32 id;
+	struct panthcpu_registers *cpuregs =
+		(struct panthcpu_registers*) PANTHEON_CPU_BASE;
+
+	id = readl(&cpuregs->chip_id);
+	printf("SoC:   PANTHEON 88AP%X-%X\n", (id & 0xFFF), (id >> 0x10));
+	return 0;
+}
+#endif
diff --git a/arch/arm/cpu/arm926ejs/pantheon/dram.c b/arch/arm/cpu/arm926ejs/pantheon/dram.c
new file mode 100644
index 0000000..0523cd0
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/pantheon/dram.c
@@ -0,0 +1,130 @@ 
+/*
+ * (C) Copyright 2010
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Lei Wen <leiwen@marvell.com>,
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <asm/arch/pantheon.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Pantheon DRAM controller supports upto 8 banks
+ * for chip select 0 and 1
+ */
+
+/*
+ * DDR Memory Control Registers
+ * Refer Datasheet 4.4
+ */
+struct panthddr_map_registers {
+	u32	cs;	/* Memory Address Map Register -CS */
+	u32	pad[3];
+};
+
+struct panthddr_registers {
+	u8	pad[0x100 - 0x000];
+	struct panthddr_map_registers mmap[2];
+};
+
+/*
+ * panth_sdram_base - reads SDRAM Base Address Register
+ */
+u32 panth_sdram_base(int chip_sel)
+{
+	struct panthddr_registers *ddr_regs =
+		(struct panthddr_registers *)PANTHEON_DRAM_BASE;
+	u32 result = 0;
+	u32 CS_valid = 0x01 & readl(&ddr_regs->mmap[chip_sel].cs);
+
+	if (!CS_valid)
+		return 0;
+
+	result = readl(&ddr_regs->mmap[chip_sel].cs) & 0xFF800000;
+	return result;
+}
+
+/*
+ * panth_sdram_size - reads SDRAM size
+ */
+u32 panth_sdram_size(int chip_sel)
+{
+	struct panthddr_registers *ddr_regs =
+		(struct panthddr_registers *)PANTHEON_DRAM_BASE;
+	u32 result = 0;
+	u32 CS_valid = 0x01 & readl(&ddr_regs->mmap[chip_sel].cs);
+
+	if (!CS_valid)
+		return 0;
+
+	result = readl(&ddr_regs->mmap[chip_sel].cs);
+	result = (result >> 16) & 0xF;
+	if (result < 0x7) {
+		printf("Unknown DRAM Size\n");
+		return -1;
+	} else {
+		return ((0x8 << (result - 0x7)) * 1024 * 1024);
+	}
+}
+
+#ifndef CONFIG_SYS_BOARD_DRAM_INIT
+int dram_init(void)
+{
+	int i;
+
+	gd->ram_size = 0;
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+		gd->bd->bi_dram[i].start = panth_sdram_base(i);
+		gd->bd->bi_dram[i].size = panth_sdram_size(i);
+		/*
+		 * It is assumed that all memory banks are consecutive
+		 * and without gaps.
+		 * If the gap is found, ram_size will be reported for
+		 * consecutive memory only
+		 */
+		if (gd->bd->bi_dram[i].start != gd->ram_size)
+			break;
+
+		gd->ram_size += gd->bd->bi_dram[i].size;
+
+	}
+
+	for (; i < CONFIG_NR_DRAM_BANKS; i++) {
+		/* If above loop terminated prematurely, we need to set
+		 * remaining banks' start address & size as 0. Otherwise other
+		 * u-boot functions and Linux kernel gets wrong values which
+		 * could result in crash */
+		gd->bd->bi_dram[i].start = 0;
+		gd->bd->bi_dram[i].size = 0;
+	}
+	return 0;
+}
+
+/*
+ * If this function is not defined here,
+ * board.c alters dram bank zero configuration defined above.
+ */
+void dram_init_banksize(void)
+{
+	dram_init();
+}
+#endif /* CONFIG_SYS_BOARD_DRAM_INIT */
diff --git a/arch/arm/cpu/arm926ejs/pantheon/timer.c b/arch/arm/cpu/arm926ejs/pantheon/timer.c
new file mode 100644
index 0000000..5d421df
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/pantheon/timer.c
@@ -0,0 +1,204 @@ 
+/*
+ * (C) Copyright 2010
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Lei Wen <leiwen@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <asm/arch/pantheon.h>
+
+/*
+ * Timer registers
+ * Refer 6.2.9 in Datasheet
+ */
+struct panthtmr_registers {
+	u32 clk_ctrl;	/* Timer clk control reg */
+	u32 match[9];	/* Timer match registers */
+	u32 count[3];	/* Timer count registers */
+	u32 status[3];
+	u32 ie[3];
+	u32 preload[3];	/* Timer preload value */
+	u32 preload_ctrl[3];
+	u32 wdt_match_en;
+	u32 wdt_match_r;
+	u32 wdt_val;
+	u32 wdt_sts;
+	u32 icr[3];
+	u32 wdt_icr;
+	u32 cer;	/* Timer count enable reg */
+	u32 cmr;
+	u32 ilr[3];
+	u32 wcr;
+	u32 wfar;
+	u32 wsar;
+	u32 cvwr[3];
+};
+
+#define TIMER			0	/* Use TIMER 0 */
+/* Each timer has 3 match registers */
+#define MATCH_CMP(x)		((3 * TIMER) + x)
+#define TIMER_LOAD_VAL 		0xffffffff
+#define	COUNT_RD_REQ		0x1
+
+DECLARE_GLOBAL_DATA_PTR;
+/* Using gd->tbu from timestamp and gd->tbl for lastdec */
+
+/* For preventing risk of instability in reading counter value,
+ * first set read request to register cvwr and then read same
+ * register after it captures counter value.
+ */
+ulong read_timer(void)
+{
+	struct panthtmr_registers *panthtimers =
+		(struct panthtmr_registers *) PANTHEON_TIMER_BASE;
+	volatile int loop=100;
+
+	writel(COUNT_RD_REQ, &panthtimers->cvwr);
+	while (loop--);
+	return(readl(&panthtimers->cvwr));
+}
+
+void reset_timer_masked(void)
+{
+	/* reset time */
+	gd->tbl = read_timer();
+	gd->tbu = 0;
+}
+
+ulong get_timer_masked(void)
+{
+	ulong now = read_timer();
+
+	if (now >= gd->tbl) {
+		/* normal mode */
+		gd->tbu += now - gd->tbl;
+	} else {
+		/* we have an overflow ... */
+		gd->tbu += now + TIMER_LOAD_VAL - gd->tbl;
+	}
+	gd->tbl = now;
+
+	return gd->tbu;
+}
+
+void reset_timer(void)
+{
+	reset_timer_masked();
+}
+
+ulong get_timer(ulong base)
+{
+	return ((get_timer_masked() / (CONFIG_SYS_HZ_CLOCK / 1000)) -
+		base);
+}
+
+void set_timer(ulong t)
+{
+	gd->tbu = t;
+}
+
+void __udelay(unsigned long usec)
+{
+	ulong delayticks;
+	ulong endtime;
+
+	delayticks = (usec * (CONFIG_SYS_HZ_CLOCK / 1000000));
+	endtime = get_timer_masked() + delayticks;
+
+	while (get_timer_masked() < endtime);
+}
+
+/*
+ * init the Timer
+ */
+int timer_init(void)
+{
+	struct panthapb_registers *apb1clkres =
+		(struct panthapb_registers *) PANTHEON_APBC_BASE;
+	struct panthtmr_registers *panthtimers =
+		(struct panthtmr_registers *) PANTHEON_TIMER_BASE;
+
+	/* Enable Timer clock at 3.25 MHZ */
+	writel(APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3), &apb1clkres->timers);
+
+	/* load value into timer */
+	writel(0x0, &panthtimers->clk_ctrl);
+	/* Use Timer 0 Match Resiger 0 */
+	writel(TIMER_LOAD_VAL, &panthtimers->match[MATCH_CMP(0)]);
+	/* Preload value is 0 */
+	writel(0x0, &panthtimers->preload[TIMER]);
+	/* Enable match comparator 0 for Timer 0 */
+	writel(0x1, &panthtimers->preload_ctrl[TIMER]);
+
+	/* Enable timer 0 */
+	writel(0x1, &panthtimers->cer);
+	/* init the gd->tbu and gd->tbl value */
+	reset_timer_masked();
+
+	return 0;
+}
+
+#define MPMU_APRR_WDTR	(1<<4)
+#define TMR_WFAR	0xbaba	/* WDT Register First key */
+#define TMP_WSAR	0xeb10	/* WDT Register Second key */
+
+/*
+ * This function uses internal Watchdog Timer
+ * based reset mechanism.
+ * Steps to write watchdog registers (protected access)
+ * 1. Write key value to TMR_WFAR reg.
+ * 2. Write key value to TMP_WSAR reg.
+ * 3. Perform write operation.
+ */
+void reset_cpu (unsigned long ignored)
+{
+	struct panthmpmu_registers *mpmu =
+		(struct panthmpmu_registers *) PANTHEON_MPMU_BASE;
+	struct panthtmr_registers *panthtimers =
+		(struct panthtmr_registers *) PANTHEON_WD_TIMER_BASE;
+	u32 val;
+
+	/* negate hardware reset to the WDT after system reset */
+	val = readl(&mpmu->aprr);
+	val = val | MPMU_APRR_WDTR;
+	writel(val, &mpmu->aprr);
+
+	/* reset/enable WDT clock */
+	writel(APBC_APBCLK, &mpmu->wdtpcr);
+
+	/* clear previous WDT status */
+	writel(TMR_WFAR, &panthtimers->wfar);
+	writel(TMP_WSAR, &panthtimers->wsar);
+	writel(0, &panthtimers->wdt_sts);
+
+	/* set match counter */
+	writel(TMR_WFAR, &panthtimers->wfar);
+	writel(TMP_WSAR, &panthtimers->wsar);
+	writel(0xf, &panthtimers->wdt_match_r);
+
+	/* enable WDT reset */
+	writel(TMR_WFAR, &panthtimers->wfar);
+	writel(TMP_WSAR, &panthtimers->wsar);
+	writel(0x3, &panthtimers->wdt_match_en);
+
+	/*enable functional WDT clock */
+	writel(APBC_APBCLK | APBC_FNCLK, &mpmu->wdtpcr);
+}
diff --git a/arch/arm/include/asm/arch-pantheon/config.h b/arch/arm/include/asm/arch-pantheon/config.h
new file mode 100644
index 0000000..06c9cb8
--- /dev/null
+++ b/arch/arm/include/asm/arch-pantheon/config.h
@@ -0,0 +1,44 @@ 
+/*
+ * (C) Copyright 2010
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Lei Wen <leiwen@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _PANTHEON_CONFIG_H
+#define _PANTHEON_CONFIG_H
+
+#define CONFIG_ARM926EJS	1	/* Basic Architecture */
+
+#define CONFIG_SYS_TCLK		(14745600)	/* NS16550 clk config */
+#define CONFIG_SYS_HZ_CLOCK	(3250000)	/* Timer Freq. 3.25MHZ */
+#define CONFIG_MARVELL_MFP			/* Enable mvmfp driver */
+#define MV_MFPR_BASE		PANTHEON_MFPR_BASE
+#define MV_UART_CONSOLE_BASE	PANTHEON_UART1_BASE
+#define CONFIG_SYS_NS16550_IER	(1 << 6)	/* Bit 6 in UART_IER register
+						represents UART Unit Enable */
+/*
+ * There is no internal RAM in ARMADA100, using DRAM
+ * TBD: dcache to be used for this
+ */
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_TEXT_BASE - 0x00200000)
+#define CONFIG_NR_DRAM_BANKS_MAX	2
+
+#endif /* _PANTHEON_CONFIG_H */
diff --git a/arch/arm/include/asm/arch-pantheon/cpu.h b/arch/arm/include/asm/arch-pantheon/cpu.h
new file mode 100644
index 0000000..1f112c9
--- /dev/null
+++ b/arch/arm/include/asm/arch-pantheon/cpu.h
@@ -0,0 +1,79 @@ 
+/*
+ * (C) Copyright 2010
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Lei Wen <leiwen@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _PANTHEON_CPU_H
+#define _PANTHEON_CPU_H
+
+#include <asm/io.h>
+#include <asm/system.h>
+
+/*
+ * Main Power Management (MPMU) Registers
+ * Refer Register Datasheet 9.1
+ */
+struct panthmpmu_registers {
+	u8 pad0[0x0024];
+	u32 ccgr;	/*0x0024*/
+	u8 pad1[0x0200 - 0x024 - 4];
+	u32 wdtpcr;	/*0x0200*/
+	u8 pad2[0x1020 - 0x200 - 4];
+	u32 aprr;	/*0x1020*/
+	u32 acgr;	/*0x1024*/
+};
+
+/*
+ * APB Clock Reset/Control Registers
+ * Refer Register Datasheet 6.14
+ */
+struct panthapb_registers {
+	u32 uart0;	/*0x000*/
+	u32 uart1;	/*0x004*/
+	u32 gpio;	/*0x008*/
+	u8 pad0[0x034 - 0x08 - 4];
+	u32 timers;	/*0x034*/
+};
+
+/*
+ * CPU Interface Registers
+ * Refer Register Datasheet 4.3
+ */
+struct panthcpu_registers {
+	u32 chip_id;		/* Chip Id Reg */
+	u32 pad;
+	u32 cpu_conf;		/* CPU Conf Reg */
+	u32 pad1;
+	u32 cpu_sram_spd;	/* CPU SRAM Speed Reg */
+	u32 pad2;
+	u32 cpu_l2c_spd;	/* CPU L2cache Speed Conf */
+	u32 mcb_conf;		/* MCB Conf Reg */
+	u32 sys_boot_ctl;	/* Sytem Boot Control */
+};
+
+/*
+ * Functions
+ */
+u32 panth_sdram_base(int);
+u32 panth_sdram_size(int);
+
+#endif /* _PANTHEON_CPU_H */
diff --git a/arch/arm/include/asm/arch-pantheon/pantheon.h b/arch/arm/include/asm/arch-pantheon/pantheon.h
new file mode 100644
index 0000000..fb1b1b5
--- /dev/null
+++ b/arch/arm/include/asm/arch-pantheon/pantheon.h
@@ -0,0 +1,54 @@ 
+/*
+ * (C) Copyright 2010
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Lei Wen <leiwen@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _PANTHEON_H
+#define _PANTHEON_H
+
+#ifndef __ASSEMBLY__
+#include <asm/types.h>
+#include <asm/io.h>
+#endif	/* __ASSEMBLY__ */
+
+#include <asm/arch/cpu.h>
+
+/* Common APB clock register bit definitions */
+#define APBC_APBCLK     (1<<0)  /* APB Bus Clock Enable */
+#define APBC_FNCLK      (1<<1)  /* Functional Clock Enable */
+#define APBC_RST        (1<<2)  /* Reset Generation */
+/* Functional Clock Selection Mask */
+#define APBC_FNCLKSEL(x)        (((x) & 0xf) << 4)
+
+/* Register Base Addresses */
+#define PANTHEON_DRAM_BASE	0xB0000000
+#define PANTHEON_TIMER_BASE	0xD4014000
+#define PANTHEON_WD_TIMER_BASE	0xD4080000
+#define PANTHEON_APBC_BASE	0xD4015000
+#define PANTHEON_UART1_BASE	0xD4017000
+#define PANTHEON_UART2_BASE	0xD4018000
+#define PANTHEON_GPIO_BASE	0xD4019000
+#define PANTHEON_MFPR_BASE	0xD401E000
+#define PANTHEON_MPMU_BASE	0xD4050000
+#define PANTHEON_CPU_BASE	0xD4282C00
+
+#endif /* _PANTHEON_H */