diff mbox

[AArch64] optimize float immediate moves (3 /4) - testsuite.

Message ID VI1PR0801MB2031A417A9F60B12103E0144FFDF0@VI1PR0801MB2031.eurprd08.prod.outlook.com
State New
Headers show

Commit Message

Tamar Christina June 26, 2017, 10:49 a.m. UTC 
Hi,

With the changes in the patches the testsuite had a minor update in the assembler scan.
I've posted the patch but will assume it's OK based on the previous OK for trunk and
the fact that this can fall in the obvious rule.

Thanks,
Tamar

Comments

Bin.Cheng Aug. 1, 2017, 9:48 a.m. UTC | #1 
On Mon, Jun 26, 2017 at 11:49 AM, Tamar Christina
<Tamar.Christina@arm.com> wrote:
> Hi,
>
> With the changes in the patches the testsuite had a minor update in the assembler scan.
> I've posted the patch but will assume it's OK based on the previous OK for trunk and
> the fact that this can fall in the obvious rule.
Hi,
With below commit:
commit b78acb5046f8b0e517f39edf17751b275d026b6c
Author: tnfchris <tnfchris@138bc75d-0d04-0410-961f-82ee72b054a4>
Date:   Fri Jul 28 15:14:25 2017 +0000

    2017-07-28  Tamar Christina  <tamar.christina@arm.com>
            Bilyan Borisov  <bilyan.borisov@arm.com>

        * gcc.target/aarch64/dbl_mov_immediate_1.c: New.
        * gcc.target/aarch64/flt_mov_immediate_1.c: New.
        * gcc.target/aarch64/f16_mov_immediate_1.c: New.
        * gcc.target/aarch64/f16_mov_immediate_2.c: New.
        * gcc.target/aarch64/pr63304_1.c: Changed to double.

I saw test failure on aarch64_be.
FAIL: gcc.target/aarch64/dbl_mov_immediate_1.c scan-assembler-times
mov\tx[0-9]+, 25838523252736 1
FAIL: gcc.target/aarch64/dbl_mov_immediate_1.c scan-assembler-times
movk\tx[0-9]+, 0x40fe, lsl 48 1
FAIL: gcc.target/aarch64/dbl_mov_immediate_1.c scan-assembler-times
mov\tx[0-9]+, -9223372036854775808 1

Thanks,
bin
>
> Thanks,
> Tamar
> ________________________________________
> From: James Greenhalgh <james.greenhalgh@arm.com>
> Sent: Wednesday, June 14, 2017 10:11:19 AM
> To: Tamar Christina
> Cc: GCC Patches; nd; Richard Earnshaw; Marcus Shawcroft
> Subject: Re: [PATCH][GCC][AArch64] optimize float immediate moves (3 /4) - testsuite.
>
> On Wed, Jun 07, 2017 at 12:38:41PM +0100, Tamar Christina wrote:
>> Hi All,
>>
>>
>> This patch adds new tests to cover the newly generated code from this patch series.
>>
>>
>> Regression tested on aarch64-none-linux-gnu and no regressions.
>>
>> OK for trunk?
>
> OK.
>
> Thanks,
> James
>
>>
>> gcc/testsuite/
>> 2017-06-07  Tamar Christina  <tamar.christina@arm.com>
>>           Bilyan Borisov  <bilyan.borisov@arm.com>
>>
>>       * gcc.target/aarch64/dbl_mov_immediate_1.c: New.
>>       * gcc.target/aarch64/flt_mov_immediate_1.c: New.
>>       * gcc.target/aarch64/f16_mov_immediate_1.c: New.
>>       * gcc.target/aarch64/f16_mov_immediate_2.c: New.
>
>
diff mbox

Patch

diff --git a/gcc/testsuite/gcc.target/aarch64/dbl_mov_immediate_1.c b/gcc/testsuite/gcc.target/aarch64/dbl_mov_immediate_1.c
new file mode 100644
index 0000000000000000000000000000000000000000..eb5b23b8f842c1f299bd58c8f944dce6234c111b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/dbl_mov_immediate_1.c
@@ -0,0 +1,52 @@ 
+/* { dg-do compile } */
+/* { dg-options "-O3" } */
+
+double d0(void)
+{
+  double x = 0.0d;
+  return x;
+}
+
+double dn1(void)
+{
+  double x = -0.0d;
+  return x;
+}
+
+
+double d1(void)
+{
+  double x = 1.5d;
+  return x;
+}
+
+double d2(void)
+{
+  double x = 123256.0d;
+  return x;
+}
+
+double d3(void)
+{
+  double x = 123256123456.0d;
+  return x;
+}
+
+double d4(void)
+{
+  double x = 123456123456123456.0d;
+  return x;
+}
+
+/* { dg-final { scan-assembler-times "movi\td\[0-9\]+, ?#0"                 1 } } */
+
+/* { dg-final { scan-assembler-times "adrp\tx\[0-9\]+, \.LC\[0-9\]"         2 } } */
+/* { dg-final { scan-assembler-times "ldr\td\[0-9\]+, \\\[x\[0-9\], #:lo12:\.LC\[0-9\]\\\]" 2 } } */
+
+/* { dg-final { scan-assembler-times "fmov\td\[0-9\]+, 1\\\.5e\\\+0"        1 } } */
+
+/* { dg-final { scan-assembler-times "mov\tx\[0-9\]+, 25838523252736"       1 } } */
+/* { dg-final { scan-assembler-times "movk\tx\[0-9\]+, 0x40fe, lsl 48"      1 } } */
+/* { dg-final { scan-assembler-times "mov\tx\[0-9\]+, -9223372036854775808" 1 } } */
+/* { dg-final { scan-assembler-times "fmov\td\[0-9\]+, x\[0-9\]+"           2 } } */
+
diff --git a/gcc/testsuite/gcc.target/aarch64/f16_mov_immediate_1.c b/gcc/testsuite/gcc.target/aarch64/f16_mov_immediate_1.c
new file mode 100644
index 0000000000000000000000000000000000000000..1ed3831e139745227487eafa3ccfdc05c99deb34
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/f16_mov_immediate_1.c
@@ -0,0 +1,49 @@ 
+/* { dg-do compile } */
+/* { dg-options "-O3" } */
+/* { dg-require-effective-target arm_v8_2a_fp16_scalar_ok } */
+/* { dg-add-options arm_v8_2a_fp16_scalar } */
+
+extern __fp16 foo ();
+extern void bar (__fp16* x);
+
+void f1 ()
+{
+  volatile __fp16 a = 17.0;
+}
+
+
+void f2 (__fp16 *a)
+{
+  *a = 17.0;
+}
+
+void f3 ()
+{
+  __fp16 b = foo ();
+  b = 17.0;
+  bar (&b);
+}
+
+__fp16 f4 ()
+{
+  __fp16 a = 0;
+  __fp16 b = 1;
+  __fp16 c = 2;
+  __fp16 d = 4;
+
+  __fp16 z = a + b;
+  z = z + c;
+  z = z - d;
+  return z;
+}
+
+__fp16 f5 ()
+{
+  __fp16 a = 16;
+  bar (&a);
+  return a;
+}
+
+/* { dg-final { scan-assembler-times "mov\tw\[0-9\]+, #?19520"           3 } } */
+/* { dg-final { scan-assembler-times "movi\tv\[0-9\]+\\\.2s, 0xbc, lsl 8"  1 } } */
+/* { dg-final { scan-assembler-times "movi\tv\[0-9\]+\\\.2s, 0x4c, lsl 8"  1 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/f16_mov_immediate_2.c b/gcc/testsuite/gcc.target/aarch64/f16_mov_immediate_2.c
new file mode 100644
index 0000000000000000000000000000000000000000..6f44821e9d08d4c3b87eb52b70491183a32ac2ff
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/f16_mov_immediate_2.c
@@ -0,0 +1,45 @@ 
+/* { dg-do compile } */
+/* { dg-options "-O3" } */
+/* { dg-require-effective-target arm_v8_2a_fp16_scalar_ok } */
+/* { dg-add-options arm_v8_2a_fp16_scalar } */
+
+#include <arm_fp16.h>
+
+float16_t f0(void)
+{
+  float16_t x = 0.0f;
+  return x;
+}
+
+float16_t fn1(void)
+{
+  float16_t x = -0.0f;
+  return x;
+}
+
+float16_t f1(void)
+{
+  float16_t x = 256.0f;
+  return x;
+}
+
+float16_t f2(void)
+{
+  float16_t x = 123256.0f;
+  return x;
+}
+
+float16_t f3(void)
+{
+  float16_t x = 17.0;
+  return x;
+}
+
+/* { dg-final { scan-assembler-times "movi\tv\[0-9\]+\\\.4h, ?#0"         1 } } */
+/* { dg-final { scan-assembler-times "movi\tv\[0-9\]+\\\.2s, 0x80, lsl 8" 1 } } */
+/* { dg-final { scan-assembler-times "movi\tv\[0-9\]+\\\.2s, 0x5c, lsl 8" 1 } } */
+/* { dg-final { scan-assembler-times "movi\tv\[0-9\]+\\\.2s, 0x7c, lsl 8" 1 } } */
+
+/* { dg-final { scan-assembler-times "mov\tw\[0-9\]+, 19520"              1 } } */
+/* { dg-final { scan-assembler-times "fmov\th\[0-9\], w\[0-9\]+"          1 } } */
+
diff --git a/gcc/testsuite/gcc.target/aarch64/flt_mov_immediate_1.c b/gcc/testsuite/gcc.target/aarch64/flt_mov_immediate_1.c
new file mode 100644
index 0000000000000000000000000000000000000000..7b92a5ae40fbd042a6b564a557118d8f8eac7abd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/flt_mov_immediate_1.c
@@ -0,0 +1,52 @@ 
+/* { dg-do compile } */
+/* { dg-options "-O3" } */
+
+float f0(void)
+{
+  float x = 0.0f;
+  return x;
+}
+
+float fn1(void)
+{
+  float x = -0.0f;
+  return x;
+}
+
+float f1(void)
+{
+  float x = 256.0f;
+  return x;
+}
+
+float f2(void)
+{
+  float x = 123256.0f;
+  return x;
+}
+
+float f3(void)
+{
+  float x = 2.0f;
+  return x;
+}
+
+float f4(void)
+{
+  float x = -20000.1;
+  return x;
+}
+
+
+/* { dg-final { scan-assembler-times "movi\tv\[0-9\]+\\\.2s, ?#0"           1 } } */
+/* { dg-final { scan-assembler-times "movi\tv\[0-9\]+\\\.2s, 0x80, lsl 24"  1 } } */
+/* { dg-final { scan-assembler-times "movi\tv\[0-9\]+\\\.2s, 0x80, lsl 24"  1 } } */
+
+/* { dg-final { scan-assembler-times "mov\tw\[0-9\]+, 48128"                1 } } */
+/* { dg-final { scan-assembler-times "movk\tw\[0-9\]+, 0x47f0, lsl 16"      1 } } */
+
+/* { dg-final { scan-assembler-times "fmov\ts\[0-9\]+, 2\\\.0e\\\+0"  1 } } */
+
+/* { dg-final { scan-assembler-times "mov\tw\[0-9\]+, 16435"                1 } } */
+/* { dg-final { scan-assembler-times "movk\tw\[0-9\]+, 0xc69c, lsl 16"      1 } } */
+