Patchwork [4/7] tcg-ia64: Implement deposit operation.

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Submitter Richard Henderson
Date Jan. 7, 2011, 10:43 p.m.
Message ID <1294440183-885-5-git-send-email-rth@twiddle.net>
Download mbox | patch
Permalink /patch/77932/
State New
Headers show

Comments

Richard Henderson - Jan. 7, 2011, 10:43 p.m.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 tcg/ia64/tcg-target.c |   92 +++++++++++++++++++++++++++++++++++++++++++++++++
 tcg/ia64/tcg-target.h |    2 +
 2 files changed, 94 insertions(+), 0 deletions(-)
Aurelien Jarno - Jan. 9, 2011, 10:04 p.m.
On Fri, Jan 07, 2011 at 02:43:00PM -0800, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <rth@twiddle.net>
> ---
>  tcg/ia64/tcg-target.c |   92 +++++++++++++++++++++++++++++++++++++++++++++++++
>  tcg/ia64/tcg-target.h |    2 +
>  2 files changed, 94 insertions(+), 0 deletions(-)
> 
> diff --git a/tcg/ia64/tcg-target.c b/tcg/ia64/tcg-target.c
> index 3ddf434..2708d55 100644
> --- a/tcg/ia64/tcg-target.c
> +++ b/tcg/ia64/tcg-target.c
> @@ -237,6 +237,7 @@ enum {
>      OPC_CMP4_LT_A6            = 0x18400000000ull,
>      OPC_CMP4_LTU_A6           = 0x1a400000000ull,
>      OPC_CMP4_EQ_A6            = 0x1c400000000ull,
> +    OPC_DEP_I15               = 0x08000000000ull,
>      OPC_DEP_Z_I12             = 0x0a600000000ull,
>      OPC_EXTR_I11              = 0x0a400002000ull,
>      OPC_EXTR_U_I11            = 0x0a400000000ull,
> @@ -508,6 +509,19 @@ static inline uint64_t tcg_opc_i12(int qp, uint64_t opc, int r1,
>             | (qp & 0x3f);
>  }
>  
> +static inline uint64_t tcg_opc_i15(int qp, uint64_t opc, int r1,
> +                                   int r2, int r3, int len, uint64_t len,
> +                                   uint64_t cpos)
> +{
> +    return opc
> +           | ((cpos & 0x3f) << 31)
> +           | ((len & 0x0f) << 27)
> +           | ((r3 & 0x7f) << 20)
> +           | ((r2 & 0x7f) << 13)
> +           | ((r1 & 0x7f) << 6)
> +           | (qp & 0x3f);
> +}
> +
>  static inline uint64_t tcg_opc_i18(int qp, uint64_t opc, uint64_t imm)
>  {
>      return opc
> @@ -1335,6 +1349,73 @@ static inline void tcg_out_bswap64(TCGContext *s, TCGArg ret, TCGArg arg)
>                     tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, ret, arg, 0xb));
>  }
>  
> +static void tcg_out_deposit_i32(TCGContext *s, TCGArg out, TCGArg in,
> +                                TCGArg val, unsigned ofs, unsigned len)
> +{
> +    uint64_t nop_m = tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0);
> +
> +    if (val == 0) {
> +        tcg_out_bundle(s, mmI, nop_m, nop_m,
> +                       tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, out, in,
> +                                   len - 1, 63 - ofs));
> +    } else if (len <= 16) {
> +        tcg_out_bundle(s, mmI, nop_m, nop_m,
> +                       tcg_opc_i15(TCG_REG_P0, OPC_DEP_I15, out, in, val,
> +                                   len - 1, 63 - ofs));
> +    } else {
> +        tcg_out_bundle(s, miI, nop_m,
> +                       tcg_opc_i11(TCG_REG_P0, OPC_EXTR_U_I11, TCG_REG_R2,
> +                                   val, 16, 31 - 16),
> +                       tcg_opc_i15(TCG_REG_P0, OPC_DEP_I15, out, in, val,
> +                                   16 - 1, 63 - ofs));
> +        tcg_out_bundle(s, mmI, nop_m, nop_m,
> +                       tcg_opc_i15(TCG_REG_P0, OPC_DEP_I15, out, out,
> +                                   TCG_REG_R2, len - 16 - 1, 63 - (ofs + 16)));
> +    }
> +}
> +
> +static void tcg_out_deposit_i64(TCGContext *s, TCGArg out, TCGArg in,
> +                                TCGArg val, unsigned ofs, unsigned len)
> +{
> +    uint64_t nop_m = tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0);
> +
> +    if (val == 0) {
> +        tcg_out_bundle(s, mmI, nop_m, nop_m,
> +                       tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, out, in,
> +                                   len - 1, 63 - ofs));
> +    } else if (len <= 16) {
> +        tcg_out_bundle(s, mmI, nop_m, nop_m,
> +                       tcg_opc_i15(TCG_REG_P0, OPC_DEP_I15, out, in, val,
> +                                   len - 1, 63 - ofs));
> +    } else {
> +        uint64_t ror = 0, shrp, rol = 0;
> +
> +        if (ofs) {
> +	    ror = tcg_opc_i10(TCG_REG_P0, OPC_SHRP_I10, TCG_REG_R2,
> +                              in, in, ofs);
> +            in = TCG_REG_R2;
> +        }
> +
> +        shrp = tcg_opc_i10(TCG_REG_P0, OPC_SHRP_I10, out, in, val, len);
> +
> +        ofs = (ofs - len) & 63;
> +        if (ofs) {
> +            rol = tcg_opc_i10(TCG_REG_P0, OPC_SHRP_I10, out, out, out, 64-ofs);
> +        }
> +
> +        if (ror) {
> +            tcg_out_bundle(s, mII, nop_m, ror, shrp);
> +            if (rol) {
> +                tcg_out_bundle(s, mmI, nop_m, nop_m, rol);
> +            }
> +        } else if (rol) {
> +            tcg_out_bundle(s, mII, nop_m, shrp, rol);
> +        } else {
> +            tcg_out_bundle(s, mmI, nop_m, nop_m, shrp);
> +        }
> +    }
> +}
> +
>  static inline uint64_t tcg_opc_cmp_a(int qp, TCGCond cond, TCGArg arg1,
>                                       TCGArg arg2, int cmp4)
>  {
> @@ -2063,6 +2144,15 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
>          tcg_out_rotr_i64(s, args[0], args[1], args[2], const_args[2]);
>          break;
>  
> +    case INDEX_op_deposit_i32:
> +        tcg_out_deposit_i32(s, args[0], args[1], args[2],
> +                            (args[3] >> 8) & 31, args[3] & 31);
> +        break;
> +    case INDEX_op_deposit_i64:
> +        tcg_out_deposit_i64(s, args[0], args[1], args[2],
> +                            (args[3] >> 8) & 63, args[3] & 63);
> +        break;
> +
>      case INDEX_op_ext8s_i32:
>      case INDEX_op_ext8s_i64:
>          tcg_out_ext(s, OPC_SXT1_I29, args[0], args[1]);
> @@ -2192,6 +2282,7 @@ static const TCGTargetOpDef ia64_op_defs[] = {
>      { INDEX_op_shr_i32, { "r", "rZ", "ri" } },
>      { INDEX_op_rotl_i32, { "r", "rZ", "ri" } },
>      { INDEX_op_rotr_i32, { "r", "rZ", "ri" } },
> +    { INDEX_op_deposit_i32, { "r", "rZ", "rZ" } },
>  
>      { INDEX_op_ext8s_i32, { "r", "rZ"} },
>      { INDEX_op_ext8u_i32, { "r", "rZ"} },
> @@ -2238,6 +2329,7 @@ static const TCGTargetOpDef ia64_op_defs[] = {
>      { INDEX_op_shr_i64, { "r", "rZ", "ri" } },
>      { INDEX_op_rotl_i64, { "r", "rZ", "ri" } },
>      { INDEX_op_rotr_i64, { "r", "rZ", "ri" } },
> +    { INDEX_op_deposit_i64, { "r", "rZ", "rZ" } },
>  
>      { INDEX_op_ext8s_i64, { "r", "rZ"} },
>      { INDEX_op_ext8u_i64, { "r", "rZ"} },
> diff --git a/tcg/ia64/tcg-target.h b/tcg/ia64/tcg-target.h
> index e56e88f..80e3534 100644
> --- a/tcg/ia64/tcg-target.h
> +++ b/tcg/ia64/tcg-target.h
> @@ -131,6 +131,8 @@ enum {
>  #define TCG_TARGET_HAS_orc_i64
>  #define TCG_TARGET_HAS_rot_i32
>  #define TCG_TARGET_HAS_rot_i64
> +#define TCG_TARGET_HAS_deposit_i32
> +#define TCG_TARGET_HAS_deposit_i64
>  
>  /* optional instructions automatically implemented */
>  #undef TCG_TARGET_HAS_neg_i32   /* sub r1, r0, r3 */

I haven't tested it yet, but it looks ok.

Patch

diff --git a/tcg/ia64/tcg-target.c b/tcg/ia64/tcg-target.c
index 3ddf434..2708d55 100644
--- a/tcg/ia64/tcg-target.c
+++ b/tcg/ia64/tcg-target.c
@@ -237,6 +237,7 @@  enum {
     OPC_CMP4_LT_A6            = 0x18400000000ull,
     OPC_CMP4_LTU_A6           = 0x1a400000000ull,
     OPC_CMP4_EQ_A6            = 0x1c400000000ull,
+    OPC_DEP_I15               = 0x08000000000ull,
     OPC_DEP_Z_I12             = 0x0a600000000ull,
     OPC_EXTR_I11              = 0x0a400002000ull,
     OPC_EXTR_U_I11            = 0x0a400000000ull,
@@ -508,6 +509,19 @@  static inline uint64_t tcg_opc_i12(int qp, uint64_t opc, int r1,
            | (qp & 0x3f);
 }
 
+static inline uint64_t tcg_opc_i15(int qp, uint64_t opc, int r1,
+                                   int r2, int r3, int len, uint64_t len,
+                                   uint64_t cpos)
+{
+    return opc
+           | ((cpos & 0x3f) << 31)
+           | ((len & 0x0f) << 27)
+           | ((r3 & 0x7f) << 20)
+           | ((r2 & 0x7f) << 13)
+           | ((r1 & 0x7f) << 6)
+           | (qp & 0x3f);
+}
+
 static inline uint64_t tcg_opc_i18(int qp, uint64_t opc, uint64_t imm)
 {
     return opc
@@ -1335,6 +1349,73 @@  static inline void tcg_out_bswap64(TCGContext *s, TCGArg ret, TCGArg arg)
                    tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, ret, arg, 0xb));
 }
 
+static void tcg_out_deposit_i32(TCGContext *s, TCGArg out, TCGArg in,
+                                TCGArg val, unsigned ofs, unsigned len)
+{
+    uint64_t nop_m = tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0);
+
+    if (val == 0) {
+        tcg_out_bundle(s, mmI, nop_m, nop_m,
+                       tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, out, in,
+                                   len - 1, 63 - ofs));
+    } else if (len <= 16) {
+        tcg_out_bundle(s, mmI, nop_m, nop_m,
+                       tcg_opc_i15(TCG_REG_P0, OPC_DEP_I15, out, in, val,
+                                   len - 1, 63 - ofs));
+    } else {
+        tcg_out_bundle(s, miI, nop_m,
+                       tcg_opc_i11(TCG_REG_P0, OPC_EXTR_U_I11, TCG_REG_R2,
+                                   val, 16, 31 - 16),
+                       tcg_opc_i15(TCG_REG_P0, OPC_DEP_I15, out, in, val,
+                                   16 - 1, 63 - ofs));
+        tcg_out_bundle(s, mmI, nop_m, nop_m,
+                       tcg_opc_i15(TCG_REG_P0, OPC_DEP_I15, out, out,
+                                   TCG_REG_R2, len - 16 - 1, 63 - (ofs + 16)));
+    }
+}
+
+static void tcg_out_deposit_i64(TCGContext *s, TCGArg out, TCGArg in,
+                                TCGArg val, unsigned ofs, unsigned len)
+{
+    uint64_t nop_m = tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0);
+
+    if (val == 0) {
+        tcg_out_bundle(s, mmI, nop_m, nop_m,
+                       tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, out, in,
+                                   len - 1, 63 - ofs));
+    } else if (len <= 16) {
+        tcg_out_bundle(s, mmI, nop_m, nop_m,
+                       tcg_opc_i15(TCG_REG_P0, OPC_DEP_I15, out, in, val,
+                                   len - 1, 63 - ofs));
+    } else {
+        uint64_t ror = 0, shrp, rol = 0;
+
+        if (ofs) {
+	    ror = tcg_opc_i10(TCG_REG_P0, OPC_SHRP_I10, TCG_REG_R2,
+                              in, in, ofs);
+            in = TCG_REG_R2;
+        }
+
+        shrp = tcg_opc_i10(TCG_REG_P0, OPC_SHRP_I10, out, in, val, len);
+
+        ofs = (ofs - len) & 63;
+        if (ofs) {
+            rol = tcg_opc_i10(TCG_REG_P0, OPC_SHRP_I10, out, out, out, 64-ofs);
+        }
+
+        if (ror) {
+            tcg_out_bundle(s, mII, nop_m, ror, shrp);
+            if (rol) {
+                tcg_out_bundle(s, mmI, nop_m, nop_m, rol);
+            }
+        } else if (rol) {
+            tcg_out_bundle(s, mII, nop_m, shrp, rol);
+        } else {
+            tcg_out_bundle(s, mmI, nop_m, nop_m, shrp);
+        }
+    }
+}
+
 static inline uint64_t tcg_opc_cmp_a(int qp, TCGCond cond, TCGArg arg1,
                                      TCGArg arg2, int cmp4)
 {
@@ -2063,6 +2144,15 @@  static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
         tcg_out_rotr_i64(s, args[0], args[1], args[2], const_args[2]);
         break;
 
+    case INDEX_op_deposit_i32:
+        tcg_out_deposit_i32(s, args[0], args[1], args[2],
+                            (args[3] >> 8) & 31, args[3] & 31);
+        break;
+    case INDEX_op_deposit_i64:
+        tcg_out_deposit_i64(s, args[0], args[1], args[2],
+                            (args[3] >> 8) & 63, args[3] & 63);
+        break;
+
     case INDEX_op_ext8s_i32:
     case INDEX_op_ext8s_i64:
         tcg_out_ext(s, OPC_SXT1_I29, args[0], args[1]);
@@ -2192,6 +2282,7 @@  static const TCGTargetOpDef ia64_op_defs[] = {
     { INDEX_op_shr_i32, { "r", "rZ", "ri" } },
     { INDEX_op_rotl_i32, { "r", "rZ", "ri" } },
     { INDEX_op_rotr_i32, { "r", "rZ", "ri" } },
+    { INDEX_op_deposit_i32, { "r", "rZ", "rZ" } },
 
     { INDEX_op_ext8s_i32, { "r", "rZ"} },
     { INDEX_op_ext8u_i32, { "r", "rZ"} },
@@ -2238,6 +2329,7 @@  static const TCGTargetOpDef ia64_op_defs[] = {
     { INDEX_op_shr_i64, { "r", "rZ", "ri" } },
     { INDEX_op_rotl_i64, { "r", "rZ", "ri" } },
     { INDEX_op_rotr_i64, { "r", "rZ", "ri" } },
+    { INDEX_op_deposit_i64, { "r", "rZ", "rZ" } },
 
     { INDEX_op_ext8s_i64, { "r", "rZ"} },
     { INDEX_op_ext8u_i64, { "r", "rZ"} },
diff --git a/tcg/ia64/tcg-target.h b/tcg/ia64/tcg-target.h
index e56e88f..80e3534 100644
--- a/tcg/ia64/tcg-target.h
+++ b/tcg/ia64/tcg-target.h
@@ -131,6 +131,8 @@  enum {
 #define TCG_TARGET_HAS_orc_i64
 #define TCG_TARGET_HAS_rot_i32
 #define TCG_TARGET_HAS_rot_i64
+#define TCG_TARGET_HAS_deposit_i32
+#define TCG_TARGET_HAS_deposit_i64
 
 /* optional instructions automatically implemented */
 #undef TCG_TARGET_HAS_neg_i32   /* sub r1, r0, r3 */