[U-Boot,03/11] Revert "powerpc, 5xxx, 512x: remove support for mpc5xxx and mpc512x"
diff mbox

Message ID e8b0013261f290ff04210e5241e8848378bc4289.1497591422.git.christophe.leroy@c-s.fr
State Changes Requested
Delegated to: Tom Rini
Headers show

Commit Message

Christophe Leroy June 21, 2017, 3:08 p.m. UTC
This reverts commit 064b55cfcb25c0f7692ecf6d4a38f12cd82739f7.

Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
---
 .travis.yml                                        |    6 +
 MAINTAINERS                                        |    6 +
 README                                             |   25 +-
 api/api_platform-powerpc.c                         |    2 +
 arch/powerpc/Kconfig                               |    8 +
 arch/powerpc/cpu/mpc512x/Kconfig                   |   34 +
 arch/powerpc/cpu/mpc512x/Makefile                  |   18 +
 arch/powerpc/cpu/mpc512x/asm-offsets.h             |   15 +
 arch/powerpc/cpu/mpc512x/config.mk                 |    7 +
 arch/powerpc/cpu/mpc512x/cpu.c                     |  193 +++
 arch/powerpc/cpu/mpc512x/cpu_init.c                |  195 +++
 arch/powerpc/cpu/mpc512x/diu.c                     |   44 +
 arch/powerpc/cpu/mpc512x/fixed_sdram.c             |  155 +++
 arch/powerpc/cpu/mpc512x/ide.c                     |  111 ++
 arch/powerpc/cpu/mpc512x/interrupts.c              |   45 +
 arch/powerpc/cpu/mpc512x/iopin.c                   |   87 ++
 arch/powerpc/cpu/mpc512x/pci.c                     |  209 ++++
 arch/powerpc/cpu/mpc512x/serial.c                  |  431 +++++++
 arch/powerpc/cpu/mpc512x/speed.c                   |  137 +++
 arch/powerpc/cpu/mpc512x/start.S                   |  694 +++++++++++
 arch/powerpc/cpu/mpc512x/traps.c                   |  190 +++
 arch/powerpc/cpu/mpc512x/u-boot.lds                |   73 ++
 arch/powerpc/cpu/mpc5xxx/Kconfig                   |   90 ++
 arch/powerpc/cpu/mpc5xxx/Makefile                  |   25 +
 arch/powerpc/cpu/mpc5xxx/config.mk                 |    8 +
 arch/powerpc/cpu/mpc5xxx/cpu.c                     |  168 +++
 arch/powerpc/cpu/mpc5xxx/cpu_init.c                |  231 ++++
 .../cpu/mpc5xxx/firmware_sc_task_bestcomm.impl.S   |  359 ++++++
 arch/powerpc/cpu/mpc5xxx/ide.c                     |   75 ++
 arch/powerpc/cpu/mpc5xxx/interrupts.c              |  330 +++++
 arch/powerpc/cpu/mpc5xxx/io.S                      |  112 ++
 arch/powerpc/cpu/mpc5xxx/loadtask.c                |   76 ++
 arch/powerpc/cpu/mpc5xxx/pci_mpc5200.c             |  157 +++
 arch/powerpc/cpu/mpc5xxx/serial.c                  |  265 ++++
 arch/powerpc/cpu/mpc5xxx/speed.c                   |   84 ++
 arch/powerpc/cpu/mpc5xxx/spl_boot.c                |   76 ++
 arch/powerpc/cpu/mpc5xxx/start.S                   |  780 ++++++++++++
 arch/powerpc/cpu/mpc5xxx/traps.c                   |  220 ++++
 arch/powerpc/cpu/mpc5xxx/u-boot-customlayout.lds   |   80 ++
 arch/powerpc/cpu/mpc5xxx/u-boot-spl.lds            |   44 +
 arch/powerpc/cpu/mpc5xxx/u-boot.lds                |   75 ++
 arch/powerpc/cpu/mpc5xxx/usb.c                     |   42 +
 arch/powerpc/cpu/{ppc4xx => mpc5xxx}/usb_ohci.c    |   32 +-
 .../ohci.h => arch/powerpc/cpu/mpc5xxx/usb_ohci.h  |  150 +--
 arch/powerpc/cpu/ppc4xx/usb_ohci.c                 |    3 +
 arch/powerpc/cpu/ppc4xx/usb_ohci.h                 |    5 +
 arch/powerpc/include/asm/global_data.h             |    7 +
 arch/powerpc/include/asm/immap_512x.h              | 1264 ++++++++++++++++++++
 arch/powerpc/include/asm/mpc512x.h                 |   42 +
 arch/powerpc/include/asm/ppc.h                     |   13 +
 arch/powerpc/lib/Makefile                          |   18 +
 arch/powerpc/lib/bootm.c                           |    4 +
 arch/powerpc/lib/memcpy_mpc5200.c                  |   55 +
 board/a3m071/Kconfig                               |    9 +
 board/a3m071/MAINTAINERS                           |    7 +
 board/a3m071/Makefile                              |    5 +
 board/a3m071/README                                |   80 ++
 board/a3m071/a3m071.c                              |  479 ++++++++
 board/a3m071/is46r16320d.h                         |   24 +
 board/a3m071/mt46v16m16-75.h                       |   21 +
 board/a4m072/Kconfig                               |    9 +
 board/a4m072/MAINTAINERS                           |    6 +
 board/a4m072/Makefile                              |    8 +
 board/a4m072/a4m072.c                              |  479 ++++++++
 board/a4m072/mt46v32m16.h                          |   21 +
 board/canmb/Kconfig                                |    9 +
 board/canmb/MAINTAINERS                            |    6 +
 board/canmb/Makefile                               |    9 +
 board/canmb/canmb.c                                |  187 +++
 board/canmb/mt48lc16m32s2-75.h                     |   14 +
 board/cm5200/Kconfig                               |    9 +
 board/cm5200/MAINTAINERS                           |    6 +
 board/cm5200/Makefile                              |    8 +
 board/cm5200/cm5200.c                              |  355 ++++++
 board/cm5200/cm5200.h                              |  171 +++
 board/cm5200/cmd_cm5200.c                          |  402 +++++++
 board/cm5200/fwupdate.c                            |  181 +++
 board/cm5200/fwupdate.h                            |   31 +
 board/davedenx/aria/Kconfig                        |   12 +
 board/davedenx/aria/MAINTAINERS                    |    6 +
 board/davedenx/aria/Makefile                       |    7 +
 board/davedenx/aria/aria.c                         |  115 ++
 board/esd/mecp5123/Kconfig                         |   12 +
 board/esd/mecp5123/MAINTAINERS                     |    6 +
 board/esd/mecp5123/Makefile                        |    7 +
 board/esd/mecp5123/mecp5123.c                      |  200 ++++
 board/freescale/mpc5121ads/Kconfig                 |   12 +
 board/freescale/mpc5121ads/MAINTAINERS             |    7 +
 board/freescale/mpc5121ads/Makefile                |    8 +
 board/freescale/mpc5121ads/README                  |    7 +
 board/freescale/mpc5121ads/mpc5121ads.c            |  265 ++++
 board/ifm/ac14xx/Kconfig                           |   12 +
 board/ifm/ac14xx/MAINTAINERS                       |    6 +
 board/ifm/ac14xx/Makefile                          |    7 +
 board/ifm/ac14xx/ac14xx.c                          |  569 +++++++++
 board/ifm/o2dnt2/Kconfig                           |   77 ++
 board/ifm/o2dnt2/MAINTAINERS                       |   20 +
 board/ifm/o2dnt2/Makefile                          |    8 +
 board/ifm/o2dnt2/o2dnt2.c                          |  388 ++++++
 board/inka4x0/Kconfig                              |    9 +
 board/inka4x0/MAINTAINERS                          |    6 +
 board/inka4x0/Makefile                             |    8 +
 board/inka4x0/inka4x0.c                            |  254 ++++
 board/inka4x0/inkadiag.c                           |  465 +++++++
 board/inka4x0/k4h511638c.h                         |   16 +
 board/inka4x0/mt46v16m16-75.h                      |   16 +
 board/inka4x0/mt46v32m16-75.h                      |   16 +
 board/inka4x0/mt48lc16m16a2-75.h                   |   14 +
 board/intercontrol/digsy_mtc/Kconfig               |   12 +
 board/intercontrol/digsy_mtc/MAINTAINERS           |    9 +
 board/intercontrol/digsy_mtc/Makefile              |    8 +
 board/intercontrol/digsy_mtc/cmd_disp.c            |   41 +
 board/intercontrol/digsy_mtc/digsy_mtc.c           |  477 ++++++++
 board/intercontrol/digsy_mtc/eeprom.h              |   18 +
 board/intercontrol/digsy_mtc/is42s16800a-7t.h      |   11 +
 board/intercontrol/digsy_mtc/is45s16800a2.h        |   15 +
 board/ipek01/Kconfig                               |    9 +
 board/ipek01/MAINTAINERS                           |    6 +
 board/ipek01/Makefile                              |    8 +
 board/ipek01/ipek01.c                              |  270 +++++
 board/jupiter/Kconfig                              |    9 +
 board/jupiter/MAINTAINERS                          |    6 +
 board/jupiter/Makefile                             |    8 +
 board/jupiter/jupiter.c                            |  296 +++++
 board/motionpro/Kconfig                            |    9 +
 board/motionpro/MAINTAINERS                        |    6 +
 board/motionpro/Makefile                           |    8 +
 board/motionpro/motionpro.c                        |  243 ++++
 board/munices/Kconfig                              |    9 +
 board/munices/MAINTAINERS                          |    6 +
 board/munices/Makefile                             |    8 +
 board/munices/mt48lc16m16a2-75.h                   |   14 +
 board/munices/munices.c                            |  159 +++
 board/pdm360ng/Kconfig                             |    9 +
 board/pdm360ng/MAINTAINERS                         |    6 +
 board/pdm360ng/Makefile                            |    8 +
 board/pdm360ng/pdm360ng.c                          |  581 +++++++++
 board/phytec/pcm030/Kconfig                        |   12 +
 board/phytec/pcm030/MAINTAINERS                    |    7 +
 board/phytec/pcm030/Makefile                       |    8 +
 board/phytec/pcm030/README                         |   42 +
 board/phytec/pcm030/mt46v32m16-75.h                |   21 +
 board/phytec/pcm030/pcm030.c                       |  209 ++++
 board/tqc/tqm5200/Kconfig                          |   25 +
 board/tqc/tqm5200/MAINTAINERS                      |   23 +
 board/tqc/tqm5200/Makefile                         |    8 +
 board/tqc/tqm5200/cam5200_flash.c                  |  768 ++++++++++++
 board/tqc/tqm5200/cmd_stk52xx.c                    | 1228 +++++++++++++++++++
 board/tqc/tqm5200/mt48lc16m16a2-75.h               |   18 +
 board/tqc/tqm5200/tqm5200.c                        |  875 ++++++++++++++
 board/v38b/Kconfig                                 |    9 +
 board/v38b/MAINTAINERS                             |    6 +
 board/v38b/Makefile                                |    8 +
 board/v38b/ethaddr.c                               |  197 +++
 board/v38b/v38b.c                                  |  263 ++++
 cmd/Kconfig                                        |    2 +-
 cmd/reginfo.c                                      |   55 +
 common/Kconfig                                     |    2 +-
 common/board_f.c                                   |    9 +-
 configs/MiniFAP_defconfig                          |   33 +
 configs/O2D300_defconfig                           |   17 +
 configs/O2DNT2_RAMBOOT_defconfig                   |   21 +
 configs/O2DNT2_defconfig                           |   20 +
 configs/O2D_defconfig                              |   17 +
 configs/O2I_defconfig                              |   17 +
 configs/O2MNT_O2M110_defconfig                     |   18 +
 configs/O2MNT_O2M112_defconfig                     |   18 +
 configs/O2MNT_O2M113_defconfig                     |   18 +
 configs/O2MNT_defconfig                            |   17 +
 configs/O3DNT_defconfig                            |   18 +
 configs/TQM5200S_HIGHBOOT_defconfig                |   28 +
 configs/TQM5200S_defconfig                         |   28 +
 configs/TQM5200_B_HIGHBOOT_defconfig               |   33 +
 configs/TQM5200_B_defconfig                        |   33 +
 configs/TQM5200_STK100_defconfig                   |   33 +
 configs/TQM5200_defconfig                          |   32 +
 configs/a3m071_defconfig                           |   32 +
 configs/a4m072_defconfig                           |   25 +
 configs/a4m2k_defconfig                            |   33 +
 configs/ac14xx_defconfig                           |   16 +
 configs/aria_defconfig                             |   16 +
 configs/cam5200_defconfig                          |   23 +
 configs/cam5200_niosflash_defconfig                |   23 +
 configs/canmb_defconfig                            |   14 +
 configs/charon_defconfig                           |   32 +
 configs/cm5200_defconfig                           |   28 +
 configs/digsy_mtc_RAMBOOT_defconfig                |   31 +
 configs/digsy_mtc_defconfig                        |   29 +
 configs/digsy_mtc_rev5_RAMBOOT_defconfig           |   31 +
 configs/digsy_mtc_rev5_defconfig                   |   31 +
 configs/fo300_defconfig                            |   35 +
 configs/inka4x0_defconfig                          |   19 +
 configs/ipek01_defconfig                           |   23 +
 configs/jupiter_defconfig                          |   14 +
 configs/mecp5123_defconfig                         |   19 +
 configs/motionpro_defconfig                        |   33 +
 configs/mpc5121ads_defconfig                       |   25 +
 configs/mpc5121ads_rev2_defconfig                  |   27 +
 configs/munices_defconfig                          |   13 +
 configs/pcm030_LOWBOOT_defconfig                   |   15 +
 configs/pcm030_defconfig                           |   15 +
 configs/pdm360ng_defconfig                         |   23 +
 configs/v38b_defconfig                             |   27 +
 doc/README.generic_usb_ohci                        |    4 +-
 doc/README.scrapyard                               |   21 +
 doc/README.serial_multi                            |   26 +
 drivers/bootcount/bootcount.c                      |   10 +
 drivers/input/keyboard.c                           |    2 +-
 drivers/input/ps2ser.c                             |   94 ++
 drivers/misc/fsl_iim.c                             |    2 +
 drivers/mtd/nand/Kconfig                           |    4 +-
 drivers/mtd/nand/Makefile                          |    1 +
 drivers/mtd/nand/mpc5121_nfc.c                     |  656 ++++++++++
 drivers/net/Makefile                               |    2 +
 drivers/net/mpc512x_fec.c                          |  769 ++++++++++++
 drivers/net/mpc512x_fec.h                          |   98 ++
 drivers/net/mpc5xxx_fec.c                          | 1031 ++++++++++++++++
 drivers/net/mpc5xxx_fec.h                          |  282 +++++
 drivers/rtc/Makefile                               |    1 +
 drivers/rtc/mpc5xxx.c                              |  128 ++
 drivers/serial/serial.c                            |    2 +
 drivers/usb/host/Makefile                          |    4 +
 drivers/usb/host/ehci-mpc512x.c                    |  140 +++
 drivers/usb/host/ohci-hcd.c                        |    5 +
 drivers/usb/host/ohci.h                            |    7 +
 examples/standalone/Makefile                       |    1 +
 examples/standalone/interrupt.c                    |   65 +
 include/asm-generic/u-boot.h                       |    7 +-
 include/configs/TQM5200.h                          |  623 ++++++++++
 include/configs/a3m071.h                           |  408 +++++++
 include/configs/a4m072.h                           |  320 +++++
 include/configs/ac14xx.h                           |  516 ++++++++
 include/configs/aria.h                             |  589 +++++++++
 include/configs/canmb.h                            |  199 +++
 include/configs/charon.h                           |   63 +
 include/configs/cm5200.h                           |  286 +++++
 include/configs/digsy_mtc.h                        |  410 +++++++
 include/configs/inka4x0.h                          |  306 +++++
 include/configs/ipek01.h                           |  321 +++++
 include/configs/jupiter.h                          |  246 ++++
 include/configs/manroland/mpc5200-common.h         |  173 +++
 include/configs/mecp5123.h                         |  398 ++++++
 include/configs/motionpro.h                        |  329 +++++
 include/configs/mpc5121-common.h                   |   32 +
 include/configs/mpc5121ads.h                       |  578 +++++++++
 include/configs/munices.h                          |  186 +++
 include/configs/o2d.h                              |   74 ++
 include/configs/o2d300.h                           |   81 ++
 include/configs/o2dnt-common.h                     |  300 +++++
 include/configs/o2dnt2.h                           |   66 +
 include/configs/o2i.h                              |   66 +
 include/configs/o2mnt.h                            |   74 ++
 include/configs/o3dnt.h                            |   69 ++
 include/configs/pcm030.h                           |  376 ++++++
 include/configs/pdm360ng.h                         |  420 +++++++
 include/configs/v38b.h                             |  282 +++++
 include/keyboard.h                                 |    2 +-
 include/mpc5xxx.h                                  |  893 ++++++++++++++
 include/mpc5xxx_sdma.h                             |   93 ++
 include/netdev.h                                   |    2 +
 include/post.h                                     |    9 +-
 include/ppc_asm.tmpl                               |    7 +
 include/serial.h                                   |   11 +-
 include/status_led.h                               |    4 +
 include/usb/ehci-ci.h                              |    3 +
 include/watchdog.h                                 |    5 +
 post/board/pdm360ng/Makefile                       |    8 +
 post/board/pdm360ng/coproc_com.c                   |   78 ++
 scripts/config_whitelist.txt                       |  205 ++++
 269 files changed, 32157 insertions(+), 99 deletions(-)
 create mode 100644 arch/powerpc/cpu/mpc512x/Kconfig
 create mode 100644 arch/powerpc/cpu/mpc512x/Makefile
 create mode 100644 arch/powerpc/cpu/mpc512x/asm-offsets.h
 create mode 100644 arch/powerpc/cpu/mpc512x/config.mk
 create mode 100644 arch/powerpc/cpu/mpc512x/cpu.c
 create mode 100644 arch/powerpc/cpu/mpc512x/cpu_init.c
 create mode 100644 arch/powerpc/cpu/mpc512x/diu.c
 create mode 100644 arch/powerpc/cpu/mpc512x/fixed_sdram.c
 create mode 100644 arch/powerpc/cpu/mpc512x/ide.c
 create mode 100644 arch/powerpc/cpu/mpc512x/interrupts.c
 create mode 100644 arch/powerpc/cpu/mpc512x/iopin.c
 create mode 100644 arch/powerpc/cpu/mpc512x/pci.c
 create mode 100644 arch/powerpc/cpu/mpc512x/serial.c
 create mode 100644 arch/powerpc/cpu/mpc512x/speed.c
 create mode 100644 arch/powerpc/cpu/mpc512x/start.S
 create mode 100644 arch/powerpc/cpu/mpc512x/traps.c
 create mode 100644 arch/powerpc/cpu/mpc512x/u-boot.lds
 create mode 100644 arch/powerpc/cpu/mpc5xxx/Kconfig
 create mode 100644 arch/powerpc/cpu/mpc5xxx/Makefile
 create mode 100644 arch/powerpc/cpu/mpc5xxx/config.mk
 create mode 100644 arch/powerpc/cpu/mpc5xxx/cpu.c
 create mode 100644 arch/powerpc/cpu/mpc5xxx/cpu_init.c
 create mode 100644 arch/powerpc/cpu/mpc5xxx/firmware_sc_task_bestcomm.impl.S
 create mode 100644 arch/powerpc/cpu/mpc5xxx/ide.c
 create mode 100644 arch/powerpc/cpu/mpc5xxx/interrupts.c
 create mode 100644 arch/powerpc/cpu/mpc5xxx/io.S
 create mode 100644 arch/powerpc/cpu/mpc5xxx/loadtask.c
 create mode 100644 arch/powerpc/cpu/mpc5xxx/pci_mpc5200.c
 create mode 100644 arch/powerpc/cpu/mpc5xxx/serial.c
 create mode 100644 arch/powerpc/cpu/mpc5xxx/speed.c
 create mode 100644 arch/powerpc/cpu/mpc5xxx/spl_boot.c
 create mode 100644 arch/powerpc/cpu/mpc5xxx/start.S
 create mode 100644 arch/powerpc/cpu/mpc5xxx/traps.c
 create mode 100644 arch/powerpc/cpu/mpc5xxx/u-boot-customlayout.lds
 create mode 100644 arch/powerpc/cpu/mpc5xxx/u-boot-spl.lds
 create mode 100644 arch/powerpc/cpu/mpc5xxx/u-boot.lds
 create mode 100644 arch/powerpc/cpu/mpc5xxx/usb.c
 copy arch/powerpc/cpu/{ppc4xx => mpc5xxx}/usb_ohci.c (98%)
 copy drivers/usb/host/ohci.h => arch/powerpc/cpu/mpc5xxx/usb_ohci.h (82%)
 create mode 100644 arch/powerpc/include/asm/immap_512x.h
 create mode 100644 arch/powerpc/include/asm/mpc512x.h
 create mode 100644 arch/powerpc/lib/memcpy_mpc5200.c
 create mode 100644 board/a3m071/Kconfig
 create mode 100644 board/a3m071/MAINTAINERS
 create mode 100644 board/a3m071/Makefile
 create mode 100644 board/a3m071/README
 create mode 100644 board/a3m071/a3m071.c
 create mode 100644 board/a3m071/is46r16320d.h
 create mode 100644 board/a3m071/mt46v16m16-75.h
 create mode 100644 board/a4m072/Kconfig
 create mode 100644 board/a4m072/MAINTAINERS
 create mode 100644 board/a4m072/Makefile
 create mode 100644 board/a4m072/a4m072.c
 create mode 100644 board/a4m072/mt46v32m16.h
 create mode 100644 board/canmb/Kconfig
 create mode 100644 board/canmb/MAINTAINERS
 create mode 100644 board/canmb/Makefile
 create mode 100644 board/canmb/canmb.c
 create mode 100644 board/canmb/mt48lc16m32s2-75.h
 create mode 100644 board/cm5200/Kconfig
 create mode 100644 board/cm5200/MAINTAINERS
 create mode 100644 board/cm5200/Makefile
 create mode 100644 board/cm5200/cm5200.c
 create mode 100644 board/cm5200/cm5200.h
 create mode 100644 board/cm5200/cmd_cm5200.c
 create mode 100644 board/cm5200/fwupdate.c
 create mode 100644 board/cm5200/fwupdate.h
 create mode 100644 board/davedenx/aria/Kconfig
 create mode 100644 board/davedenx/aria/MAINTAINERS
 create mode 100644 board/davedenx/aria/Makefile
 create mode 100644 board/davedenx/aria/aria.c
 create mode 100644 board/esd/mecp5123/Kconfig
 create mode 100644 board/esd/mecp5123/MAINTAINERS
 create mode 100644 board/esd/mecp5123/Makefile
 create mode 100644 board/esd/mecp5123/mecp5123.c
 create mode 100644 board/freescale/mpc5121ads/Kconfig
 create mode 100644 board/freescale/mpc5121ads/MAINTAINERS
 create mode 100644 board/freescale/mpc5121ads/Makefile
 create mode 100644 board/freescale/mpc5121ads/README
 create mode 100644 board/freescale/mpc5121ads/mpc5121ads.c
 create mode 100644 board/ifm/ac14xx/Kconfig
 create mode 100644 board/ifm/ac14xx/MAINTAINERS
 create mode 100644 board/ifm/ac14xx/Makefile
 create mode 100644 board/ifm/ac14xx/ac14xx.c
 create mode 100644 board/ifm/o2dnt2/Kconfig
 create mode 100644 board/ifm/o2dnt2/MAINTAINERS
 create mode 100644 board/ifm/o2dnt2/Makefile
 create mode 100644 board/ifm/o2dnt2/o2dnt2.c
 create mode 100644 board/inka4x0/Kconfig
 create mode 100644 board/inka4x0/MAINTAINERS
 create mode 100644 board/inka4x0/Makefile
 create mode 100644 board/inka4x0/inka4x0.c
 create mode 100644 board/inka4x0/inkadiag.c
 create mode 100644 board/inka4x0/k4h511638c.h
 create mode 100644 board/inka4x0/mt46v16m16-75.h
 create mode 100644 board/inka4x0/mt46v32m16-75.h
 create mode 100644 board/inka4x0/mt48lc16m16a2-75.h
 create mode 100644 board/intercontrol/digsy_mtc/Kconfig
 create mode 100644 board/intercontrol/digsy_mtc/MAINTAINERS
 create mode 100644 board/intercontrol/digsy_mtc/Makefile
 create mode 100644 board/intercontrol/digsy_mtc/cmd_disp.c
 create mode 100644 board/intercontrol/digsy_mtc/digsy_mtc.c
 create mode 100644 board/intercontrol/digsy_mtc/eeprom.h
 create mode 100644 board/intercontrol/digsy_mtc/is42s16800a-7t.h
 create mode 100644 board/intercontrol/digsy_mtc/is45s16800a2.h
 create mode 100644 board/ipek01/Kconfig
 create mode 100644 board/ipek01/MAINTAINERS
 create mode 100644 board/ipek01/Makefile
 create mode 100644 board/ipek01/ipek01.c
 create mode 100644 board/jupiter/Kconfig
 create mode 100644 board/jupiter/MAINTAINERS
 create mode 100644 board/jupiter/Makefile
 create mode 100644 board/jupiter/jupiter.c
 create mode 100644 board/motionpro/Kconfig
 create mode 100644 board/motionpro/MAINTAINERS
 create mode 100644 board/motionpro/Makefile
 create mode 100644 board/motionpro/motionpro.c
 create mode 100644 board/munices/Kconfig
 create mode 100644 board/munices/MAINTAINERS
 create mode 100644 board/munices/Makefile
 create mode 100644 board/munices/mt48lc16m16a2-75.h
 create mode 100644 board/munices/munices.c
 create mode 100644 board/pdm360ng/Kconfig
 create mode 100644 board/pdm360ng/MAINTAINERS
 create mode 100644 board/pdm360ng/Makefile
 create mode 100644 board/pdm360ng/pdm360ng.c
 create mode 100644 board/phytec/pcm030/Kconfig
 create mode 100644 board/phytec/pcm030/MAINTAINERS
 create mode 100644 board/phytec/pcm030/Makefile
 create mode 100644 board/phytec/pcm030/README
 create mode 100644 board/phytec/pcm030/mt46v32m16-75.h
 create mode 100644 board/phytec/pcm030/pcm030.c
 create mode 100644 board/tqc/tqm5200/Kconfig
 create mode 100644 board/tqc/tqm5200/MAINTAINERS
 create mode 100644 board/tqc/tqm5200/Makefile
 create mode 100644 board/tqc/tqm5200/cam5200_flash.c
 create mode 100644 board/tqc/tqm5200/cmd_stk52xx.c
 create mode 100644 board/tqc/tqm5200/mt48lc16m16a2-75.h
 create mode 100644 board/tqc/tqm5200/tqm5200.c
 create mode 100644 board/v38b/Kconfig
 create mode 100644 board/v38b/MAINTAINERS
 create mode 100644 board/v38b/Makefile
 create mode 100644 board/v38b/ethaddr.c
 create mode 100644 board/v38b/v38b.c
 create mode 100644 configs/MiniFAP_defconfig
 create mode 100644 configs/O2D300_defconfig
 create mode 100644 configs/O2DNT2_RAMBOOT_defconfig
 create mode 100644 configs/O2DNT2_defconfig
 create mode 100644 configs/O2D_defconfig
 create mode 100644 configs/O2I_defconfig
 create mode 100644 configs/O2MNT_O2M110_defconfig
 create mode 100644 configs/O2MNT_O2M112_defconfig
 create mode 100644 configs/O2MNT_O2M113_defconfig
 create mode 100644 configs/O2MNT_defconfig
 create mode 100644 configs/O3DNT_defconfig
 create mode 100644 configs/TQM5200S_HIGHBOOT_defconfig
 create mode 100644 configs/TQM5200S_defconfig
 create mode 100644 configs/TQM5200_B_HIGHBOOT_defconfig
 create mode 100644 configs/TQM5200_B_defconfig
 create mode 100644 configs/TQM5200_STK100_defconfig
 create mode 100644 configs/TQM5200_defconfig
 create mode 100644 configs/a3m071_defconfig
 create mode 100644 configs/a4m072_defconfig
 create mode 100644 configs/a4m2k_defconfig
 create mode 100644 configs/ac14xx_defconfig
 create mode 100644 configs/aria_defconfig
 create mode 100644 configs/cam5200_defconfig
 create mode 100644 configs/cam5200_niosflash_defconfig
 create mode 100644 configs/canmb_defconfig
 create mode 100644 configs/charon_defconfig
 create mode 100644 configs/cm5200_defconfig
 create mode 100644 configs/digsy_mtc_RAMBOOT_defconfig
 create mode 100644 configs/digsy_mtc_defconfig
 create mode 100644 configs/digsy_mtc_rev5_RAMBOOT_defconfig
 create mode 100644 configs/digsy_mtc_rev5_defconfig
 create mode 100644 configs/fo300_defconfig
 create mode 100644 configs/inka4x0_defconfig
 create mode 100644 configs/ipek01_defconfig
 create mode 100644 configs/jupiter_defconfig
 create mode 100644 configs/mecp5123_defconfig
 create mode 100644 configs/motionpro_defconfig
 create mode 100644 configs/mpc5121ads_defconfig
 create mode 100644 configs/mpc5121ads_rev2_defconfig
 create mode 100644 configs/munices_defconfig
 create mode 100644 configs/pcm030_LOWBOOT_defconfig
 create mode 100644 configs/pcm030_defconfig
 create mode 100644 configs/pdm360ng_defconfig
 create mode 100644 configs/v38b_defconfig
 create mode 100644 drivers/mtd/nand/mpc5121_nfc.c
 create mode 100644 drivers/net/mpc512x_fec.c
 create mode 100644 drivers/net/mpc512x_fec.h
 create mode 100644 drivers/net/mpc5xxx_fec.c
 create mode 100644 drivers/net/mpc5xxx_fec.h
 create mode 100644 drivers/rtc/mpc5xxx.c
 create mode 100644 drivers/usb/host/ehci-mpc512x.c
 create mode 100644 examples/standalone/interrupt.c
 create mode 100644 include/configs/TQM5200.h
 create mode 100644 include/configs/a3m071.h
 create mode 100644 include/configs/a4m072.h
 create mode 100644 include/configs/ac14xx.h
 create mode 100644 include/configs/aria.h
 create mode 100644 include/configs/canmb.h
 create mode 100644 include/configs/charon.h
 create mode 100644 include/configs/cm5200.h
 create mode 100644 include/configs/digsy_mtc.h
 create mode 100644 include/configs/inka4x0.h
 create mode 100644 include/configs/ipek01.h
 create mode 100644 include/configs/jupiter.h
 create mode 100644 include/configs/manroland/mpc5200-common.h
 create mode 100644 include/configs/mecp5123.h
 create mode 100644 include/configs/motionpro.h
 create mode 100644 include/configs/mpc5121-common.h
 create mode 100644 include/configs/mpc5121ads.h
 create mode 100644 include/configs/munices.h
 create mode 100644 include/configs/o2d.h
 create mode 100644 include/configs/o2d300.h
 create mode 100644 include/configs/o2dnt-common.h
 create mode 100644 include/configs/o2dnt2.h
 create mode 100644 include/configs/o2i.h
 create mode 100644 include/configs/o2mnt.h
 create mode 100644 include/configs/o3dnt.h
 create mode 100644 include/configs/pcm030.h
 create mode 100644 include/configs/pdm360ng.h
 create mode 100644 include/configs/v38b.h
 create mode 100644 include/mpc5xxx.h
 create mode 100644 include/mpc5xxx_sdma.h
 create mode 100644 post/board/pdm360ng/Makefile
 create mode 100644 post/board/pdm360ng/coproc_com.c

Patch
diff mbox

diff --git a/.travis.yml b/.travis.yml
index a534743911..3105a6fc73 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -194,6 +194,12 @@  matrix:
         - BUILDMAN="mips"
           TOOLCHAIN="mips"
     - env:
+        - BUILDMAN="mpc512x"
+    - env:
+        - BUILDMAN="mpc5xx"
+    - env:
+        - BUILDMAN="mpc5xxx"
+    - env:
         - BUILDMAN="mpc83xx"
     - env:
         - BUILDMAN="mpc85xx -x freescale"
diff --git a/MAINTAINERS b/MAINTAINERS
index 2c0b8aa18f..3c7438dd1e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -321,6 +321,12 @@  M:	Wolfgang Denk <wd@denx.de>
 S:	Maintained
 F:	arch/powerpc/
 
+POWERPC MPC5XXX
+M:	Wolfgang Denk <wd@denx.de>
+S:	Maintained
+T:	git git://git.denx.de/u-boot-mpc5xxx.git
+F:	arch/powerpc/cpu/mpc5*/
+
 POWERPC MPC8XX
 M:	Wolfgang Denk <wd@denx.de>
 S:	Maintained
diff --git a/README b/README
index 27a075abbb..0833c41d48 100644
--- a/README
+++ b/README
@@ -608,6 +608,10 @@  The following options need to be configured:
 		 * Adds the "fdt" command
 		 * The bootm command automatically updates the fdt
 
+		OF_CPU - The proper name of the cpus node (only required for
+			MPC512X and MPC5xxx based boards).
+		OF_SOC - The proper name of the soc node (only required for
+			MPC512X and MPC5xxx based boards).
 		OF_TBCLK - The timebase frequency.
 		OF_STDOUT_PATH - The path to the console device
 
@@ -1228,7 +1232,7 @@  The following options need to be configured:
 
 - USB Support:
 		At the moment only the UHCI host controller is
-		supported (PIP405, MIP405); define
+		supported (PIP405, MIP405, MPC5200); define
 		CONFIG_USB_UHCI to enable it.
 		define CONFIG_USB_KEYBOARD to enable the USB Keyboard
 		and define CONFIG_USB_STORAGE to enable the USB
@@ -1236,6 +1240,19 @@  The following options need to be configured:
 		Note:
 		Supported are USB Keyboards and USB Floppy drives
 		(TEAC FD-05PUB).
+		MPC5200 USB requires additional defines:
+			CONFIG_USB_CLOCK
+				for 528 MHz Clock: 0x0001bbbb
+			CONFIG_PSC3_USB
+				for USB on PSC3
+			CONFIG_USB_CONFIG
+				for differential drivers: 0x00001000
+				for single ended drivers: 0x00005000
+				for differential drivers on PSC3: 0x00000100
+				for single ended drivers on PSC3: 0x00004100
+			CONFIG_SYS_USB_EVENT_POLL
+				May be defined to allow interrupt polling
+				instead of using asynchronous interrupts
 
 		CONFIG_USB_EHCI_TXFIFO_THRESH enables setting of the
 		txfilltuning field in the EHCI controller on reset.
@@ -1877,6 +1894,12 @@  The following options need to be configured:
 		In such cases CONFIG_GPIO_LED_INVERTED_TABLE may be defined
 		with a list of GPIO LEDs that have inverted polarity.
 
+- CAN Support:	CONFIG_CAN_DRIVER
+
+		Defining CONFIG_CAN_DRIVER enables CAN driver support
+		on those systems that support this (optional)
+		feature.
+
 - I2C Support:	CONFIG_SYS_I2C
 
 		This enable the NEW i2c subsystem, and will allow you to use
diff --git a/api/api_platform-powerpc.c b/api/api_platform-powerpc.c
index d1b54ea4e1..7d54ea7978 100644
--- a/api/api_platform-powerpc.c
+++ b/api/api_platform-powerpc.c
@@ -32,6 +32,8 @@  int platform_sys_info(struct sys_info *si)
 
 #if defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
 #define bi_bar	bi_immr_base
+#elif defined(CONFIG_MPC5xxx)
+#define bi_bar	bi_mbar_base
 #elif defined(CONFIG_MPC83xx)
 #define bi_bar	bi_immrbar
 #endif
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index d030610105..c0345acbf2 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -8,6 +8,12 @@  choice
 	prompt "CPU select"
 	optional
 
+config MPC512X
+	bool "MPC512X"
+
+config MPC5xxx
+	bool "MPC5xxx"
+
 config MPC83xx
 	bool "MPC83xx"
 	select CREATE_ARCH_SYMLINK
@@ -36,6 +42,8 @@  config 4xx
 
 endchoice
 
+source "arch/powerpc/cpu/mpc512x/Kconfig"
+source "arch/powerpc/cpu/mpc5xxx/Kconfig"
 source "arch/powerpc/cpu/mpc83xx/Kconfig"
 source "arch/powerpc/cpu/mpc85xx/Kconfig"
 source "arch/powerpc/cpu/mpc86xx/Kconfig"
diff --git a/arch/powerpc/cpu/mpc512x/Kconfig b/arch/powerpc/cpu/mpc512x/Kconfig
new file mode 100644
index 0000000000..53450aeaba
--- /dev/null
+++ b/arch/powerpc/cpu/mpc512x/Kconfig
@@ -0,0 +1,34 @@ 
+menu "mpc512x CPU"
+	depends on MPC512X
+
+config SYS_CPU
+	default "mpc512x"
+
+choice
+	prompt "Target select"
+	optional
+
+config TARGET_PDM360NG
+	bool "Support pdm360ng"
+
+config TARGET_ARIA
+	bool "Support aria"
+
+config TARGET_MECP5123
+	bool "Support mecp5123"
+
+config TARGET_MPC5121ADS
+	bool "Support mpc5121ads"
+
+config TARGET_AC14XX
+	bool "Support ac14xx"
+
+endchoice
+
+source "board/davedenx/aria/Kconfig"
+source "board/esd/mecp5123/Kconfig"
+source "board/freescale/mpc5121ads/Kconfig"
+source "board/ifm/ac14xx/Kconfig"
+source "board/pdm360ng/Kconfig"
+
+endmenu
diff --git a/arch/powerpc/cpu/mpc512x/Makefile b/arch/powerpc/cpu/mpc512x/Makefile
new file mode 100644
index 0000000000..933deebdae
--- /dev/null
+++ b/arch/powerpc/cpu/mpc512x/Makefile
@@ -0,0 +1,18 @@ 
+#
+# (C) Copyright 2007-2009 DENX Software Engineering
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+extra-y	= start.o
+obj-y	:= cpu.o
+obj-y	+= traps.o
+obj-y += cpu_init.o
+obj-y += fixed_sdram.o
+obj-y += interrupts.o
+obj-y += iopin.o
+obj-y += serial.o
+obj-y += speed.o
+obj-$(CONFIG_FSL_DIU_FB) += diu.o
+obj-$(CONFIG_CMD_IDE) += ide.o
+obj-$(CONFIG_PCI) += pci.o
diff --git a/arch/powerpc/cpu/mpc512x/asm-offsets.h b/arch/powerpc/cpu/mpc512x/asm-offsets.h
new file mode 100644
index 0000000000..957d4be2d2
--- /dev/null
+++ b/arch/powerpc/cpu/mpc512x/asm-offsets.h
@@ -0,0 +1,15 @@ 
+/*
+ * needed for arch/powerpc/cpu/mpc512x/start.S
+ *
+ * These should be auto-generated
+ */
+#define LPCS0AW			0x0024
+#define SRAMBAR			0x00C4
+#define SWCRR			0x0904
+#define LPC_OFFSET		0x10000
+#define CS0_CONFIG		0x00000
+#define CS_CTRL			0x00020
+#define CS_CTRL_ME		0x01000000	/* CS Master Enable bit */
+
+#define EXC_OFF_SYS_RESET	0x0100
+#define	_START_OFFSET		EXC_OFF_SYS_RESET
diff --git a/arch/powerpc/cpu/mpc512x/config.mk b/arch/powerpc/cpu/mpc512x/config.mk
new file mode 100644
index 0000000000..5bf1b2a3b9
--- /dev/null
+++ b/arch/powerpc/cpu/mpc512x/config.mk
@@ -0,0 +1,7 @@ 
+#
+# (C) Copyright 2007-2010 DENX Software Engineering
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+PLATFORM_CPPFLAGS += -DCONFIG_E300 -msoft-float -mcpu=603e
diff --git a/arch/powerpc/cpu/mpc512x/cpu.c b/arch/powerpc/cpu/mpc512x/cpu.c
new file mode 100644
index 0000000000..ce524fcdc7
--- /dev/null
+++ b/arch/powerpc/cpu/mpc512x/cpu.c
@@ -0,0 +1,193 @@ 
+/*
+ * (C) Copyright 2007-2010 DENX Software Engineering
+ * Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * CPU specific code for the MPC512x family.
+ *
+ * Derived from the MPC83xx code.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <net.h>
+#include <netdev.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+
+#if defined(CONFIG_OF_LIBFDT)
+#include <fdt_support.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkcpu (void)
+{
+	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
+	ulong clock = gd->cpu_clk;
+	u32 pvr = get_pvr ();
+	u32 spridr = in_be32(&immr->sysconf.spridr);
+	char buf1[32], buf2[32];
+
+	puts ("CPU:   ");
+
+	switch (spridr & 0xffff0000) {
+	case SPR_5121E:
+		puts ("MPC5121e ");
+		break;
+	default:
+		printf ("Unknown part ID %08x ", spridr & 0xffff0000);
+	}
+	printf ("rev. %d.%d, Core ", SVR_MJREV (spridr), SVR_MNREV (spridr));
+
+	switch (pvr & 0xffff0000) {
+	case PVR_E300C4:
+		puts ("e300c4 ");
+		break;
+	default:
+		puts ("unknown ");
+	}
+	printf ("at %s MHz, CSB at %s MHz (RSR=0x%04lx)\n",
+		strmhz(buf1, clock),
+		strmhz(buf2, gd->arch.csb_clk),
+		gd->arch.reset_status & 0xffff);
+	return 0;
+}
+
+
+int
+do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+{
+	ulong msr;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+
+	/* Interrupts and MMU off */
+	__asm__ __volatile__ ("mfmsr    %0":"=r" (msr):);
+
+	msr &= ~( MSR_EE | MSR_IR | MSR_DR);
+	__asm__ __volatile__ ("mtmsr    %0"::"r" (msr));
+
+	/*
+	 * Enable Reset Control Reg - "RSTE" is the magic word that let us go
+	 */
+	out_be32(&immap->reset.rpr, 0x52535445);
+
+	/* Verify Reset Control Reg is enabled */
+	while (!(in_be32(&immap->reset.rcer) & RCER_CRE))
+		;
+
+	printf ("Resetting the board.\n");
+	udelay(200);
+
+	/* Perform reset */
+	out_be32(&immap->reset.rcr, RCR_SWHR);
+
+	/* Unreached... */
+	return 1;
+}
+
+
+/*
+ * Get timebase clock frequency (like cpu_clk in Hz)
+ */
+unsigned long get_tbclk (void)
+{
+	return (gd->bus_clk + 3L) / 4L;
+}
+
+
+#if defined(CONFIG_WATCHDOG)
+void watchdog_reset (void)
+{
+	int re_enable = disable_interrupts ();
+
+	/* Reset watchdog */
+	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
+	out_be32(&immr->wdt.swsrr, 0x556c);
+	out_be32(&immr->wdt.swsrr, 0xaa39);
+
+	if (re_enable)
+		enable_interrupts ();
+}
+#endif
+
+#ifdef CONFIG_OF_LIBFDT
+
+#ifdef CONFIG_OF_SUPPORT_OLD_DEVICE_TREES
+/*
+ * fdt setup for old device trees
+ * fix up
+ * 	cpu clocks
+ * 	soc clocks
+ * 	ethernet addresses
+ */
+static void old_ft_cpu_setup(void *blob, bd_t *bd)
+{
+	/*
+	 * avoid fixing up by path because that
+	 * produces scary error messages
+	 */
+	uchar enetaddr[6];
+
+	/*
+	 * old device trees have ethernet nodes with
+	 * device_type = "network"
+	 */
+	eth_getenv_enetaddr("ethaddr", enetaddr);
+	do_fixup_by_prop(blob, "device_type", "network", 8,
+		"local-mac-address", enetaddr, 6, 0);
+	do_fixup_by_prop(blob, "device_type", "network", 8,
+		"address", enetaddr, 6, 0);
+	/*
+	 * old device trees have soc nodes with
+	 * device_type = "soc"
+	 */
+	do_fixup_by_prop_u32(blob, "device_type", "soc", 4,
+		"bus-frequency", bd->bi_ipsfreq, 0);
+}
+#endif
+
+static void ft_clock_setup(void *blob, bd_t *bd)
+{
+	char *cpu_path = "/cpus/" OF_CPU;
+
+	/*
+	 * fixup cpu clocks using path
+	 */
+	do_fixup_by_path_u32(blob, cpu_path,
+		"timebase-frequency", OF_TBCLK, 1);
+	do_fixup_by_path_u32(blob, cpu_path,
+		"bus-frequency", bd->bi_busfreq, 1);
+	do_fixup_by_path_u32(blob, cpu_path,
+		"clock-frequency", bd->bi_intfreq, 1);
+	/*
+	 * fixup soc clocks using compatible
+	 */
+	do_fixup_by_compat_u32(blob, OF_SOC_COMPAT,
+		"bus-frequency", bd->bi_ipsfreq, 1);
+}
+
+void ft_cpu_setup(void *blob, bd_t *bd)
+{
+#ifdef CONFIG_OF_SUPPORT_OLD_DEVICE_TREES
+	old_ft_cpu_setup(blob, bd);
+#endif
+	ft_clock_setup(blob, bd);
+	fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
+}
+#endif
+
+#ifdef CONFIG_MPC512x_FEC
+/* Default initializations for FEC controllers.  To override,
+ * create a board-specific function called:
+ * 	int board_eth_init(bd_t *bis)
+ */
+
+int cpu_eth_init(bd_t *bis)
+{
+	return mpc512x_fec_initialize(bis);
+}
+#endif
diff --git a/arch/powerpc/cpu/mpc512x/cpu_init.c b/arch/powerpc/cpu/mpc512x/cpu_init.c
new file mode 100644
index 0000000000..48a5e4f8b2
--- /dev/null
+++ b/arch/powerpc/cpu/mpc512x/cpu_init.c
@@ -0,0 +1,195 @@ 
+/*
+ * Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
+ * Copyright (C) 2007-2009 DENX Software Engineering
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Derived from the MPC83xx code.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/mpc512x.h>
+#include <asm/processor.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Set up the memory map, initialize registers,
+ */
+void cpu_init_f (volatile immap_t * im)
+{
+	u32 ips_div;
+
+	/* Pointer is writable since we allocated a register for it */
+	gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
+
+	/* Clear initial global data */
+	memset ((void *) gd, 0, sizeof (gd_t));
+
+	/* Local Window and chip select configuration */
+#if defined(CONFIG_SYS_CS0_START) && defined(CONFIG_SYS_CS0_SIZE)
+	out_be32(&im->sysconf.lpcs0aw,
+		CSAW_START(CONFIG_SYS_CS0_START) |
+		CSAW_STOP(CONFIG_SYS_CS0_START, CONFIG_SYS_CS0_SIZE));
+	sync_law(&im->sysconf.lpcs0aw);
+#endif
+#if defined(CONFIG_SYS_CS0_CFG)
+	out_be32(&im->lpc.cs_cfg[0], CONFIG_SYS_CS0_CFG);
+#endif
+
+#if defined(CONFIG_SYS_CS1_START) && defined(CONFIG_SYS_CS1_SIZE)
+	out_be32(&im->sysconf.lpcs1aw,
+		CSAW_START(CONFIG_SYS_CS1_START) |
+		CSAW_STOP(CONFIG_SYS_CS1_START, CONFIG_SYS_CS1_SIZE));
+	sync_law(&im->sysconf.lpcs1aw);
+#endif
+#if defined(CONFIG_SYS_CS1_CFG)
+	out_be32(&im->lpc.cs_cfg[1], CONFIG_SYS_CS1_CFG);
+#endif
+
+#if defined(CONFIG_SYS_CS2_START) && (defined CONFIG_SYS_CS2_SIZE)
+	out_be32(&im->sysconf.lpcs2aw,
+		CSAW_START(CONFIG_SYS_CS2_START) |
+		CSAW_STOP(CONFIG_SYS_CS2_START, CONFIG_SYS_CS2_SIZE));
+	sync_law(&im->sysconf.lpcs2aw);
+#endif
+#if defined(CONFIG_SYS_CS2_CFG)
+	out_be32(&im->lpc.cs_cfg[2], CONFIG_SYS_CS2_CFG);
+#endif
+
+#if defined(CONFIG_SYS_CS3_START) && defined(CONFIG_SYS_CS3_SIZE)
+	out_be32(&im->sysconf.lpcs3aw,
+		CSAW_START(CONFIG_SYS_CS3_START) |
+		CSAW_STOP(CONFIG_SYS_CS3_START, CONFIG_SYS_CS3_SIZE));
+	sync_law(&im->sysconf.lpcs3aw);
+#endif
+#if defined(CONFIG_SYS_CS3_CFG)
+	out_be32(&im->lpc.cs_cfg[3], CONFIG_SYS_CS3_CFG);
+#endif
+
+#if defined(CONFIG_SYS_CS4_START) && defined(CONFIG_SYS_CS4_SIZE)
+	out_be32(&im->sysconf.lpcs4aw,
+		CSAW_START(CONFIG_SYS_CS4_START) |
+		CSAW_STOP(CONFIG_SYS_CS4_START, CONFIG_SYS_CS4_SIZE));
+	sync_law(&im->sysconf.lpcs4aw);
+#endif
+#if defined(CONFIG_SYS_CS4_CFG)
+	out_be32(&im->lpc.cs_cfg[4], CONFIG_SYS_CS4_CFG);
+#endif
+
+#if defined(CONFIG_SYS_CS5_START) && defined(CONFIG_SYS_CS5_SIZE)
+	out_be32(&im->sysconf.lpcs5aw,
+		CSAW_START(CONFIG_SYS_CS5_START) |
+		CSAW_STOP(CONFIG_SYS_CS5_START, CONFIG_SYS_CS5_SIZE));
+	sync_law(&im->sysconf.lpcs5aw);
+#endif
+#if defined(CONFIG_SYS_CS5_CFG)
+	out_be32(&im->lpc.cs_cfg[5], CONFIG_SYS_CS5_CFG);
+#endif
+
+#if defined(CONFIG_SYS_CS6_START) && defined(CONFIG_SYS_CS6_SIZE)
+	out_be32(&im->sysconf.lpcs6aw,
+		CSAW_START(CONFIG_SYS_CS6_START) |
+		CSAW_STOP(CONFIG_SYS_CS6_START, CONFIG_SYS_CS6_SIZE));
+	sync_law(&im->sysconf.lpcs6aw);
+#endif
+#if defined(CONFIG_SYS_CS6_CFG)
+	out_be32(&im->lpc.cs_cfg[6], CONFIG_SYS_CS6_CFG);
+#endif
+
+#if defined(CONFIG_SYS_CS7_START) && defined(CONFIG_SYS_CS7_SIZE)
+	out_be32(&im->sysconf.lpcs7aw,
+		CSAW_START(CONFIG_SYS_CS7_START) |
+		CSAW_STOP(CONFIG_SYS_CS7_START, CONFIG_SYS_CS7_SIZE));
+	sync_law(&im->sysconf.lpcs7aw);
+#endif
+#if defined(CONFIG_SYS_CS7_CFG)
+	out_be32(&im->lpc.cs_cfg[7], CONFIG_SYS_CS7_CFG);
+#endif
+
+#if defined CONFIG_SYS_CS_ALETIMING
+	if (SVR_MJREV(in_be32(&im->sysconf.spridr)) >= 2)
+		out_be32(&im->lpc.altr, CONFIG_SYS_CS_ALETIMING);
+#endif
+#if defined CONFIG_SYS_CS_BURST
+	out_be32(&im->lpc.cs_bcr, CONFIG_SYS_CS_BURST);
+#endif
+#if defined CONFIG_SYS_CS_DEADCYCLE
+	out_be32(&im->lpc.cs_dccr, CONFIG_SYS_CS_DEADCYCLE);
+#endif
+#if defined CONFIG_SYS_CS_HOLDCYCLE
+	out_be32(&im->lpc.cs_hccr, CONFIG_SYS_CS_HOLDCYCLE);
+#endif
+
+	/* system performance tweaking */
+
+#ifdef CONFIG_SYS_ACR_PIPE_DEP
+	/* Arbiter pipeline depth */
+	out_be32(&im->arbiter.acr,
+		(im->arbiter.acr & ~ACR_PIPE_DEP) |
+		(CONFIG_SYS_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT)
+	);
+#endif
+
+#ifdef CONFIG_SYS_ACR_RPTCNT
+	/* Arbiter repeat count */
+	out_be32(im->arbiter.acr,
+		(im->arbiter.acr & ~(ACR_RPTCNT)) |
+		(CONFIG_SYS_ACR_RPTCNT << ACR_RPTCNT_SHIFT)
+	);
+#endif
+
+	/* RSR - Reset Status Register - clear all status */
+	gd->arch.reset_status = im->reset.rsr;
+	out_be32(&im->reset.rsr, ~RSR_RES);
+
+	/*
+	 * RMR - Reset Mode Register - enable checkstop reset
+	 */
+	out_be32(&im->reset.rmr, RMR_CSRE & (1 << RMR_CSRE_SHIFT));
+
+	/* Set IPS-CSB divider: IPS = 1/2 CSB */
+	ips_div = in_be32(&im->clk.scfr[0]);
+	ips_div &= ~(SCFR1_IPS_DIV_MASK);
+	ips_div |= SCFR1_IPS_DIV << SCFR1_IPS_DIV_SHIFT;
+	out_be32(&im->clk.scfr[0], ips_div);
+
+#ifdef SCFR1_LPC_DIV
+	clrsetbits_be32(&im->clk.scfr[0], SCFR1_LPC_DIV_MASK,
+			SCFR1_LPC_DIV << SCFR1_LPC_DIV_SHIFT);
+#endif
+
+#ifdef SCFR1_NFC_DIV
+	clrsetbits_be32(&im->clk.scfr[0], SCFR1_NFC_DIV_MASK,
+			SCFR1_NFC_DIV << SCFR1_NFC_DIV_SHIFT);
+#endif
+
+#ifdef SCFR1_DIU_DIV
+	clrsetbits_be32(&im->clk.scfr[0], SCFR1_DIU_DIV_MASK,
+			SCFR1_DIU_DIV << SCFR1_DIU_DIV_SHIFT);
+#endif
+
+	/*
+	 * Enable Time Base/Decrementer
+	 *
+	 * NOTICE: TB needs to be enabled as early as possible in order to
+	 * have udelay() working; if not enabled, usually leads to a hang, like
+	 * during FLASH chip identification etc.
+	 */
+	setbits_be32(&im->sysconf.spcr, SPCR_TBEN);
+
+	/*
+	 * Enable clocks
+	 */
+	out_be32(&im->clk.sccr[0], SCCR1_CLOCKS_EN);
+	out_be32(&im->clk.sccr[1], SCCR2_CLOCKS_EN);
+#if defined(CONFIG_FSL_IIM) || defined(CONFIG_CMD_FUSE)
+	setbits_be32(&im->clk.sccr[1], CLOCK_SCCR2_IIM_EN);
+#endif
+}
+
+int cpu_init_r (void)
+{
+	return 0;
+}
diff --git a/arch/powerpc/cpu/mpc512x/diu.c b/arch/powerpc/cpu/mpc512x/diu.c
new file mode 100644
index 0000000000..36e1f9cffd
--- /dev/null
+++ b/arch/powerpc/cpu/mpc512x/diu.c
@@ -0,0 +1,44 @@ 
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ * York Sun <yorksun@freescale.com>
+ *
+ * FSL DIU Framebuffer driver
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/io.h>
+
+#include <fsl_diu_fb.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void diu_set_pixel_clock(unsigned int pixclock)
+{
+	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
+	volatile clk512x_t *clk = &immap->clk;
+	volatile unsigned int *clkdvdr = &clk->scfr[0];
+	unsigned long speed_ccb, temp, pixval;
+
+	speed_ccb = get_bus_freq(0) * 4;
+	temp = 1000000000/pixclock;
+	temp *= 1000;
+	pixval = speed_ccb / temp;
+	debug("DIU pixval = %lu\n", pixval);
+
+	/* Modify PXCLK in GUTS CLKDVDR */
+	debug("DIU: Current value of CLKDVDR = 0x%08x\n", in_be32(clkdvdr));
+	temp = in_be32(clkdvdr) & 0xFFFFFF00;
+	out_be32(clkdvdr, temp | (pixval & 0xFF));
+	debug("DIU: Modified value of CLKDVDR = 0x%08x\n", in_be32(clkdvdr));
+}
+
+int platform_diu_init(unsigned int xres, unsigned int yres, const char *port)
+{
+	unsigned int pixel_format = 0x88883316;
+
+	debug("mpc5121_diu_init\n");
+	return fsl_diu_init(xres, yres, pixel_format, 0);
+}
diff --git a/arch/powerpc/cpu/mpc512x/fixed_sdram.c b/arch/powerpc/cpu/mpc512x/fixed_sdram.c
new file mode 100644
index 0000000000..68c5f8a27b
--- /dev/null
+++ b/arch/powerpc/cpu/mpc512x/fixed_sdram.c
@@ -0,0 +1,155 @@ 
+/*
+ * (C) Copyright 2007-2009 DENX Software Engineering
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/mpc512x.h>
+
+/*
+ * MDDRC Config Runtime Settings
+ */
+ddr512x_config_t default_mddrc_config = {
+	.ddr_sys_config   = CONFIG_SYS_MDDRC_SYS_CFG,
+	.ddr_time_config0 = CONFIG_SYS_MDDRC_TIME_CFG0,
+	.ddr_time_config1 = CONFIG_SYS_MDDRC_TIME_CFG1,
+	.ddr_time_config2 = CONFIG_SYS_MDDRC_TIME_CFG2,
+};
+
+u32 default_init_seq[] = {
+	CONFIG_SYS_DDRCMD_NOP,
+	CONFIG_SYS_DDRCMD_NOP,
+	CONFIG_SYS_DDRCMD_NOP,
+	CONFIG_SYS_DDRCMD_NOP,
+	CONFIG_SYS_DDRCMD_NOP,
+	CONFIG_SYS_DDRCMD_NOP,
+	CONFIG_SYS_DDRCMD_NOP,
+	CONFIG_SYS_DDRCMD_NOP,
+	CONFIG_SYS_DDRCMD_NOP,
+	CONFIG_SYS_DDRCMD_NOP,
+	CONFIG_SYS_DDRCMD_PCHG_ALL,
+	CONFIG_SYS_DDRCMD_NOP,
+	CONFIG_SYS_DDRCMD_RFSH,
+	CONFIG_SYS_DDRCMD_NOP,
+	CONFIG_SYS_DDRCMD_RFSH,
+	CONFIG_SYS_DDRCMD_NOP,
+	CONFIG_SYS_MICRON_INIT_DEV_OP,
+	CONFIG_SYS_DDRCMD_NOP,
+	CONFIG_SYS_DDRCMD_EM2,
+	CONFIG_SYS_DDRCMD_NOP,
+	CONFIG_SYS_DDRCMD_PCHG_ALL,
+	CONFIG_SYS_DDRCMD_EM2,
+	CONFIG_SYS_DDRCMD_EM3,
+	CONFIG_SYS_DDRCMD_EN_DLL,
+	CONFIG_SYS_MICRON_INIT_DEV_OP,
+	CONFIG_SYS_DDRCMD_PCHG_ALL,
+	CONFIG_SYS_DDRCMD_RFSH,
+	CONFIG_SYS_MICRON_INIT_DEV_OP,
+	CONFIG_SYS_DDRCMD_OCD_DEFAULT,
+	CONFIG_SYS_DDRCMD_PCHG_ALL,
+	CONFIG_SYS_DDRCMD_NOP
+};
+
+/*
+ * fixed sdram init:
+ * The board doesn't use memory modules that have serial presence
+ * detect or similar mechanism for discovery of the DRAM settings
+ */
+long int fixed_sdram(ddr512x_config_t *mddrc_config,
+			u32 *dram_init_seq, int seq_sz)
+{
+	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+	u32 msize = CONFIG_SYS_MAX_RAM_SIZE;
+	u32 msize_log2 = __ilog2(msize);
+	u32 i;
+
+	/* take default settings and init sequence if necessary */
+	if (mddrc_config == NULL)
+		mddrc_config = &default_mddrc_config;
+	if (dram_init_seq == NULL) {
+		dram_init_seq = default_init_seq;
+		seq_sz = ARRAY_SIZE(default_init_seq);
+	}
+
+	/* Initialize IO Control */
+	out_be32(&im->io_ctrl.io_control_mem, CONFIG_SYS_IOCTRL_MUX_DDR);
+
+	/* Initialize DDR Local Window */
+	out_be32(&im->sysconf.ddrlaw.bar, CONFIG_SYS_DDR_BASE & 0xFFFFF000);
+	out_be32(&im->sysconf.ddrlaw.ar, msize_log2 - 1);
+	sync_law(&im->sysconf.ddrlaw.ar);
+
+	/* DDR Enable */
+	/*
+	 * the "enable" combination: DRAM controller out of reset,
+	 * clock enabled, command mode -- BUT leave CKE low for now
+	 */
+	i = MDDRC_SYS_CFG_EN & ~MDDRC_SYS_CFG_CKE_MASK;
+	out_be32(&im->mddrc.ddr_sys_config, i);
+	/* maintain 200 microseconds of stable power and clock */
+	udelay(200);
+	/* apply a NOP, it shouldn't harm */
+	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_DDRCMD_NOP);
+	/* now assert CKE (high) */
+	i |= MDDRC_SYS_CFG_CKE_MASK;
+	out_be32(&im->mddrc.ddr_sys_config, i);
+
+	/* Initialize DDR Priority Manager */
+	out_be32(&im->mddrc.prioman_config1, CONFIG_SYS_MDDRCGRP_PM_CFG1);
+	out_be32(&im->mddrc.prioman_config2, CONFIG_SYS_MDDRCGRP_PM_CFG2);
+	out_be32(&im->mddrc.hiprio_config, CONFIG_SYS_MDDRCGRP_HIPRIO_CFG);
+	out_be32(&im->mddrc.lut_table0_main_upper, CONFIG_SYS_MDDRCGRP_LUT0_MU);
+	out_be32(&im->mddrc.lut_table0_main_lower, CONFIG_SYS_MDDRCGRP_LUT0_ML);
+	out_be32(&im->mddrc.lut_table1_main_upper, CONFIG_SYS_MDDRCGRP_LUT1_MU);
+	out_be32(&im->mddrc.lut_table1_main_lower, CONFIG_SYS_MDDRCGRP_LUT1_ML);
+	out_be32(&im->mddrc.lut_table2_main_upper, CONFIG_SYS_MDDRCGRP_LUT2_MU);
+	out_be32(&im->mddrc.lut_table2_main_lower, CONFIG_SYS_MDDRCGRP_LUT2_ML);
+	out_be32(&im->mddrc.lut_table3_main_upper, CONFIG_SYS_MDDRCGRP_LUT3_MU);
+	out_be32(&im->mddrc.lut_table3_main_lower, CONFIG_SYS_MDDRCGRP_LUT3_ML);
+	out_be32(&im->mddrc.lut_table4_main_upper, CONFIG_SYS_MDDRCGRP_LUT4_MU);
+	out_be32(&im->mddrc.lut_table4_main_lower, CONFIG_SYS_MDDRCGRP_LUT4_ML);
+	out_be32(&im->mddrc.lut_table0_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT0_AU);
+	out_be32(&im->mddrc.lut_table0_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT0_AL);
+	out_be32(&im->mddrc.lut_table1_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT1_AU);
+	out_be32(&im->mddrc.lut_table1_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT1_AL);
+	out_be32(&im->mddrc.lut_table2_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT2_AU);
+	out_be32(&im->mddrc.lut_table2_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT2_AL);
+	out_be32(&im->mddrc.lut_table3_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT3_AU);
+	out_be32(&im->mddrc.lut_table3_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT3_AL);
+	out_be32(&im->mddrc.lut_table4_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT4_AU);
+	out_be32(&im->mddrc.lut_table4_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT4_AL);
+
+	/*
+	 * Initialize MDDRC
+	 *  put MDDRC in CMD mode and
+	 *  set the max time between refreshes to 0 during init process
+	 */
+	out_be32(&im->mddrc.ddr_sys_config,
+		mddrc_config->ddr_sys_config | MDDRC_SYS_CFG_CMD_MASK);
+	out_be32(&im->mddrc.ddr_time_config0,
+		mddrc_config->ddr_time_config0 & MDDRC_REFRESH_ZERO_MASK);
+	out_be32(&im->mddrc.ddr_time_config1,
+		mddrc_config->ddr_time_config1);
+	out_be32(&im->mddrc.ddr_time_config2,
+		mddrc_config->ddr_time_config2);
+
+	/* Initialize DDR with either default or supplied init sequence */
+	for (i = 0; i < seq_sz; i++)
+		out_be32(&im->mddrc.ddr_command, dram_init_seq[i]);
+
+	/* Start MDDRC */
+	out_be32(&im->mddrc.ddr_time_config0, mddrc_config->ddr_time_config0);
+	out_be32(&im->mddrc.ddr_sys_config, mddrc_config->ddr_sys_config);
+
+	/* Allow for the DLL to startup before accessing data */
+	udelay(10);
+
+	msize = get_ram_size(CONFIG_SYS_DDR_BASE, CONFIG_SYS_MAX_RAM_SIZE);
+	/* Fix DDR Local Window for new size */
+	out_be32(&im->sysconf.ddrlaw.ar, __ilog2(msize) - 1);
+	sync_law(&im->sysconf.ddrlaw.ar);
+
+	return msize;
+}
diff --git a/arch/powerpc/cpu/mpc512x/ide.c b/arch/powerpc/cpu/mpc512x/ide.c
new file mode 100644
index 0000000000..dd1130694d
--- /dev/null
+++ b/arch/powerpc/cpu/mpc512x/ide.c
@@ -0,0 +1,111 @@ 
+/*
+ * (C) Copyright 2007-2009 DENX Software Engineering
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_IDE_RESET)
+
+void ide_set_reset (int idereset)
+{
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+	debug ("ide_set_reset(%d)\n", idereset);
+
+	if (idereset) {
+		out_be32(&im->pata.pata_ata_control, 0);
+	} else {
+		out_be32(&im->pata.pata_ata_control, FSL_ATA_CTRL_ATA_RST_B);
+	}
+	udelay(100);
+}
+
+void init_ide_reset (void)
+{
+	debug ("init_ide_reset\n");
+
+	/*
+	 * Clear the reset bit to reset the interface
+	 * cf. RefMan MPC5121EE: 28.4.1 Resetting the ATA Bus
+	 */
+	ide_set_reset(1);
+
+	/* Assert the reset bit to enable the interface */
+	ide_set_reset(0);
+
+}
+
+#define CALC_TIMING(t) (t + period - 1) / period
+
+int ide_preinit (void)
+{
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+	long t;
+	const struct {
+		short t0;
+		short t1;
+		short t2_8;
+		short t2_16;
+		short t2i;
+		short t4;
+		short t9;
+		short tA;
+	} pio_specs = {
+		.t0    = 600,
+		.t1    =  70,
+		.t2_8  = 290,
+		.t2_16 = 165,
+		.t2i   =   0,
+		.t4    =  30,
+		.t9    =  20,
+		.tA    =  50,
+	};
+	union {
+		u32 config;
+		struct {
+			u8 field1;
+			u8 field2;
+			u8 field3;
+			u8 field4;
+		}bytes;
+	} cfg;
+
+	debug ("IDE preinit using PATA peripheral at IMMR-ADDR %08x\n",
+		(u32)&im->pata);
+
+	/* Set the reset bit to 1 to enable the interface */
+	ide_set_reset(0);
+
+	/* Init timings : we use PIO mode 0 timings */
+	t = 1000000000 / gd->arch.ips_clk;	/* period in ns */
+	cfg.bytes.field1 = 3;
+	cfg.bytes.field2 = 3;
+	cfg.bytes.field3 = (pio_specs.t1 + t) / t;
+	cfg.bytes.field4 = (pio_specs.t2_8 + t) / t;
+
+	out_be32(&im->pata.pata_time1, cfg.config);
+
+	cfg.bytes.field1 = (pio_specs.t2_8 + t) / t;
+	cfg.bytes.field2 = (pio_specs.tA + t) / t + 2;
+	cfg.bytes.field3 = 1;
+	cfg.bytes.field4 = (pio_specs.t4 + t) / t;
+
+	out_be32(&im->pata.pata_time2, cfg.config);
+
+	cfg.config = in_be32(&im->pata.pata_time3);
+	cfg.bytes.field1 = (pio_specs.t9 + t) / t;
+
+	out_be32(&im->pata.pata_time3, cfg.config);
+
+	debug ("PATA preinit complete.\n");
+
+	return 0;
+}
+
+#endif /* defined(CONFIG_IDE_RESET) */
diff --git a/arch/powerpc/cpu/mpc512x/interrupts.c b/arch/powerpc/cpu/mpc512x/interrupts.c
new file mode 100644
index 0000000000..3385aed1cc
--- /dev/null
+++ b/arch/powerpc/cpu/mpc512x/interrupts.c
@@ -0,0 +1,45 @@ 
+/*
+ * (C) Copyright 2000-2007
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright 2004 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Derived from the MPC83xx code.
+ */
+
+#include <common.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct irq_action {
+	interrupt_handler_t *handler;
+	void *arg;
+	ulong count;
+};
+
+int interrupt_init_cpu (unsigned *decrementer_count)
+{
+	*decrementer_count = get_tbclk () / CONFIG_SYS_HZ;
+
+	return 0;
+}
+
+/*
+ * Install and free an interrupt handler.
+ */
+void
+irq_install_handler (int irq, interrupt_handler_t * handler, void *arg)
+{
+}
+
+void irq_free_handler (int irq)
+{
+}
+
+void timer_interrupt_cpu (struct pt_regs *regs)
+{
+	/* nothing to do here */
+	return;
+}
diff --git a/arch/powerpc/cpu/mpc512x/iopin.c b/arch/powerpc/cpu/mpc512x/iopin.c
new file mode 100644
index 0000000000..0b53c7b98e
--- /dev/null
+++ b/arch/powerpc/cpu/mpc512x/iopin.c
@@ -0,0 +1,87 @@ 
+/*
+ * (C) Copyright 2008
+ * Martha J Marx, Silicon Turnkey Express, mmarx@silicontkx.com
+ * mpc512x I/O pin/pad initialization for the ADS5121 board
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/types.h>
+#include <asm/io.h>
+
+void iopin_initialize(iopin_t *ioregs_init, int len)
+{
+	short i, j, p;
+	u32 *reg;
+	immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+
+	reg = (u32 *)&(im->io_ctrl);
+
+	if (sizeof(ioregs_init) == 0)
+		return;
+
+	for (i = 0; i < len; i++) {
+		for (p = 0, j = ioregs_init[i].p_offset / sizeof(u_long);
+			p < ioregs_init[i].nr_pins; p++, j++) {
+			if (ioregs_init[i].bit_or)
+				setbits_be32(reg + j, ioregs_init[i].val);
+			else
+				out_be32 (reg + j, ioregs_init[i].val);
+		}
+	}
+	return;
+}
+
+void iopin_initialize_bits(iopin_t *ioregs_init, int len)
+{
+	short i, j, p;
+	u32 *reg, mask;
+	immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+
+	reg = (u32 *)&(im->io_ctrl);
+
+	/* iterate over table entries */
+	for (i = 0; i < len; i++) {
+		/* iterate over pins within a table entry */
+		for (p = 0, j = ioregs_init[i].p_offset / sizeof(u_long);
+			p < ioregs_init[i].nr_pins; p++, j++) {
+			if (ioregs_init[i].bit_or & IO_PIN_OVER_EACH) {
+				/* replace all settings at once */
+				out_be32(reg + j, ioregs_init[i].val);
+			} else {
+				/*
+				 * only replace individual parts, but
+				 * REPLACE them instead of just ORing
+				 * them in and "inheriting" previously
+				 * set bits which we don't want
+				 */
+				mask = 0;
+				if (ioregs_init[i].bit_or & IO_PIN_OVER_FMUX)
+					mask |= IO_PIN_FMUX(3);
+
+				if (ioregs_init[i].bit_or & IO_PIN_OVER_HOLD)
+					mask |= IO_PIN_HOLD(3);
+
+				if (ioregs_init[i].bit_or & IO_PIN_OVER_PULL)
+					mask |= IO_PIN_PUD(1) | IO_PIN_PUE(1);
+
+				if (ioregs_init[i].bit_or & IO_PIN_OVER_STRIG)
+					mask |= IO_PIN_ST(1);
+
+				if (ioregs_init[i].bit_or & IO_PIN_OVER_DRVSTR)
+					mask |= IO_PIN_DS(3);
+				/*
+				 * DON'T do the "mask, then insert"
+				 * in place on the register, it may
+				 * break access to external hardware
+				 * (like boot ROMs) when configuring
+				 * LPB related pins, while the code to
+				 * configure the pin is read from this
+				 * very address region
+				 */
+				clrsetbits_be32(reg + j, mask,
+						ioregs_init[i].val & mask);
+			}
+		}
+	}
+}
diff --git a/arch/powerpc/cpu/mpc512x/pci.c b/arch/powerpc/cpu/mpc512x/pci.c
new file mode 100644
index 0000000000..7ea5df2960
--- /dev/null
+++ b/arch/powerpc/cpu/mpc512x/pci.c
@@ -0,0 +1,209 @@ 
+/*
+ * Copyright (C) 2009-2010 DENX Software Engineering <wd@denx.de>
+ * Copyright (C) Freescale Semiconductor, Inc. 2006, 2007.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+
+#include <asm/io.h>
+#include <asm/mmu.h>
+#include <asm/global_data.h>
+#include <pci.h>
+#if defined(CONFIG_OF_LIBFDT)
+#include <libfdt.h>
+#include <fdt_support.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* System RAM mapped to PCI space */
+#define CONFIG_PCI_SYS_MEM_BUS	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_PCI_SYS_MEM_PHYS	CONFIG_SYS_SDRAM_BASE
+
+static struct pci_controller pci_hose;
+
+
+/**************************************************************************
+ * pci_init_board()
+ *
+ */
+void
+pci_init_board(void)
+{
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+	volatile law512x_t *pci_law;
+	volatile pot512x_t *pci_pot;
+	volatile pcictrl512x_t *pci_ctrl;
+	u16 reg16;
+	u32 reg32;
+	u32 dev;
+	int i;
+	struct pci_controller *hose;
+
+	/* Set PCI divider for 33MHz */
+	reg32 = in_be32(&im->clk.scfr[0]);
+	reg32 &= ~(SCFR1_PCI_DIV_MASK);
+	reg32 |= SCFR1_PCI_DIV << SCFR1_PCI_DIV_SHIFT;
+	out_be32(&im->clk.scfr[0], reg32);
+
+	clrsetbits_be32(&im->clk.scfr[0],
+			SCFR1_PCI_DIV_MASK,
+			SCFR1_PCI_DIV << SCFR1_PCI_DIV_SHIFT
+	);
+
+	pci_law = im->sysconf.pcilaw;
+	pci_pot = im->ios.pot;
+	pci_ctrl = &im->pci_ctrl;
+
+	hose = &pci_hose;
+
+	/*
+	 * Release PCI RST Output signal
+	 */
+	out_be32(&pci_ctrl->gcr, 0);
+	udelay(2000);
+	out_be32(&pci_ctrl->gcr, 1);
+
+	/* We need to wait at least a 1sec based on PCI specs */
+	for (i = 0; i < 1000; i++)
+		udelay(1000);
+
+	/*
+	 * Configure PCI Local Access Windows
+	 */
+	out_be32(&pci_law[0].bar, CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR);
+	out_be32(&pci_law[0].ar, LAWAR_EN | LAWAR_SIZE_512M);
+
+	out_be32(&pci_law[1].bar, CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR);
+	out_be32(&pci_law[1].ar, LAWAR_EN | LAWAR_SIZE_16M);
+
+	/*
+	 * Configure PCI Outbound Translation Windows
+	 */
+
+	/* PCI mem space - prefetch */
+	out_be32(&pci_pot[0].potar,
+		(CONFIG_SYS_PCI_MEM_BASE >> 12) & POTAR_TA_MASK);
+	out_be32(&pci_pot[0].pobar,
+		(CONFIG_SYS_PCI_MEM_PHYS >> 12) & POBAR_BA_MASK);
+	out_be32(&pci_pot[0].pocmr,
+		POCMR_EN | POCMR_PRE | POCMR_CM_256M);
+
+	/* PCI IO space */
+	out_be32(&pci_pot[1].potar,
+		(CONFIG_SYS_PCI_IO_BASE >> 12) & POTAR_TA_MASK);
+	out_be32(&pci_pot[1].pobar,
+		(CONFIG_SYS_PCI_IO_PHYS >> 12) & POBAR_BA_MASK);
+	out_be32(&pci_pot[1].pocmr,
+		POCMR_EN | POCMR_IO | POCMR_CM_16M);
+
+	/* PCI mmio - non-prefetch mem space */
+	out_be32(&pci_pot[2].potar,
+		(CONFIG_SYS_PCI_MMIO_BASE >> 12) & POTAR_TA_MASK);
+	out_be32(&pci_pot[2].pobar,
+		(CONFIG_SYS_PCI_MMIO_PHYS >> 12) & POBAR_BA_MASK);
+	out_be32(&pci_pot[2].pocmr,
+		POCMR_EN | POCMR_CM_256M);
+
+	/*
+	 * Configure PCI Inbound Translation Windows
+	 */
+
+	/* we need RAM mapped to PCI space for the devices to
+	 * access main memory */
+	out_be32(&pci_ctrl[0].pitar1, 0x0);
+	out_be32(&pci_ctrl[0].pibar1, 0x0);
+	out_be32(&pci_ctrl[0].piebar1, 0x0);
+	out_be32(&pci_ctrl[0].piwar1,
+		PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP |
+		PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1));
+
+	hose->first_busno = 0;
+	hose->last_busno = 0xff;
+
+	/* PCI memory prefetch space */
+	pci_set_region(hose->regions + 0,
+		       CONFIG_SYS_PCI_MEM_BASE,
+		       CONFIG_SYS_PCI_MEM_PHYS,
+		       CONFIG_SYS_PCI_MEM_SIZE,
+		       PCI_REGION_MEM|PCI_REGION_PREFETCH);
+
+	/* PCI memory space */
+	pci_set_region(hose->regions + 1,
+		       CONFIG_SYS_PCI_MMIO_BASE,
+		       CONFIG_SYS_PCI_MMIO_PHYS,
+		       CONFIG_SYS_PCI_MMIO_SIZE,
+		       PCI_REGION_MEM);
+
+	/* PCI IO space */
+	pci_set_region(hose->regions + 2,
+		       CONFIG_SYS_PCI_IO_BASE,
+		       CONFIG_SYS_PCI_IO_PHYS,
+		       CONFIG_SYS_PCI_IO_SIZE,
+		       PCI_REGION_IO);
+
+	/* System memory space */
+	pci_set_region(hose->regions + 3,
+		       CONFIG_PCI_SYS_MEM_BUS,
+		       CONFIG_PCI_SYS_MEM_PHYS,
+		       gd->ram_size,
+		       PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
+
+	hose->region_count = 4;
+
+	pci_setup_indirect(hose,
+			   (CONFIG_SYS_IMMR + 0x8300),
+			   (CONFIG_SYS_IMMR + 0x8304));
+
+	pci_register_hose(hose);
+
+	/*
+	 * Write to Command register
+	 */
+	reg16 = 0xff;
+	dev = PCI_BDF(hose->first_busno, 0, 0);
+	pci_hose_read_config_word(hose, dev, PCI_COMMAND, &reg16);
+	reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
+	pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
+
+	/*
+	 * Clear non-reserved bits in status register.
+	 */
+	pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
+	pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
+	pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
+
+#ifdef CONFIG_PCI_SCAN_SHOW
+	printf("PCI:   Bus Dev VenId DevId Class Int\n");
+#endif
+	/*
+	 * Hose scan.
+	 */
+	hose->last_busno = pci_hose_scan(hose);
+}
+
+#if defined(CONFIG_OF_LIBFDT)
+void ft_pci_setup(void *blob, bd_t *bd)
+{
+	int nodeoffset;
+	int tmp[2];
+	const char *path;
+
+	nodeoffset = fdt_path_offset(blob, "/aliases");
+	if (nodeoffset >= 0) {
+		path = fdt_getprop(blob, nodeoffset, "pci", NULL);
+		if (path) {
+			tmp[0] = cpu_to_be32(pci_hose.first_busno);
+			tmp[1] = cpu_to_be32(pci_hose.last_busno);
+			do_fixup_by_path(blob, path, "bus-range",
+				&tmp, sizeof(tmp), 1);
+
+			tmp[0] = cpu_to_be32(gd->pci_clk);
+			do_fixup_by_path(blob, path, "clock-frequency",
+				&tmp, sizeof(tmp[0]), 1);
+		}
+	}
+}
+#endif /* CONFIG_OF_LIBFDT */
diff --git a/arch/powerpc/cpu/mpc512x/serial.c b/arch/powerpc/cpu/mpc512x/serial.c
new file mode 100644
index 0000000000..ac77ddcf4d
--- /dev/null
+++ b/arch/powerpc/cpu/mpc512x/serial.c
@@ -0,0 +1,431 @@ 
+/*
+ * (C) Copyright 2000 - 2010
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Based ont the MPC5200 PSC driver.
+ * Adapted for MPC512x by Jan Wrobel <wrr@semihalf.com>
+ */
+
+/*
+ * Minimal serial functions needed to use one of the PSC ports
+ * as serial console interface.
+ */
+
+#include <common.h>
+#include <linux/compiler.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+#include <serial.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_PSC_CONSOLE)
+
+static void fifo_init (volatile psc512x_t *psc)
+{
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+	u32 tfsize, rfsize;
+
+	/* reset Rx & Tx fifo slice */
+	out_be32(&psc->rfcmd, PSC_FIFO_RESET_SLICE);
+	out_be32(&psc->tfcmd, PSC_FIFO_RESET_SLICE);
+
+	/* disable Tx & Rx FIFO interrupts */
+	out_be32(&psc->rfintmask, 0);
+	out_be32(&psc->tfintmask, 0);
+
+	switch (((u32)psc & 0xf00) >> 8) {
+	case 0:
+		tfsize = FIFOC_PSC0_TX_SIZE | (FIFOC_PSC0_TX_ADDR << 16);
+		rfsize = FIFOC_PSC0_RX_SIZE | (FIFOC_PSC0_RX_ADDR << 16);
+		break;
+	case 1:
+		tfsize = FIFOC_PSC1_TX_SIZE | (FIFOC_PSC1_TX_ADDR << 16);
+		rfsize = FIFOC_PSC1_RX_SIZE | (FIFOC_PSC1_RX_ADDR << 16);
+		break;
+	case 2:
+		tfsize = FIFOC_PSC2_TX_SIZE | (FIFOC_PSC2_TX_ADDR << 16);
+		rfsize = FIFOC_PSC2_RX_SIZE | (FIFOC_PSC2_RX_ADDR << 16);
+		break;
+	case 3:
+		tfsize = FIFOC_PSC3_TX_SIZE | (FIFOC_PSC3_TX_ADDR << 16);
+		rfsize = FIFOC_PSC3_RX_SIZE | (FIFOC_PSC3_RX_ADDR << 16);
+		break;
+	case 4:
+		tfsize = FIFOC_PSC4_TX_SIZE | (FIFOC_PSC4_TX_ADDR << 16);
+		rfsize = FIFOC_PSC4_RX_SIZE | (FIFOC_PSC4_RX_ADDR << 16);
+		break;
+	case 5:
+		tfsize = FIFOC_PSC5_TX_SIZE | (FIFOC_PSC5_TX_ADDR << 16);
+		rfsize = FIFOC_PSC5_RX_SIZE | (FIFOC_PSC5_RX_ADDR << 16);
+		break;
+	case 6:
+		tfsize = FIFOC_PSC6_TX_SIZE | (FIFOC_PSC6_TX_ADDR << 16);
+		rfsize = FIFOC_PSC6_RX_SIZE | (FIFOC_PSC6_RX_ADDR << 16);
+		break;
+	case 7:
+		tfsize = FIFOC_PSC7_TX_SIZE | (FIFOC_PSC7_TX_ADDR << 16);
+		rfsize = FIFOC_PSC7_RX_SIZE | (FIFOC_PSC7_RX_ADDR << 16);
+		break;
+	case 8:
+		tfsize = FIFOC_PSC8_TX_SIZE | (FIFOC_PSC8_TX_ADDR << 16);
+		rfsize = FIFOC_PSC8_RX_SIZE | (FIFOC_PSC8_RX_ADDR << 16);
+		break;
+	case 9:
+		tfsize = FIFOC_PSC9_TX_SIZE | (FIFOC_PSC9_TX_ADDR << 16);
+		rfsize = FIFOC_PSC9_RX_SIZE | (FIFOC_PSC9_RX_ADDR << 16);
+		break;
+	case 10:
+		tfsize = FIFOC_PSC10_TX_SIZE | (FIFOC_PSC10_TX_ADDR << 16);
+		rfsize = FIFOC_PSC10_RX_SIZE | (FIFOC_PSC10_RX_ADDR << 16);
+		break;
+	case 11:
+		tfsize = FIFOC_PSC11_TX_SIZE | (FIFOC_PSC11_TX_ADDR << 16);
+		rfsize = FIFOC_PSC11_RX_SIZE | (FIFOC_PSC11_RX_ADDR << 16);
+		break;
+	default:
+		return;
+	}
+
+	out_be32(&psc->tfsize, tfsize);
+	out_be32(&psc->rfsize, rfsize);
+
+	/* enable Tx & Rx FIFO slice */
+	out_be32(&psc->rfcmd, PSC_FIFO_ENABLE_SLICE);
+	out_be32(&psc->tfcmd, PSC_FIFO_ENABLE_SLICE);
+
+	out_be32(&im->fifoc.fifoc_cmd, FIFOC_DISABLE_CLOCK_GATE);
+	__asm__ volatile ("sync");
+}
+
+void serial_setbrg_dev(unsigned int idx)
+{
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+	volatile psc512x_t *psc = (psc512x_t *) &im->psc[idx];
+	unsigned long baseclk, div;
+	unsigned long baudrate;
+	char buf[16];
+	char *br_env;
+
+	baudrate = gd->baudrate;
+	if (idx != CONFIG_PSC_CONSOLE) {
+		/* Allows setting baudrate for other serial devices
+		 * on PSCx using environment. If not specified, use
+		 * the same baudrate as for console.
+		 */
+		sprintf(buf, "psc%d_baudrate", idx);
+		br_env = getenv(buf);
+		if (br_env)
+			baudrate = simple_strtoul(br_env, NULL, 10);
+
+		debug("%s: idx %d, baudrate %ld\n", __func__, idx, baudrate);
+	}
+
+	/* calculate divisor for setting PSC CTUR and CTLR registers */
+	baseclk = (gd->arch.ips_clk + 8) / 16;
+	div = (baseclk + (baudrate / 2)) / baudrate;
+
+	out_8(&psc->ctur, (div >> 8) & 0xff);
+	out_8(&psc->ctlr,  div & 0xff); /* set baudrate */
+}
+
+int serial_init_dev(unsigned int idx)
+{
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+	volatile psc512x_t *psc = (psc512x_t *) &im->psc[idx];
+	u32 reg;
+
+	reg = in_be32(&im->clk.sccr[0]);
+	out_be32(&im->clk.sccr[0], reg | CLOCK_SCCR1_PSC_EN(idx));
+
+	fifo_init (psc);
+
+	/* set MR register to point to MR1 */
+	out_8(&psc->command, PSC_SEL_MODE_REG_1);
+
+	/* disable Tx/Rx */
+	out_8(&psc->command, PSC_TX_DISABLE | PSC_RX_DISABLE);
+
+	/* choose the prescaler	by 16 for the Tx/Rx clock generation */
+	out_be16(&psc->psc_clock_select, 0xdd00);
+
+	/* switch to UART mode */
+	out_be32(&psc->sicr, 0);
+
+	/* mode register points to mr1 */
+	/* configure parity, bit length and so on in mode register 1*/
+	out_8(&psc->mode, PSC_MODE_8_BITS | PSC_MODE_PARNONE);
+	/* now, mode register points to mr2 */
+	out_8(&psc->mode, PSC_MODE_1_STOPBIT);
+
+	/* set baudrate */
+	serial_setbrg_dev(idx);
+
+	/* disable all interrupts */
+	out_be16(&psc->psc_imr, 0);
+
+	/* reset and enable Rx/Tx */
+	out_8(&psc->command, PSC_RST_RX);
+	out_8(&psc->command, PSC_RST_TX);
+	out_8(&psc->command, PSC_RX_ENABLE | PSC_TX_ENABLE);
+
+	return 0;
+}
+
+int serial_uninit_dev(unsigned int idx)
+{
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+	volatile psc512x_t *psc = (psc512x_t *) &im->psc[idx];
+	u32 reg;
+
+	out_8(&psc->command, PSC_RX_DISABLE | PSC_TX_DISABLE);
+	reg = in_be32(&im->clk.sccr[0]);
+	reg &= ~CLOCK_SCCR1_PSC_EN(idx);
+	out_be32(&im->clk.sccr[0], reg);
+
+	return 0;
+}
+
+void serial_putc_dev(unsigned int idx, const char c)
+{
+	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+	volatile psc512x_t *psc = (psc512x_t *) &im->psc[idx];
+
+	if (c == '\n')
+		serial_putc_dev(idx, '\r');
+
+	/* Wait for last character to go. */
+	while (!(in_be16(&psc->psc_status) & PSC_SR_TXEMP))
+		;
+
+	out_8(&psc->tfdata_8, c);
+}
+
+void serial_puts_dev(unsigned int idx, const char *s)
+{
+	while (*s)
+		serial_putc_dev(idx, *s++);
+}
+
+int serial_getc_dev(unsigned int idx)
+{
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+	volatile psc512x_t *psc = (psc512x_t *) &im->psc[idx];
+
+	/* Wait for a character to arrive. */
+	while (in_be32(&psc->rfstat) & PSC_FIFO_EMPTY)
+		;
+
+	return in_8(&psc->rfdata_8);
+}
+
+int serial_tstc_dev(unsigned int idx)
+{
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+	volatile psc512x_t *psc = (psc512x_t *) &im->psc[idx];
+
+	return !(in_be32(&psc->rfstat) & PSC_FIFO_EMPTY);
+}
+
+void serial_setrts_dev(unsigned int idx, int s)
+{
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+	volatile psc512x_t *psc = (psc512x_t *) &im->psc[idx];
+
+	if (s) {
+		/* Assert RTS (become LOW) */
+		out_8(&psc->op1, 0x1);
+	}
+	else {
+		/* Negate RTS (become HIGH) */
+		out_8(&psc->op0, 0x1);
+	}
+}
+
+int serial_getcts_dev(unsigned int idx)
+{
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+	volatile psc512x_t *psc = (psc512x_t *) &im->psc[idx];
+
+	return (in_8(&psc->ip) & 0x1) ? 0 : 1;
+}
+#endif /* CONFIG_PSC_CONSOLE */
+
+#define DECLARE_PSC_SERIAL_FUNCTIONS(port) \
+	int serial##port##_init(void) \
+	{ \
+		return serial_init_dev(port); \
+	} \
+	int serial##port##_uninit(void) \
+	{ \
+		return serial_uninit_dev(port); \
+	} \
+	void serial##port##_setbrg(void) \
+	{ \
+		serial_setbrg_dev(port); \
+	} \
+	int serial##port##_getc(void) \
+	{ \
+		return serial_getc_dev(port); \
+	} \
+	int serial##port##_tstc(void) \
+	{ \
+		return serial_tstc_dev(port); \
+	} \
+	void serial##port##_putc(const char c) \
+	{ \
+		serial_putc_dev(port, c); \
+	} \
+	void serial##port##_puts(const char *s) \
+	{ \
+		serial_puts_dev(port, s); \
+	}
+
+#define INIT_PSC_SERIAL_STRUCTURE(port, __name) {	\
+	.name	= __name,				\
+	.start	= serial##port##_init,			\
+	.stop	= serial##port##_uninit,		\
+	.setbrg	= serial##port##_setbrg,		\
+	.getc	= serial##port##_getc,			\
+	.tstc	= serial##port##_tstc,			\
+	.putc	= serial##port##_putc,			\
+	.puts	= serial##port##_puts,			\
+}
+
+#if defined(CONFIG_SYS_PSC1)
+DECLARE_PSC_SERIAL_FUNCTIONS(1);
+struct serial_device serial1_device =
+INIT_PSC_SERIAL_STRUCTURE(1, "psc1");
+#endif
+
+#if defined(CONFIG_SYS_PSC3)
+DECLARE_PSC_SERIAL_FUNCTIONS(3);
+struct serial_device serial3_device =
+INIT_PSC_SERIAL_STRUCTURE(3, "psc3");
+#endif
+
+#if defined(CONFIG_SYS_PSC4)
+DECLARE_PSC_SERIAL_FUNCTIONS(4);
+struct serial_device serial4_device =
+INIT_PSC_SERIAL_STRUCTURE(4, "psc4");
+#endif
+
+#if defined(CONFIG_SYS_PSC6)
+DECLARE_PSC_SERIAL_FUNCTIONS(6);
+struct serial_device serial6_device =
+INIT_PSC_SERIAL_STRUCTURE(6, "psc6");
+#endif
+
+__weak struct serial_device *default_serial_console(void)
+{
+#if (CONFIG_PSC_CONSOLE == 3)
+	return &serial3_device;
+#elif (CONFIG_PSC_CONSOLE == 6)
+	return &serial6_device;
+#else
+#error "invalid CONFIG_PSC_CONSOLE"
+#endif
+}
+
+void mpc512x_serial_initialize(void)
+{
+#if defined(CONFIG_SYS_PSC1)
+	serial_register(&serial1_device);
+#endif
+#if defined(CONFIG_SYS_PSC3)
+	serial_register(&serial3_device);
+#endif
+#if defined(CONFIG_SYS_PSC4)
+	serial_register(&serial4_device);
+#endif
+#if defined(CONFIG_SYS_PSC6)
+	serial_register(&serial6_device);
+#endif
+}
+
+#include <stdio_dev.h>
+/*
+ * Routines for communication with serial devices over PSC
+ */
+/* Bitfield for initialized PSCs */
+static unsigned int initialized;
+
+struct stdio_dev *open_port(int num, int baudrate)
+{
+	struct stdio_dev *port;
+	char env_var[16];
+	char env_val[10];
+	char name[7];
+
+	if (num < 0 || num > 11)
+		return NULL;
+
+	sprintf(name, "psc%d", num);
+	port = stdio_get_by_name(name);
+	if (!port)
+		return NULL;
+
+	if (!test_bit(num, &initialized)) {
+		sprintf(env_var, "psc%d_baudrate", num);
+		sprintf(env_val, "%d", baudrate);
+		setenv(env_var, env_val);
+
+		if (port->start(port))
+			return NULL;
+
+		set_bit(num, &initialized);
+	}
+
+	return port;
+}
+
+int close_port(int num)
+{
+	struct stdio_dev *port;
+	int ret;
+	char name[7];
+
+	if (num < 0 || num > 11)
+		return -1;
+
+	sprintf(name, "psc%d", num);
+	port = stdio_get_by_name(name);
+	if (!port)
+		return -1;
+
+	ret = port->stop(port);
+	clear_bit(num, &initialized);
+
+	return ret;
+}
+
+int write_port(struct stdio_dev *port, char *buf)
+{
+	if (!port || !buf)
+		return -1;
+
+	port->puts(port, buf);
+
+	return 0;
+}
+
+int read_port(struct stdio_dev *port, char *buf, int size)
+{
+	int cnt = 0;
+
+	if (!port || !buf)
+		return -1;
+
+	if (!size)
+		return 0;
+
+	while (port->tstc(port)) {
+		buf[cnt++] = port->getc(port);
+		if (cnt > size)
+			break;
+	}
+
+	return cnt;
+}
diff --git a/arch/powerpc/cpu/mpc512x/speed.c b/arch/powerpc/cpu/mpc512x/speed.c
new file mode 100644
index 0000000000..95069cad84
--- /dev/null
+++ b/arch/powerpc/cpu/mpc512x/speed.c
@@ -0,0 +1,137 @@ 
+/*
+ * (C) Copyright 2000-2009
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Based on the MPC83xx code.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int spmf_mult[] = {
+	68, 1, 12, 16,
+	20, 24, 28, 32,
+	36, 40, 44, 48,
+	52, 56, 60, 64
+};
+
+static int cpmf_mult[][2] = {
+	{0, 1}, {0, 1}, /* 0 and 1 are not valid */
+	{1, 1}, {3, 2},
+	{2, 1}, {5, 2},
+	{3, 1}, {7, 2},
+	{0, 1}, {0, 1}, /* and all above 7 are not valid too */
+	{0, 1}, {0, 1},
+	{0, 1}, {0, 1},
+	{0, 1}, {0, 1}
+};
+
+static int sys_dividors[][2] = {
+	{2, 1}, {5, 2}, {3, 1}, {7, 2}, {4, 1},
+	{9, 2}, {5, 1}, {7, 1}, {6, 1}, {8, 1},
+	{9, 1}, {11, 1}, {10, 1}, {12, 1}, {13, 1},
+	{15, 1}, {14, 1}, {16, 1}, {17, 1}, {19, 1},
+	{18, 1}, {20, 1}, {21, 1}, {23, 1}, {22, 1},
+	{24, 1}, {25, 1}, {27, 1}, {26, 1}, {28, 1},
+	{29, 1}, {31, 1}, {30, 1}, {32, 1}, {33, 1}
+};
+
+int get_clocks (void)
+{
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+	u8 spmf;
+	u8 cpmf;
+	u8 sys_div;
+	u8 ips_div;
+	u8 pci_div;
+	u32 ref_clk = CONFIG_SYS_MPC512X_CLKIN;
+	u32 spll;
+	u32 sys_clk;
+	u32 core_clk;
+	u32 csb_clk;
+	u32 ips_clk;
+	u32 pci_clk;
+	u32 reg;
+
+	reg = in_be32(&im->sysconf.immrbar);
+	if ((reg & IMMRBAR_BASE_ADDR) != (u32) im)
+		return -1;
+
+	reg = in_be32(&im->clk.spmr);
+	spmf = (reg & SPMR_SPMF) >> SPMR_SPMF_SHIFT;
+	spll = ref_clk * spmf_mult[spmf];
+
+	reg = in_be32(&im->clk.scfr[1]);
+	sys_div = (reg & SCFR2_SYS_DIV) >> SCFR2_SYS_DIV_SHIFT;
+	sys_clk = (spll * sys_dividors[sys_div][1]) / sys_dividors[sys_div][0];
+
+	csb_clk = sys_clk / 2;
+
+	reg = in_be32(&im->clk.spmr);
+	cpmf = (reg & SPMR_CPMF) >> SPMR_CPMF_SHIFT;
+	core_clk = (csb_clk * cpmf_mult[cpmf][0]) / cpmf_mult[cpmf][1];
+
+	reg = in_be32(&im->clk.scfr[0]);
+	ips_div = (reg & SCFR1_IPS_DIV_MASK) >> SCFR1_IPS_DIV_SHIFT;
+	if (ips_div != 0) {
+		ips_clk = csb_clk / ips_div;
+	} else {
+		/* in case we cannot get a sane IPS divisor, fail gracefully */
+		ips_clk = 0;
+	}
+
+	reg = in_be32(&im->clk.scfr[0]);
+	pci_div = (reg & SCFR1_PCI_DIV_MASK) >> SCFR1_PCI_DIV_SHIFT;
+	if (pci_div != 0) {
+		pci_clk = csb_clk / pci_div;
+	} else {
+		/* in case we cannot get a sane IPS divisor, fail gracefully */
+		pci_clk = 333333;
+	}
+
+	gd->arch.ips_clk = ips_clk;
+	gd->pci_clk = pci_clk;
+	gd->arch.csb_clk = csb_clk;
+	gd->cpu_clk = core_clk;
+	gd->bus_clk = csb_clk;
+	return 0;
+
+}
+
+/********************************************
+ * get_bus_freq
+ * return system bus freq in Hz
+ *********************************************/
+ulong get_bus_freq (ulong dummy)
+{
+	return gd->arch.csb_clk;
+}
+
+int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+{
+	char buf[32];
+
+	printf("Clock configuration:\n");
+	printf("  CPU:                 %-4s MHz\n", strmhz(buf, gd->cpu_clk));
+	printf("  Coherent System Bus: %-4s MHz\n",
+	       strmhz(buf, gd->arch.csb_clk));
+	printf("  IPS Bus:             %-4s MHz\n",
+	       strmhz(buf, gd->arch.ips_clk));
+	printf("  PCI:                 %-4s MHz\n", strmhz(buf, gd->pci_clk));
+	printf("  DDR:                 %-4s MHz\n",
+	       strmhz(buf, 2 * gd->arch.csb_clk));
+	return 0;
+}
+
+U_BOOT_CMD(clocks, 1, 0, do_clocks,
+	"print clock configuration",
+	"    clocks"
+);
diff --git a/arch/powerpc/cpu/mpc512x/start.S b/arch/powerpc/cpu/mpc512x/start.S
new file mode 100644
index 0000000000..dd3066ec4c
--- /dev/null
+++ b/arch/powerpc/cpu/mpc512x/start.S
@@ -0,0 +1,694 @@ 
+/*
+ * Copyright (C) 1998  Dan Malek <dmalek@jlc.net>
+ * Copyright (C) 1999  Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
+ * Copyright (C) 2000-2009 Wolfgang Denk <wd@denx.de>
+ * Copyright Freescale Semiconductor, Inc. 2004, 2006.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Based on the MPC83xx code.
+ */
+
+/*
+ *  U-Boot - Startup Code for MPC512x based Embedded Boards
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <version.h>
+
+#define CONFIG_521X	1		/* needed for Linux kernel header files*/
+
+#include <asm/immap_512x.h>
+#include "asm-offsets.h"
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+
+#include <asm/cache.h>
+#include <asm/mmu.h>
+#include <asm/u-boot.h>
+
+/*
+ * Floating Point enable, Machine Check and Recoverable Interr.
+ */
+#undef	MSR_KERNEL
+#ifdef DEBUG
+#define MSR_KERNEL (MSR_FP|MSR_RI)
+#else
+#define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI)
+#endif
+
+/* Macros for manipulating CSx_START/STOP */
+#define START_REG(start)	((start) >> 16)
+#define STOP_REG(start, size)	(((start) + (size) - 1) >> 16)
+
+/*
+ * Set up GOT: Global Offset Table
+ *
+ * Use r12 to access the GOT
+ */
+	START_GOT
+	GOT_ENTRY(_GOT2_TABLE_)
+	GOT_ENTRY(_FIXUP_TABLE_)
+
+	GOT_ENTRY(_start)
+	GOT_ENTRY(_start_of_vectors)
+	GOT_ENTRY(_end_of_vectors)
+	GOT_ENTRY(transfer_to_handler)
+
+	GOT_ENTRY(__init_end)
+	GOT_ENTRY(__bss_end)
+	GOT_ENTRY(__bss_start)
+	END_GOT
+
+/*
+ * Magic number and version string
+ */
+	.long	0x27051956		/* U-Boot Magic Number */
+	.globl	version_string
+version_string:
+	.ascii U_BOOT_VERSION_STRING, "\0"
+
+/*
+ * Vector Table
+ */
+	.text
+	. = EXC_OFF_SYS_RESET
+
+	.globl	_start
+	/* Start from here after reset/power on */
+_start:
+	b	boot_cold
+
+	.globl	_start_of_vectors
+_start_of_vectors:
+
+/* Machine check */
+	STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
+
+/* Data Storage exception. */
+	STD_EXCEPTION(0x300, DataStorage, UnknownException)
+
+/* Instruction Storage exception. */
+	STD_EXCEPTION(0x400, InstStorage, UnknownException)
+
+/* External Interrupt exception. */
+	STD_EXCEPTION(0x500, ExtInterrupt, UnknownException)
+
+/* Alignment exception. */
+	. = 0x600
+Alignment:
+	EXCEPTION_PROLOG(SRR0, SRR1)
+	mfspr	r4,DAR
+	stw	r4,_DAR(r21)
+	mfspr	r5,DSISR
+	stw	r5,_DSISR(r21)
+	addi	r3,r1,STACK_FRAME_OVERHEAD
+	EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
+
+/* Program check exception */
+	. = 0x700
+ProgramCheck:
+	EXCEPTION_PROLOG(SRR0, SRR1)
+	addi	r3,r1,STACK_FRAME_OVERHEAD
+	EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
+		MSR_KERNEL, COPY_EE)
+
+/* Floating Point Unit unavailable exception */
+	STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
+
+/* Decrementer */
+	STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
+
+/* Critical interrupt */
+	STD_EXCEPTION(0xa00, Critical, UnknownException)
+
+/* System Call */
+	STD_EXCEPTION(0xc00, SystemCall, UnknownException)
+
+/* Trace interrupt */
+	STD_EXCEPTION(0xd00, Trace, UnknownException)
+
+/* Performance Monitor interrupt */
+	STD_EXCEPTION(0xf00, PerfMon, UnknownException)
+
+/* Intruction Translation Miss */
+	STD_EXCEPTION(0x1000, InstructionTLBMiss, UnknownException)
+
+/* Data Load Translation Miss */
+	STD_EXCEPTION(0x1100, DataLoadTLBMiss, UnknownException)
+
+/* Data Store Translation Miss */
+	STD_EXCEPTION(0x1200, DataStoreTLBMiss, UnknownException)
+
+/* Instruction Address Breakpoint */
+	STD_EXCEPTION(0x1300, InstructionAddrBreakpoint, DebugException)
+
+/* System Management interrupt */
+	STD_EXCEPTION(0x1400, SystemMgmtInterrupt, UnknownException)
+
+	.globl	_end_of_vectors
+_end_of_vectors:
+
+	. = 0x3000
+boot_cold:
+	/* Save msr contents */
+	mfmsr	r5
+
+	/* Set IMMR area to our preferred location */
+	lis	r4, CONFIG_DEFAULT_IMMR@h
+	lis	r3, CONFIG_SYS_IMMR@h
+	ori	r3, r3, CONFIG_SYS_IMMR@l
+	stw	r3, IMMRBAR(r4)
+	mtspr	MBAR, r3		/* IMMRBAR is mirrored into the MBAR SPR (311) */
+
+	/* Initialise the machine */
+	bl	cpu_early_init
+
+	/*
+	 * Set up Local Access Windows:
+	 *
+	 * 1) Boot/CS0 (boot FLASH)
+	 * 2) On-chip SRAM (initial stack purposes)
+	 */
+
+	/* Boot CS/CS0 window range */
+	lis     r3, CONFIG_SYS_IMMR@h
+	ori     r3, r3, CONFIG_SYS_IMMR@l
+
+	lis	r4, START_REG(CONFIG_SYS_FLASH_BASE)
+	ori	r4, r4, STOP_REG(CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE)
+	stw	r4, LPCS0AW(r3)
+
+	/*
+	 * The SRAM window has a fixed size (256K), so only the start address
+	 * is necessary
+	 */
+	lis	r4, START_REG(CONFIG_SYS_SRAM_BASE) & 0xff00
+	stw	r4, SRAMBAR(r3)
+
+	/*
+	 * According to MPC5121e RM, configuring local access windows should
+	 * be followed by a dummy read of the config register that was
+	 * modified last and an isync
+	 */
+	lwz	r4, SRAMBAR(r3)
+	isync
+
+	/*
+	 * Set configuration of the Boot/CS0, the SRAM window does not have a
+	 * config register so no params can be set for it
+	 */
+	lis     r3, (CONFIG_SYS_IMMR + LPC_OFFSET)@h
+	ori     r3, r3, (CONFIG_SYS_IMMR + LPC_OFFSET)@l
+
+	lis     r4, CONFIG_SYS_CS0_CFG@h
+	ori     r4, r4, CONFIG_SYS_CS0_CFG@l
+	stw     r4, CS0_CONFIG(r3)
+
+	/* Master enable all CS's */
+	lis	r4, CS_CTRL_ME@h
+	ori	r4, r4, CS_CTRL_ME@l
+	stw	r4, CS_CTRL(r3)
+
+	lis	r4, (CONFIG_SYS_MONITOR_BASE)@h
+	ori	r4, r4, (CONFIG_SYS_MONITOR_BASE)@l
+	addi	r5, r4, in_flash - _start + EXC_OFF_SYS_RESET
+	mtlr	r5
+	blr
+
+in_flash:
+	lis	r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h
+	ori	r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l
+
+	li	r0, 0		/* Make room for stack frame header and	*/
+	stwu	r0, -4(r1)	/* clear final stack frame so that	*/
+	stwu	r0, -4(r1)	/* stack backtraces terminate cleanly	*/
+
+	/* let the C-code set up the rest			*/
+	/*							*/
+	/* Be careful to keep code relocatable & stack humble	*/
+	/*------------------------------------------------------*/
+
+	GET_GOT			/* initialize GOT access	*/
+
+	/* r3: IMMR */
+	lis	r3, CONFIG_SYS_IMMR@h
+	/* run low-level CPU init code (in Flash) */
+	bl	cpu_init_f
+
+	/* run 1st part of board init code (in Flash) */
+	bl	board_init_f
+
+	/* NOTREACHED - board_init_f() does not return */
+
+/*
+ * This code finishes saving the registers to the exception frame
+ * and jumps to the appropriate handler for the exception.
+ * Register r21 is pointer into trap frame, r1 has new stack pointer.
+ */
+	.globl	transfer_to_handler
+transfer_to_handler:
+	stw	r22,_NIP(r21)
+	lis	r22,MSR_POW@h
+	andc	r23,r23,r22
+	stw	r23,_MSR(r21)
+	SAVE_GPR(7, r21)
+	SAVE_4GPRS(8, r21)
+	SAVE_8GPRS(12, r21)
+	SAVE_8GPRS(24, r21)
+	mflr	r23
+	andi.	r24,r23,0x3f00		/* get vector offset */
+	stw	r24,TRAP(r21)
+	li	r22,0
+	stw	r22,RESULT(r21)
+	lwz	r24,0(r23)		/* virtual address of handler */
+	lwz	r23,4(r23)		/* where to go when done */
+	mtspr	SRR0,r24
+	mtspr	SRR1,r20
+	mtlr	r23
+	SYNC
+	rfi				/* jump to handler, enable MMU */
+
+int_return:
+	mfmsr	r28		/* Disable interrupts */
+	li	r4,0
+	ori	r4,r4,MSR_EE
+	andc	r28,r28,r4
+	SYNC			/* Some chip revs need this... */
+	mtmsr	r28
+	SYNC
+	lwz	r2,_CTR(r1)
+	lwz	r0,_LINK(r1)
+	mtctr	r2
+	mtlr	r0
+	lwz	r2,_XER(r1)
+	lwz	r0,_CCR(r1)
+	mtspr	XER,r2
+	mtcrf	0xFF,r0
+	REST_10GPRS(3, r1)
+	REST_10GPRS(13, r1)
+	REST_8GPRS(23, r1)
+	REST_GPR(31, r1)
+	lwz	r2,_NIP(r1)	/* Restore environment */
+	lwz	r0,_MSR(r1)
+	mtspr	SRR0,r2
+	mtspr	SRR1,r0
+	lwz	r0,GPR0(r1)
+	lwz	r2,GPR2(r1)
+	lwz	r1,GPR1(r1)
+	SYNC
+	rfi
+
+/*
+ * This code initialises the machine, it expects original MSR contents to be in r5.
+ */
+cpu_early_init:
+	/* Initialize machine status; enable machine check interrupt */
+	/*-----------------------------------------------------------*/
+
+	li	r3, MSR_KERNEL			/* Set ME and RI flags */
+	rlwimi	r3, r5, 0, 25, 25		/* preserve IP bit */
+#ifdef DEBUG
+	rlwimi	r3, r5, 0, 21, 22		/* debugger might set SE, BE bits */
+#endif
+	mtmsr	r3
+	SYNC
+	mtspr	SRR1, r3			/* Mirror current MSR state in SRR1 */
+
+	lis	r3, CONFIG_SYS_IMMR@h
+
+#if defined(CONFIG_WATCHDOG)
+	/* Initialise the watchdog and reset it */
+	/*--------------------------------------*/
+	lis r4, CONFIG_SYS_WATCHDOG_VALUE
+	ori r4, r4, (SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR)
+	stw r4, SWCRR(r3)
+
+	/* reset */
+	li	r4, 0x556C
+	sth	r4, SWSRR@l(r3)
+	li	r4, 0x0
+	ori	r4, r4, 0xAA39
+	sth	r4, SWSRR@l(r3)
+#else
+	/* Disable the watchdog */
+	/*----------------------*/
+	lwz r4, SWCRR(r3)
+	/*
+	 * Check to see if it's enabled for disabling: once disabled by s/w
+	 * it's not possible to re-enable it
+	 */
+	andi. r4, r4, 0x4
+	beq 1f
+	xor r4, r4, r4
+	stw r4, SWCRR(r3)
+1:
+#endif /* CONFIG_WATCHDOG */
+
+	/* Initialize the Hardware Implementation-dependent Registers */
+	/* HID0 also contains cache control			*/
+	/*------------------------------------------------------*/
+	lis	r3, CONFIG_SYS_HID0_INIT@h
+	ori	r3, r3, CONFIG_SYS_HID0_INIT@l
+	SYNC
+	mtspr	HID0, r3
+
+	lis	r3, CONFIG_SYS_HID0_FINAL@h
+	ori	r3, r3, CONFIG_SYS_HID0_FINAL@l
+	SYNC
+	mtspr	HID0, r3
+
+	lis	r3, CONFIG_SYS_HID2@h
+	ori	r3, r3, CONFIG_SYS_HID2@l
+	SYNC
+	mtspr	HID2, r3
+	sync
+	blr
+
+
+/* Cache functions.
+ *
+ * Note: requires that all cache bits in
+ * HID0 are in the low half word.
+ */
+	.globl	icache_enable
+icache_enable:
+	mfspr	r3, HID0
+	ori	r3, r3, HID0_ICE
+	lis	r4, 0
+	ori	r4, r4, HID0_ILOCK
+	andc	r3, r3, r4
+	ori	r4, r3, HID0_ICFI
+	isync
+	mtspr	HID0, r4    /* sets enable and invalidate, clears lock */
+	isync
+	mtspr	HID0, r3	/* clears invalidate */
+	blr
+
+	.globl	icache_disable
+icache_disable:
+	mfspr	r3, HID0
+	lis	r4, 0
+	ori	r4, r4, HID0_ICE|HID0_ILOCK
+	andc	r3, r3, r4
+	ori	r4, r3, HID0_ICFI
+	isync
+	mtspr	HID0, r4     /* sets invalidate, clears enable and lock*/
+	isync
+	mtspr	HID0, r3	/* clears invalidate */
+	blr
+
+	.globl	icache_status
+icache_status:
+	mfspr	r3, HID0
+	rlwinm	r3, r3, (31 - HID0_ICE_SHIFT + 1), 31, 31
+	blr
+
+	.globl	dcache_enable
+dcache_enable:
+	mfspr	r3, HID0
+	li	r5, HID0_DCFI|HID0_DLOCK
+	andc	r3, r3, r5
+	mtspr	HID0, r3		/* no invalidate, unlock */
+	ori	r3, r3, HID0_DCE
+	ori	r5, r3, HID0_DCFI
+	mtspr	HID0, r5		/* enable + invalidate */
+	mtspr	HID0, r3		/* enable */
+	sync
+	blr
+
+	.globl	dcache_disable
+dcache_disable:
+	mfspr	r3, HID0
+	lis	r4, 0
+	ori	r4, r4, HID0_DCE|HID0_DLOCK
+	andc	r3, r3, r4
+	ori	r4, r3, HID0_DCI
+	sync
+	mtspr	HID0, r4	/* sets invalidate, clears enable and lock */
+	sync
+	mtspr	HID0, r3	/* clears invalidate */
+	blr
+
+	.globl	dcache_status
+dcache_status:
+	mfspr	r3, HID0
+	rlwinm	r3, r3, (31 - HID0_DCE_SHIFT + 1), 31, 31
+	blr
+
+	.globl get_pvr
+get_pvr:
+	mfspr	r3, PVR
+	blr
+
+	.globl get_svr
+get_svr:
+	mfspr	r3, SVR
+	blr
+
+/*-------------------------------------------------------------------*/
+
+/*
+ * void relocate_code (addr_sp, gd, addr_moni)
+ *
+ * This "function" does not return, instead it continues in RAM
+ * after relocating the monitor code.
+ *
+ * r3 = dest
+ * r4 = src
+ * r5 = length in bytes
+ * r6 = cachelinesize
+ */
+	.globl	relocate_code
+relocate_code:
+	mr	r1,  r3		/* Set new stack pointer	*/
+	mr	r9,  r4		/* Save copy of Global Data pointer */
+	mr	r10, r5		/* Save copy of Destination Address */
+
+	GET_GOT
+	mr	r3,  r5				/* Destination Address */
+	lis	r4, CONFIG_SYS_MONITOR_BASE@h		/* Source      Address */
+	ori	r4, r4, CONFIG_SYS_MONITOR_BASE@l
+	lwz	r5, GOT(__init_end)
+	sub	r5, r5, r4
+	li	r6, CONFIG_SYS_CACHELINE_SIZE		/* Cache Line Size */
+
+	/*
+	 * Fix GOT pointer:
+	 *
+	 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE)
+	 *		+ Destination Address
+	 *
+	 * Offset:
+	 */
+	sub	r15, r10, r4
+
+	/* First our own GOT */
+	add	r12, r12, r15
+	/* then the one used by the C code */
+	add	r30, r30, r15
+
+	/*
+	 * Now relocate code
+	 */
+	cmplw	cr1,r3,r4
+	addi	r0,r5,3
+	srwi.	r0,r0,2
+	beq	cr1,4f		/* In place copy is not necessary */
+	beq	7f		/* Protect against 0 count	  */
+	mtctr	r0
+	bge	cr1,2f
+	la	r8,-4(r4)
+	la	r7,-4(r3)
+
+	/* copy */
+1:	lwzu	r0,4(r8)
+	stwu	r0,4(r7)
+	bdnz	1b
+
+	addi	r0,r5,3
+	srwi.	r0,r0,2
+	mtctr	r0
+	la	r8,-4(r4)
+	la	r7,-4(r3)
+
+	/* and compare */
+20:	lwzu	r20,4(r8)
+	lwzu	r21,4(r7)
+	xor. r22, r20, r21
+	bne  30f
+	bdnz	20b
+	b 4f
+
+	/* compare failed */
+30:	li r3, 0
+	blr
+
+2:	slwi	r0,r0,2 /* re copy in reverse order ... y do we needed it? */
+	add	r8,r4,r0
+	add	r7,r3,r0
+3:	lwzu	r0,-4(r8)
+	stwu	r0,-4(r7)
+	bdnz	3b
+
+/*
+ * Now flush the cache: note that we must start from a cache aligned
+ * address. Otherwise we might miss one cache line.
+ */
+4:	cmpwi	r6,0
+	add	r5,r3,r5
+	beq	7f		/* Always flush prefetch queue in any case */
+	subi	r0,r6,1
+	andc	r3,r3,r0
+	mr	r4,r3
+5:	dcbst	0,r4
+	add	r4,r4,r6
+	cmplw	r4,r5
+	blt	5b
+	sync			/* Wait for all dcbst to complete on bus */
+	mr	r4,r3
+6:	icbi	0,r4
+	add	r4,r4,r6
+	cmplw	r4,r5
+	blt	6b
+7:	sync			/* Wait for all icbi to complete on bus	*/
+	isync
+
+/*
+ * We are done. Do not return, instead branch to second part of board
+ * initialization, now running from RAM.
+ */
+	addi	r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
+	mtlr	r0
+	blr
+
+in_ram:
+	/*
+	 * Relocation Function, r12 point to got2+0x8000
+	 *
+	 * Adjust got2 pointers, no need to check for 0, this code
+	 * already puts a few entries in the table.
+	 */
+	li	r0,__got2_entries@sectoff@l
+	la	r3,GOT(_GOT2_TABLE_)
+	lwz	r11,GOT(_GOT2_TABLE_)
+	mtctr	r0
+	sub	r11,r3,r11
+	addi	r3,r3,-4
+1:	lwzu	r0,4(r3)
+	cmpwi	r0,0
+	beq-	2f
+	add	r0,r0,r11
+	stw	r0,0(r3)
+2:	bdnz	1b
+
+	/*
+	 * Now adjust the fixups and the pointers to the fixups
+	 * in case we need to move ourselves again.
+	 */
+	li	r0,__fixup_entries@sectoff@l
+	lwz	r3,GOT(_FIXUP_TABLE_)
+	cmpwi	r0,0
+	mtctr	r0
+	addi	r3,r3,-4
+	beq	4f
+3:	lwzu	r4,4(r3)
+	lwzux	r0,r4,r11
+	cmpwi	r0,0
+	add	r0,r0,r11
+	stw	r4,0(r3)
+	beq-	5f
+	stw	r0,0(r4)
+5:	bdnz	3b
+4:
+clear_bss:
+	/*
+	 * Now clear BSS segment
+	 */
+	lwz	r3,GOT(__bss_start)
+	lwz	r4,GOT(__bss_end)
+
+	cmplw	0, r3, r4
+	beq	6f
+
+	li	r0, 0
+5:
+	stw	r0, 0(r3)
+	addi	r3, r3, 4
+	cmplw	0, r3, r4
+	bne	5b
+6:
+	mr	r3, r9		/* Global Data pointer		*/
+	mr	r4, r10		/* Destination Address		*/
+	bl	board_init_r
+
+	/*
+	 * Copy exception vector code to low memory
+	 *
+	 * r3: dest_addr
+	 * r7: source address, r8: end address, r9: target address
+	 */
+	.globl	trap_init
+trap_init:
+	mflr	r4		/* save link register */
+	GET_GOT
+	lwz	r7, GOT(_start)
+	lwz	r8, GOT(_end_of_vectors)
+
+	li	r9, 0x100	/* reset vector at 0x100 */
+
+	cmplw	0, r7, r8
+	bgelr			/* return if r7>=r8 - just in case */
+1:
+	lwz	r0, 0(r7)
+	stw	r0, 0(r9)
+	addi	r7, r7, 4
+	addi	r9, r9, 4
+	cmplw	0, r7, r8
+	bne	1b
+
+	/*
+	 * relocate `hdlr' and `int_return' entries
+	 */
+	li	r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
+	li	r8, Alignment - _start + EXC_OFF_SYS_RESET
+2:
+	bl	trap_reloc
+	addi	r7, r7, 0x100		/* next exception vector */
+	cmplw	0, r7, r8
+	blt	2b
+
+	li	r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
+	bl	trap_reloc
+
+	li	r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
+	bl	trap_reloc
+
+	li	r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
+	li	r8, SystemCall - _start + EXC_OFF_SYS_RESET
+3:
+	bl	trap_reloc
+	addi	r7, r7, 0x100		/* next exception vector */
+	cmplw	0, r7, r8
+	blt	3b
+
+	li	r7, .L_Trace - _start + EXC_OFF_SYS_RESET
+	li	r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
+4:
+	bl	trap_reloc
+	addi	r7, r7, 0x100		/* next exception vector */
+	cmplw	0, r7, r8
+	blt	4b
+
+	mfmsr	r3			/* now that the vectors have */
+	lis	r7, MSR_IP@h		/* relocated into low memory */
+	ori	r7, r7, MSR_IP@l	/* MSR[IP] can be turned off */
+	andc	r3, r3, r7		/* (if it was on) */
+	SYNC				/* Some chip revs need this... */
+	mtmsr	r3
+	SYNC
+
+	mtlr	r4			/* restore link register    */
+	blr
diff --git a/arch/powerpc/cpu/mpc512x/traps.c b/arch/powerpc/cpu/mpc512x/traps.c
new file mode 100644
index 0000000000..9f5bcd7fc3
--- /dev/null
+++ b/arch/powerpc/cpu/mpc512x/traps.c
@@ -0,0 +1,190 @@ 
+/*
+ * (C) Copyright 2000 - 2007
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 1995-1996  Gary Thomas (gdt@linuxppc.org)
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Derived from the MPC83xx code.
+ */
+
+/*
+ * This file handles the architecture-dependent parts of hardware
+ * exceptions
+ */
+
+#include <common.h>
+#include <kgdb.h>
+#include <asm/processor.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern unsigned long search_exception_table(unsigned long);
+
+/*
+ * End of addressable memory.  This may be less than the actual
+ * amount of memory on the system if we're unable to keep all
+ * the memory mapped in.
+ */
+#define END_OF_MEM (gd->bd->bi_memstart + get_effective_memsize())
+
+/*
+ * Trap & Exception support
+ */
+
+static void print_backtrace(unsigned long *sp)
+{
+	int cnt = 0;
+	unsigned long i;
+
+	puts("Call backtrace: ");
+	while (sp) {
+		if ((uint)sp > END_OF_MEM)
+			break;
+
+		i = sp[1];
+		if (cnt++ % 7 == 0)
+			putc('\n');
+		printf("%08lX ", i);
+		if (cnt > 32) break;
+		sp = (unsigned long *) *sp;
+	}
+	putc('\n');
+}
+
+void show_regs(struct pt_regs *regs)
+{
+	int i;
+
+	printf("NIP: %08lX XER: %08lX LR: %08lX REGS: %p TRAP: %04lx DAR: %08lX\n",
+	       regs->nip, regs->xer, regs->link, regs, regs->trap, regs->dar);
+	printf("MSR: %08lx EE: %01x PR: %01x FP: %01x ME: %01x IR/DR: %01x%01x\n",
+	       regs->msr, regs->msr & MSR_EE ? 1 : 0, regs->msr & MSR_PR ? 1 : 0,
+	       regs->msr & MSR_FP ? 1 : 0,regs->msr & MSR_ME ? 1 : 0,
+	       regs->msr & MSR_IR ? 1 : 0,
+	       regs->msr & MSR_DR ? 1 : 0);
+
+	putc('\n');
+	for (i = 0;  i < 32;  i++) {
+		if ((i % 8) == 0) {
+			printf("GPR%02d: ", i);
+		}
+
+		printf("%08lX ", regs->gpr[i]);
+		if ((i % 8) == 7) {
+			putc('\n');
+		}
+	}
+}
+
+
+static void _exception(int signr, struct pt_regs *regs)
+{
+	show_regs(regs);
+	print_backtrace((unsigned long *)regs->gpr[1]);
+	panic("Exception at pc %lx signal %d", regs->nip, signr);
+}
+
+
+void MachineCheckException(struct pt_regs *regs)
+{
+	unsigned long fixup = search_exception_table(regs->nip);
+
+	if (fixup) {
+		regs->nip = fixup;
+		return;
+	}
+
+#ifdef CONFIG_CMD_KGDB
+	if (debugger_exception_handler && (*debugger_exception_handler)(regs))
+		return;
+#endif
+
+	puts("Machine check.\nCaused by (from msr): ");
+	printf("regs %p ", regs);
+	switch (regs->msr & 0x00FF0000) {
+	case (0x80000000 >> 10):
+		puts("Instruction cache parity signal\n");
+		break;
+	case (0x80000000 >> 11):
+		puts("Data cache parity signal\n");
+		break;
+	case (0x80000000 >> 12):
+		puts("Machine check signal\n");
+		break;
+	case (0x80000000 >> 13):
+		puts("Transfer error ack signal\n");
+		break;
+	case (0x80000000 >> 14):
+		puts("Data parity signal\n");
+		break;
+	case (0x80000000 >> 15):
+		puts("Address parity signal\n");
+		break;
+	default:
+		puts("Unknown values in msr\n");
+	}
+	show_regs(regs);
+	print_backtrace((unsigned long *)regs->gpr[1]);
+
+	panic("machine check");
+}
+
+void AlignmentException(struct pt_regs *regs)
+{
+#ifdef CONFIG_CMD_KGDB
+	if (debugger_exception_handler && (*debugger_exception_handler)(regs))
+		return;
+#endif
+	show_regs(regs);
+	print_backtrace((unsigned long *)regs->gpr[1]);
+	panic("Alignment Exception");
+}
+
+void ProgramCheckException(struct pt_regs *regs)
+{
+#ifdef CONFIG_CMD_KGDB
+	if (debugger_exception_handler && (*debugger_exception_handler)(regs))
+		return;
+#endif
+	show_regs(regs);
+	print_backtrace((unsigned long *)regs->gpr[1]);
+	panic("Program Check Exception");
+}
+
+void SoftEmuException(struct pt_regs *regs)
+{
+#ifdef CONFIG_CMD_KGDB
+	if (debugger_exception_handler && (*debugger_exception_handler)(regs))
+		return;
+#endif
+	show_regs(regs);
+	print_backtrace((unsigned long *)regs->gpr[1]);
+	panic("Software Emulation Exception");
+}
+
+
+void UnknownException(struct pt_regs *regs)
+{
+#ifdef CONFIG_CMD_KGDB
+	if (debugger_exception_handler && (*debugger_exception_handler)(regs))
+		return;
+#endif
+	printf("Bad trap at PC: %lx, SR: %lx, vector=%lx\n",
+	       regs->nip, regs->msr, regs->trap);
+	_exception(0, regs);
+}
+
+#ifdef CONFIG_CMD_BEDBUG
+extern void do_bedbug_breakpoint(struct pt_regs *);
+#endif
+
+void DebugException(struct pt_regs *regs)
+{
+	printf("Debugger trap at @ %lx\n", regs->nip);
+	show_regs(regs);
+#ifdef CONFIG_CMD_BEDBUG
+	do_bedbug_breakpoint(regs);
+#endif
+}
diff --git a/arch/powerpc/cpu/mpc512x/u-boot.lds b/arch/powerpc/cpu/mpc512x/u-boot.lds
new file mode 100644
index 0000000000..b32f74e002
--- /dev/null
+++ b/arch/powerpc/cpu/mpc512x/u-boot.lds
@@ -0,0 +1,73 @@ 
+/*
+ * (C) Copyright 2007-2010 DENX Software Engineering.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+OUTPUT_ARCH(powerpc)
+SECTIONS
+{
+  .text      :
+  {
+    arch/powerpc/cpu/mpc512x/start.o	(.text*)
+    *(.text*)
+    . = ALIGN(16);
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    _GOT2_TABLE_ = .;
+    KEEP(*(.got2))
+    KEEP(*(.got))
+    _FIXUP_TABLE_ = .;
+    KEEP(*(.fixup))
+    *(.fixup)
+  }
+  __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data*)
+    *(.sdata*)
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	KEEP(*(SORT(.u_boot_list*)));
+  }
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   *(.bss*)
+   *(.sbss*)
+   *(COMMON)
+   . = ALIGN(4);
+  }
+  __bss_end = . ;
+  PROVIDE (end = .);
+}
+ENTRY(_start)
diff --git a/arch/powerpc/cpu/mpc5xxx/Kconfig b/arch/powerpc/cpu/mpc5xxx/Kconfig
new file mode 100644
index 0000000000..6ba0dd492d
--- /dev/null
+++ b/arch/powerpc/cpu/mpc5xxx/Kconfig
@@ -0,0 +1,90 @@ 
+menu "mpc5xxx CPU"
+	depends on MPC5xxx
+
+config SYS_CPU
+	default "mpc5xxx"
+
+choice
+	prompt "Target select"
+	optional
+
+config TARGET_A3M071
+	bool "Support a3m071"
+	select SUPPORT_SPL
+
+config TARGET_A4M072
+	bool "Support a4m072"
+
+config TARGET_CANMB
+	bool "Support canmb"
+
+config TARGET_CM5200
+	bool "Support cm5200"
+
+config TARGET_INKA4X0
+	bool "Support inka4x0"
+
+config TARGET_IPEK01
+	bool "Support ipek01"
+
+config TARGET_JUPITER
+	bool "Support jupiter"
+
+config TARGET_MOTIONPRO
+	bool "Support motionpro"
+
+config TARGET_MUNICES
+	bool "Support munices"
+
+config TARGET_V38B
+	bool "Support v38b"
+
+config TARGET_O2D
+	bool "Support O2D"
+
+config TARGET_O2D300
+	bool "Support O2D300"
+
+config TARGET_O2DNT2
+	bool "Support O2DNT2"
+
+config TARGET_O2I
+	bool "Support O2I"
+
+config TARGET_O2MNT
+	bool "Support O2MNT"
+
+config TARGET_O3DNT
+	bool "Support O3DNT"
+
+config TARGET_DIGSY_MTC
+	bool "Support digsy_mtc"
+	imply CMD_IRQ
+
+config TARGET_PCM030
+	bool "Support pcm030"
+
+config TARGET_CHARON
+	bool "Support charon"
+
+config TARGET_TQM5200
+	bool "Support TQM5200"
+
+endchoice
+
+source "board/a3m071/Kconfig"
+source "board/a4m072/Kconfig"
+source "board/canmb/Kconfig"
+source "board/cm5200/Kconfig"
+source "board/ifm/o2dnt2/Kconfig"
+source "board/inka4x0/Kconfig"
+source "board/intercontrol/digsy_mtc/Kconfig"
+source "board/ipek01/Kconfig"
+source "board/jupiter/Kconfig"
+source "board/motionpro/Kconfig"
+source "board/munices/Kconfig"
+source "board/phytec/pcm030/Kconfig"
+source "board/tqc/tqm5200/Kconfig"
+source "board/v38b/Kconfig"
+
+endmenu
diff --git a/arch/powerpc/cpu/mpc5xxx/Makefile b/arch/powerpc/cpu/mpc5xxx/Makefile
new file mode 100644
index 0000000000..88e3b2e3ae
--- /dev/null
+++ b/arch/powerpc/cpu/mpc5xxx/Makefile
@@ -0,0 +1,25 @@ 
+#
+# (C) Copyright 2003-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+extra-y	= start.o
+extra-y += traps.o
+obj-y  += io.o
+obj-y  += firmware_sc_task_bestcomm.impl.o
+obj-y += cpu.o
+obj-y += cpu_init.o
+obj-y += ide.o
+obj-y += interrupts.o
+obj-y += loadtask.o
+obj-y += pci_mpc5200.o
+obj-y += serial.o
+obj-y += speed.o
+obj-$(CONFIG_CMD_USB) += usb_ohci.o
+obj-$(CONFIG_CMD_USB) += usb.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl_boot.o
+endif
diff --git a/arch/powerpc/cpu/mpc5xxx/config.mk b/arch/powerpc/cpu/mpc5xxx/config.mk
new file mode 100644
index 0000000000..bcff2144a1
--- /dev/null
+++ b/arch/powerpc/cpu/mpc5xxx/config.mk
@@ -0,0 +1,8 @@ 
+#
+# (C) Copyright 2003-2010
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+PLATFORM_CPPFLAGS += -mstring -mcpu=603e -mmultiple
diff --git a/arch/powerpc/cpu/mpc5xxx/cpu.c b/arch/powerpc/cpu/mpc5xxx/cpu.c
new file mode 100644
index 0000000000..84fabbd473
--- /dev/null
+++ b/arch/powerpc/cpu/mpc5xxx/cpu.c
@@ -0,0 +1,168 @@ 
+/*
+ * (C) Copyright 2000-2010
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * CPU specific code for the MPC5xxx CPUs
+ */
+
+#include <common.h>
+#include <watchdog.h>
+#include <command.h>
+#include <net.h>
+#include <mpc5xxx.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+
+#if defined(CONFIG_OF_LIBFDT)
+#include <libfdt.h>
+#include <fdt_support.h>
+#endif
+
+#if defined(CONFIG_OF_IDE_FIXUP)
+#include <ide.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkcpu (void)
+{
+	ulong clock = gd->cpu_clk;
+	char buf[32];
+	uint svr, pvr;
+
+	puts ("CPU:   ");
+
+	svr = get_svr();
+	pvr = get_pvr();
+
+	switch (pvr) {
+	case PVR_5200:
+		printf("MPC5200");
+		break;
+	case PVR_5200B:
+		printf("MPC5200B");
+		break;
+	default:
+		printf("Unknown MPC5xxx");
+		break;
+	}
+
+	printf (" v%d.%d, Core v%d.%d", SVR_MJREV (svr), SVR_MNREV (svr),
+		PVR_MAJ(pvr), PVR_MIN(pvr));
+	printf (" at %s MHz\n", strmhz (buf, clock));
+	return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+int
+do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+{
+	ulong msr;
+	/* Interrupts and MMU off */
+	__asm__ __volatile__ ("mfmsr    %0":"=r" (msr):);
+
+	msr &= ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR);
+	__asm__ __volatile__ ("mtmsr    %0"::"r" (msr));
+
+	/* Charge the watchdog timer */
+	*(vu_long *)(MPC5XXX_GPT0_COUNTER) = 0x0001000f;
+	*(vu_long *)(MPC5XXX_GPT0_ENABLE) = 0x9004; /* wden|ce|timer_ms */
+	while(1);
+
+	return 1;
+
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Get timebase clock frequency (like cpu_clk in Hz)
+ *
+ */
+unsigned long get_tbclk (void)
+{
+	ulong tbclk;
+
+	tbclk = (gd->bus_clk + 3L) / 4L;
+
+	return (tbclk);
+}
+
+/* ------------------------------------------------------------------------- */
+
+#ifdef CONFIG_OF_BOARD_SETUP
+void ft_cpu_setup(void *blob, bd_t *bd)
+{
+	int div = in_8((void*)CONFIG_SYS_MBAR + 0x204) & 0x0020 ? 8 : 4;
+	char * cpu_path = "/cpus/" OF_CPU;
+#ifdef CONFIG_MPC5xxx_FEC
+	uchar enetaddr[6];
+	char * eth_path = "/" OF_SOC "/ethernet@3000";
+#endif
+
+	do_fixup_by_path_u32(blob, cpu_path, "timebase-frequency", OF_TBCLK, 1);
+	do_fixup_by_path_u32(blob, cpu_path, "bus-frequency", bd->bi_busfreq, 1);
+	do_fixup_by_path_u32(blob, cpu_path, "clock-frequency", bd->bi_intfreq, 1);
+	do_fixup_by_path_u32(blob, "/" OF_SOC, "bus-frequency", bd->bi_ipbfreq, 1);
+	do_fixup_by_path_u32(blob, "/" OF_SOC, "system-frequency",
+				bd->bi_busfreq*div, 1);
+#ifdef CONFIG_MPC5xxx_FEC
+	eth_getenv_enetaddr("ethaddr", enetaddr);
+	do_fixup_by_path(blob, eth_path, "mac-address", enetaddr, 6, 0);
+	do_fixup_by_path(blob, eth_path, "local-mac-address", enetaddr, 6, 0);
+#endif
+#ifdef CONFIG_OF_IDE_FIXUP
+	if (!ide_device_present(0)) {
+		/* NO CF card detected -> delete ata node in DTS */
+		int nodeoffset = 0;
+		char nodename[] = "/soc5200@f0000000/ata@3a00";
+
+		nodeoffset = fdt_path_offset(blob, nodename);
+		if (nodeoffset >= 0) {
+			fdt_del_node(blob, nodeoffset);
+		} else {
+			printf("%s: cannot find %s node err:%s\n",
+				__func__, nodename, fdt_strerror(nodeoffset));
+		}
+	}
+
+#endif /* CONFIG_OF_IDE_FIXUP */
+	fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
+}
+#endif /* CONFIG_OF_BOARD_SETUP */
+
+#ifdef CONFIG_MPC5xxx_FEC
+/* Default initializations for FEC controllers.  To override,
+ * create a board-specific function called:
+ * 	int board_eth_init(bd_t *bis)
+ */
+
+int cpu_eth_init(bd_t *bis)
+{
+	return mpc5xxx_fec_initialize(bis);
+}
+#endif
+
+#if defined(CONFIG_WATCHDOG)
+void watchdog_reset(void)
+{
+	int re_enable = disable_interrupts();
+	reset_5xxx_watchdog();
+	if (re_enable) enable_interrupts();
+}
+
+void reset_5xxx_watchdog(void)
+{
+	volatile struct mpc5xxx_gpt *gpt0 =
+		(struct mpc5xxx_gpt *) MPC5XXX_GPT;
+
+	/* Trigger TIMER_0 by writing A5 to OCPW */
+	clrsetbits_be32(&gpt0->emsr, 0xff000000, 0xa5000000);
+}
+#endif	/* CONFIG_WATCHDOG */
diff --git a/arch/powerpc/cpu/mpc5xxx/cpu_init.c b/arch/powerpc/cpu/mpc5xxx/cpu_init.c
new file mode 100644
index 0000000000..f9b57baf6d
--- /dev/null
+++ b/arch/powerpc/cpu/mpc5xxx/cpu_init.c
@@ -0,0 +1,231 @@ 
+/*
+ * (C) Copyright 2000-2010
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <asm/io.h>
+#include <watchdog.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Breath some life into the CPU...
+ *
+ * Set up the memory map,
+ * initialize a bunch of registers.
+ */
+void cpu_init_f (void)
+{
+	volatile struct mpc5xxx_mmap_ctl *mm =
+		(struct mpc5xxx_mmap_ctl *) CONFIG_SYS_MBAR;
+	volatile struct mpc5xxx_lpb *lpb =
+		(struct mpc5xxx_lpb *) MPC5XXX_LPB;
+	volatile struct mpc5xxx_gpio *gpio =
+		(struct mpc5xxx_gpio *) MPC5XXX_GPIO;
+	volatile struct mpc5xxx_xlb *xlb =
+		(struct mpc5xxx_xlb *) MPC5XXX_XLBARB;
+#if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK)
+	volatile struct mpc5xxx_cdm *cdm =
+		(struct mpc5xxx_cdm *) MPC5XXX_CDM;
+#endif	/* CONFIG_SYS_IPBCLK_EQUALS_XLBCLK */
+#if defined(CONFIG_WATCHDOG)
+	volatile struct mpc5xxx_gpt *gpt0 =
+		(struct mpc5xxx_gpt *) MPC5XXX_GPT;
+#endif /* CONFIG_WATCHDOG */
+	unsigned long addecr = (1 << 25); /* Boot_CS */
+	/* Pointer is writable since we allocated a register for it */
+	gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
+
+	/* Clear initial global data */
+	memset ((void *) gd, 0, sizeof (gd_t));
+
+	/*
+	 * Memory Controller: configure chip selects and enable them
+	 */
+#if defined(CONFIG_SYS_BOOTCS_START) && defined(CONFIG_SYS_BOOTCS_SIZE)
+	out_be32(&mm->boot_start, START_REG(CONFIG_SYS_BOOTCS_START));
+	out_be32(&mm->boot_stop, STOP_REG(CONFIG_SYS_BOOTCS_START,
+					  CONFIG_SYS_BOOTCS_SIZE));
+#endif
+#if defined(CONFIG_SYS_BOOTCS_CFG)
+	out_be32(&lpb->cs0_cfg, CONFIG_SYS_BOOTCS_CFG);
+#endif
+
+#if defined(CONFIG_SYS_CS0_START) && defined(CONFIG_SYS_CS0_SIZE)
+	out_be32(&mm->cs0_start, START_REG(CONFIG_SYS_CS0_START));
+	out_be32(&mm->cs0_stop, STOP_REG(CONFIG_SYS_CS0_START,
+					 CONFIG_SYS_CS0_SIZE));
+	/* CS0 and BOOT_CS cannot be enabled at once. */
+	/*	addecr |= (1 << 16); */
+#endif
+#if defined(CONFIG_SYS_CS0_CFG)
+	out_be32(&lpb->cs0_cfg, CONFIG_SYS_CS0_CFG);
+#endif
+
+#if defined(CONFIG_SYS_CS1_START) && defined(CONFIG_SYS_CS1_SIZE)
+	out_be32(&mm->cs1_start, START_REG(CONFIG_SYS_CS1_START));
+	out_be32(&mm->cs1_stop, STOP_REG(CONFIG_SYS_CS1_START,
+					 CONFIG_SYS_CS1_SIZE));
+	addecr |= (1 << 17);
+#endif
+#if defined(CONFIG_SYS_CS1_CFG)
+	out_be32(&lpb->cs1_cfg, CONFIG_SYS_CS1_CFG);
+#endif
+
+#if defined(CONFIG_SYS_CS2_START) && defined(CONFIG_SYS_CS2_SIZE)
+	out_be32(&mm->cs2_start, START_REG(CONFIG_SYS_CS2_START));
+	out_be32(&mm->cs2_stop, STOP_REG(CONFIG_SYS_CS2_START,
+					 CONFIG_SYS_CS2_SIZE));
+	addecr |= (1 << 18);
+#endif
+#if defined(CONFIG_SYS_CS2_CFG)
+	out_be32(&lpb->cs2_cfg, CONFIG_SYS_CS2_CFG);
+#endif
+
+#if defined(CONFIG_SYS_CS3_START) && defined(CONFIG_SYS_CS3_SIZE)
+	out_be32(&mm->cs3_start, START_REG(CONFIG_SYS_CS3_START));
+	out_be32(&mm->cs3_stop, STOP_REG(CONFIG_SYS_CS3_START,
+					 CONFIG_SYS_CS3_SIZE));
+	addecr |= (1 << 19);
+#endif
+#if defined(CONFIG_SYS_CS3_CFG)
+	out_be32(&lpb->cs3_cfg, CONFIG_SYS_CS3_CFG);
+#endif
+
+#if defined(CONFIG_SYS_CS4_START) && defined(CONFIG_SYS_CS4_SIZE)
+	out_be32(&mm->cs4_start, START_REG(CONFIG_SYS_CS4_START));
+	out_be32(&mm->cs4_stop, STOP_REG(CONFIG_SYS_CS4_START,
+					  CONFIG_SYS_CS4_SIZE));
+	addecr |= (1 << 20);
+#endif
+#if defined(CONFIG_SYS_CS4_CFG)
+	out_be32(&lpb->cs4_cfg, CONFIG_SYS_CS4_CFG);
+#endif
+
+#if defined(CONFIG_SYS_CS5_START) && defined(CONFIG_SYS_CS5_SIZE)
+	out_be32(&mm->cs5_start, START_REG(CONFIG_SYS_CS5_START));
+	out_be32(&mm->cs5_stop, STOP_REG(CONFIG_SYS_CS5_START,
+					  CONFIG_SYS_CS5_SIZE));
+	addecr |= (1 << 21);
+#endif
+#if defined(CONFIG_SYS_CS5_CFG)
+	out_be32(&lpb->cs5_cfg, CONFIG_SYS_CS5_CFG);
+#endif
+
+	addecr |= 1;
+#if defined(CONFIG_SYS_CS6_START) && defined(CONFIG_SYS_CS6_SIZE)
+	out_be32(&mm->cs6_start, START_REG(CONFIG_SYS_CS6_START));
+	out_be32(&mm->cs6_stop, STOP_REG(CONFIG_SYS_CS6_START,
+					  CONFIG_SYS_CS6_SIZE));
+	addecr |= (1 << 26);
+#endif
+#if defined(CONFIG_SYS_CS6_CFG)
+	out_be32(&lpb->cs6_cfg, CONFIG_SYS_CS6_CFG);
+#endif
+
+#if defined(CONFIG_SYS_CS7_START) && defined(CONFIG_SYS_CS7_SIZE)
+	out_be32(&mm->cs7_start, START_REG(CONFIG_SYS_CS7_START));
+	out_be32(&mm->cs7_stop, STOP_REG(CONFIG_SYS_CS7_START,
+					  CONFIG_SYS_CS7_SIZE));
+	addecr |= (1 << 27);
+#endif
+#if defined(CONFIG_SYS_CS7_CFG)
+	out_be32(&lpb->cs7_cfg, CONFIG_SYS_CS7_CFG);
+#endif
+
+#if defined(CONFIG_SYS_CS_BURST)
+	out_be32(&lpb->cs_burst, CONFIG_SYS_CS_BURST);
+#endif
+#if defined(CONFIG_SYS_CS_DEADCYCLE)
+	out_be32(&lpb->cs_deadcycle, CONFIG_SYS_CS_DEADCYCLE);
+#endif
+
+	/* Enable chip selects */
+	out_be32(&mm->ipbi_ws_ctrl, addecr);
+	out_be32(&lpb->cs_ctrl, (1 << 24));
+
+	/* Setup pin multiplexing */
+#if defined(CONFIG_SYS_GPS_PORT_CONFIG)
+	out_be32(&gpio->port_config, CONFIG_SYS_GPS_PORT_CONFIG);
+#endif
+
+	/* Setup gpios */
+#if defined(CONFIG_SYS_GPIO_DATADIR)
+	out_be32(&gpio->simple_ddr, CONFIG_SYS_GPIO_DATADIR);
+#endif
+#if defined(CONFIG_SYS_GPIO_OPENDRAIN)
+	out_be32(&gpio->simple_ode, CONFIG_SYS_GPIO_OPENDRAIN);
+#endif
+#if defined(CONFIG_SYS_GPIO_DATAVALUE)
+	out_be32(&gpio->simple_dvo, CONFIG_SYS_GPIO_DATAVALUE);
+#endif
+#if defined(CONFIG_SYS_GPIO_ENABLE)
+	out_be32(&gpio->simple_gpioe, CONFIG_SYS_GPIO_ENABLE);
+#endif
+
+	/* enable timebase */
+	setbits_be32(&xlb->config, (1 << 13));
+
+	/* Enable snooping for RAM */
+	setbits_be32(&xlb->config, (1 << 15));
+	out_be32(&xlb->snoop_window, CONFIG_SYS_SDRAM_BASE | 0x1d);
+
+#if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK)
+	/* Motorola reports IPB should better run at 133 MHz. */
+	setbits_be32(&mm->ipbi_ws_ctrl, 1);
+	/* pci_clk_sel = 0x02, ipb_clk_sel = 0x00; */
+	addecr = in_be32(&cdm->cfg);
+	addecr &= ~0x103;
+# if defined(CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2)
+	/* pci_clk_sel = 0x01 -> IPB_CLK/2 */
+	addecr |= 0x01;
+# else
+	/* pci_clk_sel = 0x02 -> XLB_CLK/4 = IPB_CLK/4 */
+	addecr |= 0x02;
+# endif /* CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 */
+	out_be32(&cdm->cfg, addecr);
+#endif	/* CONFIG_SYS_IPBCLK_EQUALS_XLBCLK */
+	/* Configure the XLB Arbiter */
+	out_be32(&xlb->master_pri_enable, 0xff);
+	out_be32(&xlb->master_priority, 0x11111111);
+
+#if defined(CONFIG_SYS_XLB_PIPELINING)
+	/* Enable piplining */
+	clrbits_be32(&xlb->config, (1 << 31));
+#endif
+
+#if defined(CONFIG_WATCHDOG)
+	/* Charge the watchdog timer - prescaler = 64k, count = 64k*/
+	out_be32(&gpt0->cir, 0x0000ffff);
+	out_be32(&gpt0->emsr, 0x9004);	/* wden|ce|timer_ms */
+
+	reset_5xxx_watchdog();
+#endif /* CONFIG_WATCHDOG */
+}
+
+/*
+ * initialize higher level parts of CPU like time base and timers
+ */
+int cpu_init_r (void)
+{
+	volatile struct mpc5xxx_intr *intr =
+		(struct mpc5xxx_intr *) MPC5XXX_ICTL;
+
+	/* mask all interrupts */
+	out_be32(&intr->per_mask, 0xffffff00);
+	setbits_be32(&intr->main_mask, 0x0001ffff);
+	clrbits_be32(&intr->ctrl, 0x00000f00);
+	/* route critical ints to normal ints */
+	setbits_be32(&intr->ctrl, 0x00000001);
+
+#if defined(CONFIG_CMD_NET) && defined(CONFIG_MPC5xxx_FEC)
+	/* load FEC microcode */
+	loadtask(0, 2);
+#endif
+
+	return (0);
+}
diff --git a/arch/powerpc/cpu/mpc5xxx/firmware_sc_task_bestcomm.impl.S b/arch/powerpc/cpu/mpc5xxx/firmware_sc_task_bestcomm.impl.S
new file mode 100644
index 0000000000..00c23121ac
--- /dev/null
+++ b/arch/powerpc/cpu/mpc5xxx/firmware_sc_task_bestcomm.impl.S
@@ -0,0 +1,359 @@ 
+/*
+ * Copyright (C) 2001, Software Center, Motorola China.
+ *
+ * This file contains microcode for the FEC controller of the MPC5200 CPU.
+ */
+
+#include <config.h>
+
+/* sas/sccg, gas target */
+.section        smartdmaInitData,"aw",@progbits	/* Initialized data for task variables */
+.section        smartdmaTaskTable,"aw",@progbits	/* Task tables */
+.align  9
+.globl taskTable
+taskTable:
+.globl scEthernetRecv_Entry
+scEthernetRecv_Entry:		/* Task 0 */
+.long   scEthernetRecv_TDT - taskTable	/* Task 0 Descriptor Table */
+.long   scEthernetRecv_TDT - taskTable + 0x000000a4
+.long   scEthernetRecv_VarTab - taskTable	/* Task 0 Variable Table */
+.long   scEthernetRecv_FDT - taskTable + 0x03	/* Task 0 Function Descriptor Table & Flags */
+.long   0x00000000
+.long   0x00000000
+.long   scEthernetRecv_CSave - taskTable	/* Task 0 context save space */
+.long   CONFIG_SYS_MBAR
+.globl scEthernetXmit_Entry
+scEthernetXmit_Entry:		/* Task 1 */
+.long   scEthernetXmit_TDT - taskTable	/* Task 1 Descriptor Table */
+.long   scEthernetXmit_TDT - taskTable + 0x000000d0
+.long   scEthernetXmit_VarTab - taskTable	/* Task 1 Variable Table */
+.long   scEthernetXmit_FDT - taskTable + 0x03	/* Task 1 Function Descriptor Table & Flags */
+.long   0x00000000
+.long   0x00000000
+.long   scEthernetXmit_CSave - taskTable	/* Task 1 context save space */
+.long   CONFIG_SYS_MBAR
+
+
+.globl scEthernetRecv_TDT
+scEthernetRecv_TDT:	/* Task 0 Descriptor Table */
+.long   0xc4c50000	/* 0000:  LCDEXT: idx0 = var9 + var10; idx0 once var0; idx0 += inc0 */
+.long   0x84c5e000	/* 0004:  LCD: idx1 = var9 + var11; ; idx1 += inc0 */
+.long   0x10001f08	/* 0008:    DRD1A: var7 = idx1; FN=0 MORE init=0 WS=0 RS=0 */
+.long   0x10000380	/* 000C:    DRD1A: var0 = *idx0; FN=0 MORE init=0 WS=0 RS=0 */
+.long   0x00000f88	/* 0010:    DRD1A: var3 = *idx1; FN=0 init=0 WS=0 RS=0 */
+.long   0x81980000	/* 0014:  LCD: idx0 = var3; idx0 once var0; idx0 += inc0 */
+.long   0x10000780	/* 0018:    DRD1A: var1 = *idx0; FN=0 MORE init=0 WS=0 RS=0 */
+.long   0x60000000	/* 001C:    DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */
+.long   0x010cf04c	/* 0020:    DRD2B1: var4 = EU3(); EU3(var1,var12)  */
+.long   0x82180349	/* 0024:  LCD: idx0 = var4; idx0 != var13; idx0 += inc1 */
+.long   0x81c68004	/* 0028:    LCD: idx1 = var3 + var13 + 4; idx1 once var0; idx1 += inc0 */
+.long   0x70000000	/* 002C:      DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */
+.long   0x018cf04e	/* 0030:      DRD2B1: var6 = EU3(); EU3(var1,var14)  */
+.long   0x70000000	/* 0034:      DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */
+.long   0x020cf04f	/* 0038:      DRD2B1: var8 = EU3(); EU3(var1,var15)  */
+.long   0x00000b88	/* 003C:      DRD1A: var2 = *idx1; FN=0 init=0 WS=0 RS=0 */
+.long   0x8000d184	/* 0040:    LCDEXT: idx1 = 0xf0003184; ; */
+.long   0xc6990452	/* 0044:    LCDEXT: idx2 = var13; idx2 < var17; idx2 += inc2 */
+.long   0x81486010	/* 0048:    LCD: idx3 = var2 + var16; ; idx3 += inc2 */
+.long   0x006acf88	/* 004C:      DRD1A: *idx3 = *idx1; FN=0 init=3 WS=1 RS=1 */
+.long   0x8000d184	/* 0050:    LCDEXT: idx1 = 0xf0003184; ; */
+.long   0x86810492	/* 0054:    LCD: idx2 = var13, idx3 = var2; idx2 < var18; idx2 += inc2, idx3 += inc2 */
+.long   0x006acf88	/* 0058:      DRD1A: *idx3 = *idx1; FN=0 init=3 WS=1 RS=1 */
+.long   0x8000d184	/* 005C:    LCDEXT: idx1 = 0xf0003184; ; */
+.long   0x868184d2	/* 0060:    LCD: idx2 = var13, idx3 = var3; idx2 < var19; idx2 += inc2, idx3 += inc2 */
+.long   0x000acf88	/* 0064:      DRD1A: *idx3 = *idx1; FN=0 init=0 WS=1 RS=1 */
+.long   0xc318839b	/* 0068:    LCDEXT: idx1 = var6; idx1 == var14; idx1 += inc3 */
+.long   0x80190000	/* 006C:    LCD: idx2 = var0; idx2 once var0; idx2 += inc0 */
+.long   0x04008468	/* 0070:      DRD1A: idx1 = var13; FN=0 INT init=0 WS=0 RS=0 */
+.long   0xc4038358	/* 0074:    LCDEXT: idx1 = var8, idx2 = var7; idx1 == var13; idx1 += inc3, idx2 += inc0 */
+.long   0x81c50000	/* 0078:    LCD: idx3 = var3 + var10; idx3 once var0; idx3 += inc0 */
+.long   0x1000cb18	/* 007C:      DRD1A: *idx2 = idx3; FN=0 MORE init=0 WS=0 RS=0 */
+.long   0x00000f18	/* 0080:      DRD1A: var3 = idx3; FN=0 init=0 WS=0 RS=0 */
+.long   0xc4188364	/* 0084:    LCDEXT: idx1 = var8; idx1 > var13; idx1 += inc4 */
+.long   0x83990000	/* 0088:    LCD: idx2 = var7; idx2 once var0; idx2 += inc0 */
+.long   0x10000c00	/* 008C:      DRD1A: var3 = var0; FN=0 MORE init=0 WS=0 RS=0 */
+.long   0x0000c800	/* 0090:      DRD1A: *idx2 = var0; FN=0 init=0 WS=0 RS=0 */
+.long   0x81988000	/* 0094:    LCD: idx1 = var3; idx1 once var0; idx1 += inc0 */
+.long   0x10000788	/* 0098:      DRD1A: var1 = *idx1; FN=0 MORE init=0 WS=0 RS=0 */
+.long   0x60000000	/* 009C:      DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */
+.long   0x080cf04c	/* 00A0:      DRD2B1: idx0 = EU3(); EU3(var1,var12)  */
+.long   0x000001f8	/* 00A4(:0):    NOP */
+
+
+.globl scEthernetXmit_TDT
+scEthernetXmit_TDT:	/* Task 1 Descriptor Table */
+.long   0x80024800	/* 0000:  LCDEXT: idx0 = 0xf0008800; ; */
+.long   0x85c60004	/* 0004:  LCD: idx1 = var11 + var12 + 4; idx1 once var0; idx1 += inc0 */
+.long   0x10002308	/* 0008:    DRD1A: var8 = idx1; FN=0 MORE init=0 WS=0 RS=0 */
+.long   0x10000f88	/* 000C:    DRD1A: var3 = *idx1; FN=0 MORE init=0 WS=0 RS=0 */
+.long   0x00000380	/* 0010:    DRD1A: var0 = *idx0; FN=0 init=0 WS=0 RS=0 */
+.long   0x81980000	/* 0014:  LCD: idx0 = var3; idx0 once var0; idx0 += inc0 */
+.long   0x10000780	/* 0018:    DRD1A: var1 = *idx0; FN=0 MORE init=0 WS=0 RS=0 */
+.long   0x60000000	/* 001C:    DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */
+.long   0x024cf04d	/* 0020:    DRD2B1: var9 = EU3(); EU3(var1,var13)  */
+.long   0x84980309	/* 0024:  LCD: idx0 = var9; idx0 != var12; idx0 += inc1 */
+.long   0xc0004003	/* 0028:    LCDEXT: idx1 = 0x00000003; ; */
+.long   0x81c60004	/* 002C:    LCD: idx2 = var3 + var12 + 4; idx2 once var0; idx2 += inc0 */
+.long   0x70000000	/* 0030:      DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */
+.long   0x010cf04e	/* 0034:      DRD2B1: var4 = EU3(); EU3(var1,var14)  */
+.long   0x70000000	/* 0038:      DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */
+.long   0x014cf04f	/* 003C:      DRD2B1: var5 = EU3(); EU3(var1,var15)  */
+.long   0x70000000	/* 0040:      DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */
+.long   0x028cf050	/* 0044:      DRD2B1: var10 = EU3(); EU3(var1,var16)  */
+.long   0x70000000	/* 0048:      DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT MORE init=0 WS=0 RS=0 */
+.long   0x018cf051	/* 004C:      DRD2B1: var6 = EU3(); EU3(var1,var17)  */
+.long   0x10000b90	/* 0050:      DRD1A: var2 = *idx2; FN=0 MORE init=0 WS=0 RS=0 */
+.long   0x60000000	/* 0054:      DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */
+.long   0x01ccf0a1	/* 0058:      DRD2B1: var7 = EU3(); EU3(var2,idx1)  */
+.long   0xc2988312	/* 005C:    LCDEXT: idx1 = var5; idx1 > var12; idx1 += inc2 */
+.long   0x83490000	/* 0060:    LCD: idx2 = var6 + var18; idx2 once var0; idx2 += inc0 */
+.long   0x00001b10	/* 0064:      DRD1A: var6 = idx2; FN=0 init=0 WS=0 RS=0 */
+.long   0x8000d1a4	/* 0068:    LCDEXT: idx1 = 0xf00031a4; ; */
+.long   0x8301031c	/* 006C:    LCD: idx2 = var6, idx3 = var2; idx2 > var12; idx2 += inc3, idx3 += inc4 */
+.long   0x008ac798	/* 0070:      DRD1A: *idx1 = *idx3; FN=0 init=4 WS=1 RS=1 */
+.long   0x8000d1a4	/* 0074:    LCDEXT: idx1 = 0xf00031a4; ; */
+.long   0xc1430000	/* 0078:    LCDEXT: idx2 = var2 + var6; idx2 once var0; idx2 += inc0 */
+.long   0x82998312	/* 007C:    LCD: idx3 = var5; idx3 > var12; idx3 += inc2 */
+.long   0x088ac790	/* 0080:      DRD1A: *idx1 = *idx2; FN=0 TFD init=4 WS=1 RS=1 */
+.long   0x81988000	/* 0084:    LCD: idx1 = var3; idx1 once var0; idx1 += inc0 */
+.long   0x60000001	/* 0088:      DRD2A: EU0=0 EU1=0 EU2=0 EU3=1 EXT init=0 WS=0 RS=0 */
+.long   0x0c4cfc4d	/* 008C:      DRD2B1: *idx1 = EU3(); EU3(*idx1,var13)  */
+.long   0xc21883ad	/* 0090:    LCDEXT: idx1 = var4; idx1 == var14; idx1 += inc5 */
+.long   0x80190000	/* 0094:    LCD: idx2 = var0; idx2 once var0; idx2 += inc0 */
+.long   0x04008460	/* 0098:      DRD1A: idx1 = var12; FN=0 INT init=0 WS=0 RS=0 */
+.long   0xc4052305	/* 009C:    LCDEXT: idx1 = var8, idx2 = var10; idx2 == var12; idx1 += inc0, idx2 += inc5 */
+.long   0x81c98000	/* 00A0:    LCD: idx3 = var3 + var19; idx3 once var0; idx3 += inc0 */
+.long   0x1000c718	/* 00A4:      DRD1A: *idx1 = idx3; FN=0 MORE init=0 WS=0 RS=0 */
+.long   0x00000f18	/* 00A8:      DRD1A: var3 = idx3; FN=0 init=0 WS=0 RS=0 */
+.long   0xc4188000	/* 00AC:    LCDEXT: idx1 = var8; idx1 once var0; idx1 += inc0 */
+.long   0x85190312	/* 00B0:    LCD: idx2 = var10; idx2 > var12; idx2 += inc2 */
+.long   0x10000c00	/* 00B4:      DRD1A: var3 = var0; FN=0 MORE init=0 WS=0 RS=0 */
+.long   0x1000c400	/* 00B8:      DRD1A: *idx1 = var0; FN=0 MORE init=0 WS=0 RS=0 */
+.long   0x00008860	/* 00BC:      DRD1A: idx2 = var12; FN=0 init=0 WS=0 RS=0 */
+.long   0x81988000	/* 00C0:    LCD: idx1 = var3; idx1 once var0; idx1 += inc0 */
+.long   0x10000788	/* 00C4:      DRD1A: var1 = *idx1; FN=0 MORE init=0 WS=0 RS=0 */
+.long   0x60000000	/* 00C8:      DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=0 WS=0 RS=0 */
+.long   0x080cf04d	/* 00CC:      DRD2B1: idx0 = EU3(); EU3(var1,var13)  */
+.long   0x000001f8	/* 00D0(:0):    NOP */
+
+.align  8
+
+.globl scEthernetRecv_VarTab
+scEthernetRecv_VarTab:	/* Task 0 Variable Table */
+.long   0x00000000	/* var[0] */
+.long   0x00000000	/* var[1] */
+.long   0x00000000	/* var[2] */
+.long   0x00000000	/* var[3] */
+.long   0x00000000	/* var[4] */
+.long   0x00000000	/* var[5] */
+.long   0x00000000	/* var[6] */
+.long   0x00000000	/* var[7] */
+.long   0x00000000	/* var[8] */
+.long   (CONFIG_SYS_MBAR + 0x8800)	/* var[9] */
+.long   0x00000008	/* var[10] */
+.long   0x0000000c	/* var[11] */
+.long   0x80000000	/* var[12] */
+.long   0x00000000	/* var[13] */
+.long   0x10000000	/* var[14] */
+.long   0x20000000	/* var[15] */
+.long   0x000005e4	/* var[16] */
+.long   0x0000000e	/* var[17] */
+.long   0x000005e0	/* var[18] */
+.long   0x00000004	/* var[19] */
+.long   0x00000000	/* var[20] */
+.long   0x00000000	/* var[21] */
+.long   0x00000000	/* var[22] */
+.long   0x00000000	/* var[23] */
+.long   0x00000000	/* inc[0] */
+.long   0x60000000	/* inc[1] */
+.long   0x20000001	/* inc[2] */
+.long   0x80000000	/* inc[3] */
+.long   0x40000000	/* inc[4] */
+.long   0x00000000	/* inc[5] */
+.long   0x00000000	/* inc[6] */
+.long   0x00000000	/* inc[7] */
+
+.align  8
+
+.globl scEthernetXmit_VarTab
+scEthernetXmit_VarTab:	/* Task 1 Variable Table */
+.long   0x00000000	/* var[0] */
+.long   0x00000000	/* var[1] */
+.long   0x00000000	/* var[2] */
+.long   0x00000000	/* var[3] */
+.long   0x00000000	/* var[4] */
+.long   0x00000000	/* var[5] */
+.long   0x00000000	/* var[6] */
+.long   0x00000000	/* var[7] */
+.long   0x00000000	/* var[8] */
+.long   0x00000000	/* var[9] */
+.long   0x00000000	/* var[10] */
+.long   (CONFIG_SYS_MBAR + 0x8800)	/* var[11] */
+.long   0x00000000	/* var[12] */
+.long   0x80000000	/* var[13] */
+.long   0x10000000	/* var[14] */
+.long   0x08000000	/* var[15] */
+.long   0x20000000	/* var[16] */
+.long   0x0000ffff	/* var[17] */
+.long   0xffffffff	/* var[18] */
+.long   0x00000008	/* var[19] */
+.long   0x00000000	/* var[20] */
+.long   0x00000000	/* var[21] */
+.long   0x00000000	/* var[22] */
+.long   0x00000000	/* var[23] */
+.long   0x00000000	/* inc[0] */
+.long   0x60000000	/* inc[1] */
+.long   0x40000000	/* inc[2] */
+.long   0x4000ffff	/* inc[3] */
+.long   0xe0000001	/* inc[4] */
+.long   0x80000000	/* inc[5] */
+.long   0x00000000	/* inc[6] */
+.long   0x00000000	/* inc[7] */
+
+.align  8
+
+.globl scEthernetRecv_FDT
+scEthernetRecv_FDT:	/* Task 0 Function Descriptor Table */
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x21800000	/* and(), EU# 3 */
+.long   0x21400000	/* andn(), EU# 3 */
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+
+.align  8
+
+.globl scEthernetXmit_FDT
+scEthernetXmit_FDT:	/* Task 1 Function Descriptor Table */
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x21800000	/* and(), EU# 3 */
+.long   0x21400000	/* andn(), EU# 3 */
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+.long   0x00000000
+
+
+.globl scEthernetRecv_CSave
+scEthernetRecv_CSave:	/* Task 0 context save space */
+.space  128, 0x0
+
+
+.globl scEthernetXmit_CSave
+scEthernetXmit_CSave:	/* Task 1 context save space */
+.space  128, 0x0
diff --git a/arch/powerpc/cpu/mpc5xxx/ide.c b/arch/powerpc/cpu/mpc5xxx/ide.c
new file mode 100644
index 0000000000..d1f4349184
--- /dev/null
+++ b/arch/powerpc/cpu/mpc5xxx/ide.c
@@ -0,0 +1,75 @@ 
+/*
+ * (C) Copyright 2004
+ * Pierre AUBERT, Staubli Faverges, <p.aubert@staubli.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Init is derived from Linux code.
+ */
+#include <common.h>
+
+#if defined(CONFIG_IDE)
+#include <mpc5xxx.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define CALC_TIMING(t) (t + period - 1) / period
+
+#ifdef CONFIG_IDE_RESET
+extern void init_ide_reset (void);
+#endif
+
+int ide_preinit (void)
+{
+	long period, t0, t1, t2_8, t2_16, t4, ta;
+	vu_long reg;
+	struct mpc5xxx_sdma *psdma = (struct mpc5xxx_sdma *) MPC5XXX_SDMA;
+
+	reg = *(vu_long *) MPC5XXX_GPS_PORT_CONFIG;
+#if defined(CONFIG_SYS_ATA_CS_ON_I2C2)
+	/* ATA cs0/1 on i2c2 clk/io */
+	reg = (reg & ~0x03000000ul) | 0x02000000ul;
+#elif defined(CONFIG_SYS_ATA_CS_ON_TIMER01)
+	/* ATA cs0/1 on Timer 0/1 */
+	reg = (reg & ~0x03000000ul) | 0x03000000ul;
+#else
+	/* ATA cs0/1 on Local Plus cs4/5 */
+	reg = (reg & ~0x03000000ul) | 0x01000000ul;
+#endif	/* CONFIG_TOTAL5200 */
+	*(vu_long *) MPC5XXX_GPS_PORT_CONFIG = reg;
+
+	/* All sample codes do that... */
+	*(vu_long *) MPC5XXX_ATA_SHARE_COUNT = 0;
+
+	/* Configure and reset host */
+	*(vu_long *) MPC5XXX_ATA_HOST_CONFIG = MPC5xxx_ATA_HOSTCONF_IORDY |
+		MPC5xxx_ATA_HOSTCONF_SMR | MPC5xxx_ATA_HOSTCONF_FR;
+	udelay (10);
+	*(vu_long *) MPC5XXX_ATA_HOST_CONFIG = MPC5xxx_ATA_HOSTCONF_IORDY;
+
+	/* Disable prefetch on Commbus */
+	psdma->PtdCntrl |= 1;
+
+	/* Init timings : we use PIO mode 0 timings */
+	period = 1000000000 / gd->arch.ipb_clk;	/* period in ns */
+
+	t0 = CALC_TIMING (600);
+	t2_8 = CALC_TIMING (290);
+	t2_16 = CALC_TIMING (165);
+	reg = (t0 << 24) | (t2_8 << 16) | (t2_16 << 8);
+	*(vu_long *) MPC5XXX_ATA_PIO1 = reg;
+
+	t4 = CALC_TIMING (30);
+	t1 = CALC_TIMING (70);
+	ta = CALC_TIMING (35);
+	reg = (t4 << 24) | (t1 << 16) | (ta << 8);
+
+	*(vu_long *) MPC5XXX_ATA_PIO2 = reg;
+
+#ifdef CONFIG_IDE_RESET
+	init_ide_reset ();
+#endif /* CONFIG_IDE_RESET */
+
+	return (0);
+}
+#endif
diff --git a/arch/powerpc/cpu/mpc5xxx/interrupts.c b/arch/powerpc/cpu/mpc5xxx/interrupts.c
new file mode 100644
index 0000000000..9121fa0cd0
--- /dev/null
+++ b/arch/powerpc/cpu/mpc5xxx/interrupts.c
@@ -0,0 +1,330 @@ 
+/*
+ * (C) Copyright 2006
+ * Detlev Zundel, DENX Software Engineering, dzu@denx.de
+ *
+ * (C) Copyright -2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2001
+ * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/* this section was ripped out of arch/powerpc/syslib/mpc52xx_pic.c in the
+ * Linux 2.6 source with the following copyright.
+ *
+ * Based on (well, mostly copied from) the code from the 2.4 kernel by
+ * Dale Farnsworth <dfarnsworth@mvista.com> and Kent Borg.
+ *
+ * Copyright (C) 2004 Sylvain Munaut <tnt@246tNt.com>
+ * Copyright (C) 2003 Montavista Software, Inc
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <command.h>
+
+struct irq_action {
+	interrupt_handler_t *handler;
+	void *arg;
+	ulong count;
+};
+
+static struct irq_action irq_handlers[NR_IRQS];
+
+static struct mpc5xxx_intr *intr;
+static struct mpc5xxx_sdma *sdma;
+
+static void mpc5xxx_ic_disable(unsigned int irq)
+{
+	u32 val;
+
+	if (irq == MPC5XXX_IRQ0) {
+		val = in_be32(&intr->ctrl);
+		val &= ~(1 << 11);
+		out_be32(&intr->ctrl, val);
+	} else if (irq < MPC5XXX_IRQ1) {
+		BUG();
+	} else if (irq <= MPC5XXX_IRQ3) {
+		val = in_be32(&intr->ctrl);
+		val &= ~(1 << (10 - (irq - MPC5XXX_IRQ1)));
+		out_be32(&intr->ctrl, val);
+	} else if (irq < MPC5XXX_SDMA_IRQ_BASE) {
+		val = in_be32(&intr->main_mask);
+		val |= 1 << (16 - (irq - MPC5XXX_MAIN_IRQ_BASE));
+		out_be32(&intr->main_mask, val);
+	} else if (irq < MPC5XXX_PERP_IRQ_BASE) {
+		val = in_be32(&sdma->IntMask);
+		val |= 1 << (irq - MPC5XXX_SDMA_IRQ_BASE);
+		out_be32(&sdma->IntMask, val);
+	} else {
+		val = in_be32(&intr->per_mask);
+		val |= 1 << (31 - (irq - MPC5XXX_PERP_IRQ_BASE));
+		out_be32(&intr->per_mask, val);
+	}
+}
+
+static void mpc5xxx_ic_enable(unsigned int irq)
+{
+	u32 val;
+
+	if (irq == MPC5XXX_IRQ0) {
+		val = in_be32(&intr->ctrl);
+		val |= 1 << 11;
+		out_be32(&intr->ctrl, val);
+	} else if (irq < MPC5XXX_IRQ1) {
+		BUG();
+	} else if (irq <= MPC5XXX_IRQ3) {
+		val = in_be32(&intr->ctrl);
+		val |= 1 << (10 - (irq - MPC5XXX_IRQ1));
+		out_be32(&intr->ctrl, val);
+	} else if (irq < MPC5XXX_SDMA_IRQ_BASE) {
+		val = in_be32(&intr->main_mask);
+		val &= ~(1 << (16 - (irq - MPC5XXX_MAIN_IRQ_BASE)));
+		out_be32(&intr->main_mask, val);
+	} else if (irq < MPC5XXX_PERP_IRQ_BASE) {
+		val = in_be32(&sdma->IntMask);
+		val &= ~(1 << (irq - MPC5XXX_SDMA_IRQ_BASE));
+		out_be32(&sdma->IntMask, val);
+	} else {
+		val = in_be32(&intr->per_mask);
+		val &= ~(1 << (31 - (irq - MPC5XXX_PERP_IRQ_BASE)));
+		out_be32(&intr->per_mask, val);
+	}
+}
+
+static void mpc5xxx_ic_ack(unsigned int irq)
+{
+	u32 val;
+
+	/*
+	 * Only some irqs are reset here, others in interrupting hardware.
+	 */
+
+	switch (irq) {
+	case MPC5XXX_IRQ0:
+		val = in_be32(&intr->ctrl);
+		val |= 0x08000000;
+		out_be32(&intr->ctrl, val);
+		break;
+	case MPC5XXX_CCS_IRQ:
+		val = in_be32(&intr->enc_status);
+		val |= 0x00000400;
+		out_be32(&intr->enc_status, val);
+		break;
+	case MPC5XXX_IRQ1:
+		val = in_be32(&intr->ctrl);
+		val |= 0x04000000;
+		out_be32(&intr->ctrl, val);
+		break;
+	case MPC5XXX_IRQ2:
+		val = in_be32(&intr->ctrl);
+		val |= 0x02000000;
+		out_be32(&intr->ctrl, val);
+		break;
+	case MPC5XXX_IRQ3:
+		val = in_be32(&intr->ctrl);
+		val |= 0x01000000;
+		out_be32(&intr->ctrl, val);
+		break;
+	default:
+		if (irq >= MPC5XXX_SDMA_IRQ_BASE
+		    && irq < (MPC5XXX_SDMA_IRQ_BASE + MPC5XXX_SDMA_IRQ_NUM)) {
+			out_be32(&sdma->IntPend,
+				 1 << (irq - MPC5XXX_SDMA_IRQ_BASE));
+		}
+		break;
+	}
+}
+
+static void mpc5xxx_ic_disable_and_ack(unsigned int irq)
+{
+	mpc5xxx_ic_disable(irq);
+	mpc5xxx_ic_ack(irq);
+}
+
+static void mpc5xxx_ic_end(unsigned int irq)
+{
+	mpc5xxx_ic_enable(irq);
+}
+
+void mpc5xxx_init_irq(void)
+{
+	u32 intr_ctrl;
+
+	/* Remap the necessary zones */
+	intr = (struct mpc5xxx_intr *)(MPC5XXX_ICTL);
+	sdma = (struct mpc5xxx_sdma *)(MPC5XXX_SDMA);
+
+	/* Disable all interrupt sources. */
+	out_be32(&sdma->IntPend, 0xffffffff);	/* 1 means clear pending */
+	out_be32(&sdma->IntMask, 0xffffffff);	/* 1 means disabled */
+	out_be32(&intr->per_mask, 0x7ffffc00);	/* 1 means disabled */
+	out_be32(&intr->main_mask, 0x00010fff);	/* 1 means disabled */
+	intr_ctrl = in_be32(&intr->ctrl);
+	intr_ctrl |= 0x0f000000 |	/* clear IRQ 0-3 */
+	    0x00ff0000 |	/* IRQ 0-3 level sensitive low active */
+	    0x00001000 |	/* MEE master external enable */
+	    0x00000000 |	/* 0 means disable IRQ 0-3 */
+	    0x00000001;		/* CEb route critical normally */
+	out_be32(&intr->ctrl, intr_ctrl);
+
+	/* Zero a bunch of the priority settings.  */
+	out_be32(&intr->per_pri1, 0);
+	out_be32(&intr->per_pri2, 0);
+	out_be32(&intr->per_pri3, 0);
+	out_be32(&intr->main_pri1, 0);
+	out_be32(&intr->main_pri2, 0);
+}
+
+int mpc5xxx_get_irq(struct pt_regs *regs)
+{
+	u32 status;
+	int irq = -1;
+
+	status = in_be32(&intr->enc_status);
+
+	if (status & 0x00000400) {	/* critical */
+		irq = (status >> 8) & 0x3;
+		if (irq == 2)	/* high priority peripheral */
+			goto peripheral;
+		irq += MPC5XXX_CRIT_IRQ_BASE;
+	} else if (status & 0x00200000) {	/* main */
+		irq = (status >> 16) & 0x1f;
+		if (irq == 4)	/* low priority peripheral */
+			goto peripheral;
+		irq += MPC5XXX_MAIN_IRQ_BASE;
+	} else if (status & 0x20000000) {	/* peripheral */
+	      peripheral:
+		irq = (status >> 24) & 0x1f;
+		if (irq == 0) {	/* bestcomm */
+			status = in_be32(&sdma->IntPend);
+			irq = ffs(status) + MPC5XXX_SDMA_IRQ_BASE - 1;
+		} else
+			irq += MPC5XXX_PERP_IRQ_BASE;
+	}
+
+	return irq;
+}
+
+/****************************************************************************/
+
+int interrupt_init_cpu(ulong * decrementer_count)
+{
+	*decrementer_count = get_tbclk() / CONFIG_SYS_HZ;
+
+	mpc5xxx_init_irq();
+
+	return (0);
+}
+
+/****************************************************************************/
+
+/*
+ * Handle external interrupts
+ */
+void external_interrupt(struct pt_regs *regs)
+{
+	int irq, unmask = 1;
+
+	irq = mpc5xxx_get_irq(regs);
+
+	mpc5xxx_ic_disable_and_ack(irq);
+
+	enable_interrupts();
+
+	if (irq_handlers[irq].handler != NULL)
+		(*irq_handlers[irq].handler) (irq_handlers[irq].arg);
+	else {
+		printf("\nBogus External Interrupt IRQ %d\n", irq);
+		/*
+		 * turn off the bogus interrupt, otherwise it
+		 * might repeat forever
+		 */
+		unmask = 0;
+	}
+
+	if (unmask)
+		mpc5xxx_ic_end(irq);
+}
+
+void timer_interrupt_cpu(struct pt_regs *regs)
+{
+	/* nothing to do here */
+	return;
+}
+
+/****************************************************************************/
+
+/*
+ * Install and free a interrupt handler.
+ */
+
+void irq_install_handler(int irq, interrupt_handler_t * handler, void *arg)
+{
+	if (irq < 0 || irq >= NR_IRQS) {
+		printf("irq_install_handler: bad irq number %d\n", irq);
+		return;
+	}
+
+	if (irq_handlers[irq].handler != NULL)
+		printf("irq_install_handler: 0x%08lx replacing 0x%08lx\n",
+		       (ulong) handler, (ulong) irq_handlers[irq].handler);
+
+	irq_handlers[irq].handler = handler;
+	irq_handlers[irq].arg = arg;
+
+	mpc5xxx_ic_enable(irq);
+}
+
+void irq_free_handler(int irq)
+{
+	if (irq < 0 || irq >= NR_IRQS) {
+		printf("irq_free_handler: bad irq number %d\n", irq);
+		return;
+	}
+
+	mpc5xxx_ic_disable(irq);
+
+	irq_handlers[irq].handler = NULL;
+	irq_handlers[irq].arg = NULL;
+}
+
+/****************************************************************************/
+
+#if defined(CONFIG_CMD_IRQ)
+void do_irqinfo(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char * const argv[])
+{
+	int irq, re_enable;
+	u32 intr_ctrl;
+	char *irq_config[] = { "level sensitive, active high",
+		"edge sensitive, rising active edge",
+		"edge sensitive, falling active edge",
+		"level sensitive, active low"
+	};
+
+	re_enable = disable_interrupts();
+
+	intr_ctrl = in_be32(&intr->ctrl);
+	printf("Interrupt configuration:\n");
+
+	for (irq = 0; irq <= 3; irq++) {
+		printf("IRQ%d: %s\n", irq,
+		       irq_config[(intr_ctrl >> (22 - 2 * irq)) & 0x3]);
+	}
+
+	puts("\nInterrupt-Information:\n" "Nr  Routine   Arg       Count\n");
+
+	for (irq = 0; irq < NR_IRQS; irq++)
+		if (irq_handlers[irq].handler != NULL)
+			printf("%02d  %08lx  %08lx  %ld\n", irq,
+			       (ulong) irq_handlers[irq].handler,
+			       (ulong) irq_handlers[irq].arg,
+			       irq_handlers[irq].count);
+
+	if (re_enable)
+		enable_interrupts();
+}
+#endif
diff --git a/arch/powerpc/cpu/mpc5xxx/io.S b/arch/powerpc/cpu/mpc5xxx/io.S
new file mode 100644
index 0000000000..32641ed67f
--- /dev/null
+++ b/arch/powerpc/cpu/mpc5xxx/io.S
@@ -0,0 +1,112 @@ 
+/*
+ *  Copyright (C) 1998	Dan Malek <dmalek@jlc.net>
+ *  Copyright (C) 1999	Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
+ *  Copyright (C) 2001	Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ *			Andreas Heppel <aheppel@sysgo.de>
+ *  Copyright (C) 2003	Wolfgang Denk <wd@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <config.h>
+#include <ppc_asm.tmpl>
+
+/* ------------------------------------------------------------------------------- */
+/*  Function:     in8 */
+/*  Description:  Input 8 bits */
+/* ------------------------------------------------------------------------------- */
+	.globl  in8
+in8:
+	lbz     r3,0(r3)
+	sync
+	blr
+
+/* ------------------------------------------------------------------------------- */
+/*  Function:     in16 */
+/*  Description:  Input 16 bits */
+/* ------------------------------------------------------------------------------- */
+	.globl  in16
+in16:
+	lhz     r3,0(r3)
+	sync
+	blr
+
+/* ------------------------------------------------------------------------------- */
+/*  Function:     in16r */
+/*  Description:  Input 16 bits and byte reverse */
+/* ------------------------------------------------------------------------------- */
+	.globl  in16r
+in16r:
+	lhbrx   r3,0,r3
+	sync
+	blr
+
+/* ------------------------------------------------------------------------------- */
+/*  Function:     in32 */
+/*  Description:  Input 32 bits */
+/* ------------------------------------------------------------------------------- */
+	.globl  in32
+in32:
+	lwz     3,0(3)
+	sync
+	blr
+
+/* ------------------------------------------------------------------------------- */
+/*  Function:     in32r */
+/*  Description:  Input 32 bits and byte reverse */
+/* ------------------------------------------------------------------------------- */
+    .globl  in32r
+in32r:
+	lwbrx   r3,0,r3
+	sync
+	blr
+
+/* ------------------------------------------------------------------------------- */
+/*  Function:     out8 */
+/*  Description:  Output 8 bits */
+/* ------------------------------------------------------------------------------- */
+	.globl  out8
+out8:
+	stb     r4,0(r3)
+	sync
+	blr
+
+/* ------------------------------------------------------------------------------- */
+/*  Function:     out16 */
+/*  Description:  Output 16 bits */
+/* ------------------------------------------------------------------------------- */
+	.globl  out16
+out16:
+	sth     r4,0(r3)
+	sync
+	blr
+
+/* ------------------------------------------------------------------------------- */
+/*  Function:     out16r */
+/*  Description:  Byte reverse and output 16 bits */
+/* ------------------------------------------------------------------------------- */
+	.globl  out16r
+out16r:
+	sthbrx  r4,0,r3
+	sync
+	blr
+
+/* ------------------------------------------------------------------------------- */
+/*  Function:     out32 */
+/*  Description:  Output 32 bits */
+/* ------------------------------------------------------------------------------- */
+	.globl  out32
+out32:
+	stw     r4,0(r3)
+	sync
+	blr
+
+/* ------------------------------------------------------------------------------- */
+/*  Function:     out32r */
+/*  Description:  Byte reverse and output 32 bits */
+/* ------------------------------------------------------------------------------- */
+	.globl  out32r
+out32r:
+	stwbrx  r4,0,r3
+	sync
+	blr
diff --git a/arch/powerpc/cpu/mpc5xxx/loadtask.c b/arch/powerpc/cpu/mpc5xxx/loadtask.c
new file mode 100644
index 0000000000..47e7b596a6
--- /dev/null
+++ b/arch/powerpc/cpu/mpc5xxx/loadtask.c
@@ -0,0 +1,76 @@ 
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * This file is based on code
+ * (C) Copyright Motorola, Inc., 2000
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+
+/* BestComm/SmartComm microcode */
+extern int taskTable;
+
+void loadtask(int basetask, int tasks)
+{
+	int *sram = (int *)MPC5XXX_SRAM;
+	int *task_org = &taskTable;
+	unsigned int start, offset, end;
+	int i;
+
+#ifdef DEBUG
+	printf("basetask = %d, tasks = %d\n", basetask, tasks);
+	printf("task_org = 0x%08x\n", (unsigned int)task_org);
+#endif
+
+	/* setup TaskBAR register */
+	*(vu_long *)MPC5XXX_SDMA = MPC5XXX_SRAM;
+
+	/* relocate task table entries */
+	offset = (unsigned int)sram;
+	for (i = basetask; i < basetask + tasks; i++) {
+		sram[i * 8 + 0] = task_org[i * 8 + 0] + offset;
+		sram[i * 8 + 1] = task_org[i * 8 + 1] + offset;
+		sram[i * 8 + 2] = task_org[i * 8 + 2] + offset;
+		sram[i * 8 + 3] = task_org[i * 8 + 3] + offset;
+		sram[i * 8 + 4] = task_org[i * 8 + 4];
+		sram[i * 8 + 5] = task_org[i * 8 + 5];
+		sram[i * 8 + 6] = task_org[i * 8 + 6] + offset;
+		sram[i * 8 + 7] = task_org[i * 8 + 7];
+	}
+
+	/* relocate task descriptors */
+	start = (sram[basetask * 8] - (unsigned int)sram);
+	end = (sram[(basetask + tasks - 1) * 8 + 1] - (unsigned int)sram);
+
+#ifdef DEBUG
+	printf ("TDT start = 0x%08x, end = 0x%08x\n", start, end);
+#endif
+
+	start /= 4;
+	end /= 4;
+	for (i = start; i <= end; i++) {
+		sram[i] = task_org[i];
+	}
+
+	/* relocate variables */
+	start = (sram[basetask * 8 + 2] - (unsigned int)sram);
+	end = (sram[(basetask + tasks - 1) * 8 + 2] + 256 - (unsigned int)sram);
+	start /= 4;
+	end /= 4;
+	for (i = start; i < end; i++) {
+		sram[i] = task_org[i];
+	}
+
+	/* relocate function decriptors */
+	start = ((sram[basetask * 8 + 3] & 0xfffffffc) - (unsigned int)sram);
+	end = ((sram[(basetask + tasks - 1) * 8 + 3] & 0xfffffffc) + 256 - (unsigned int)sram);
+	start /= 4;
+	end /= 4;
+	for (i = start; i < end; i++) {
+		sram[i] = task_org[i];
+	}
+
+	asm volatile ("sync");
+}
diff --git a/arch/powerpc/cpu/mpc5xxx/pci_mpc5200.c b/arch/powerpc/cpu/mpc5xxx/pci_mpc5200.c
new file mode 100644
index 0000000000..70b7e6e6cb
--- /dev/null
+++ b/arch/powerpc/cpu/mpc5xxx/pci_mpc5200.c
@@ -0,0 +1,157 @@ 
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+
+#if defined(CONFIG_PCI)
+
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <pci.h>
+#include <mpc5xxx.h>
+
+/* System RAM mapped over PCI */
+#define CONFIG_PCI_MEMORY_BUS	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_PCI_MEMORY_PHYS	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_PCI_MEMORY_SIZE	(1024 * 1024 * 1024)
+
+/* PCIIWCR bit fields */
+#define IWCR_MEM	(0 << 3)
+#define IWCR_IO		(1 << 3)
+#define IWCR_READ	(0 << 1)
+#define IWCR_READLINE	(1 << 1)
+#define IWCR_READMULT	(2 << 1)
+#define IWCR_EN		(1 << 0)
+
+static int mpc5200_read_config_dword(struct pci_controller *hose,
+			      pci_dev_t dev, int offset, u32* value)
+{
+	*(volatile u32 *)MPC5XXX_PCI_CAR = (1 << 31) | dev | offset;
+	eieio();
+	udelay(10);
+	*value = in_le32((volatile u32 *)CONFIG_PCI_IO_PHYS);
+	eieio();
+	*(volatile u32 *)MPC5XXX_PCI_CAR = 0;
+	udelay(10);
+	return 0;
+}
+
+static int mpc5200_write_config_dword(struct pci_controller *hose,
+			      pci_dev_t dev, int offset, u32 value)
+{
+	*(volatile u32 *)MPC5XXX_PCI_CAR = (1 << 31) | dev | offset;
+	eieio();
+	udelay(10);
+	out_le32((volatile u32 *)CONFIG_PCI_IO_PHYS, value);
+	eieio();
+	*(volatile u32 *)MPC5XXX_PCI_CAR = 0;
+	udelay(10);
+	return 0;
+}
+
+void pci_mpc5xxx_init (struct pci_controller *hose)
+{
+	hose->first_busno = 0;
+	hose->last_busno = 0xff;
+
+	/* System space */
+	pci_set_region(hose->regions + 0,
+		       CONFIG_PCI_MEMORY_BUS,
+		       CONFIG_PCI_MEMORY_PHYS,
+		       CONFIG_PCI_MEMORY_SIZE,
+		       PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
+
+	/* PCI memory space */
+	pci_set_region(hose->regions + 1,
+		       CONFIG_PCI_MEM_BUS,
+		       CONFIG_PCI_MEM_PHYS,
+		       CONFIG_PCI_MEM_SIZE,
+		       PCI_REGION_MEM);
+
+	/* PCI IO space */
+	pci_set_region(hose->regions + 2,
+		       CONFIG_PCI_IO_BUS,
+		       CONFIG_PCI_IO_PHYS,
+		       CONFIG_PCI_IO_SIZE,
+		       PCI_REGION_IO);
+
+	hose->region_count = 3;
+
+	pci_register_hose(hose);
+
+	/* GPIO Multiplexing - enable PCI */
+	*(vu_long *)MPC5XXX_GPS_PORT_CONFIG &= ~(1 << 15);
+
+	/* Set host bridge as pci master and enable memory decoding */
+	*(vu_long *)MPC5XXX_PCI_CMD |=
+		PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
+
+	/* Set maximum latency timer */
+	*(vu_long *)MPC5XXX_PCI_CFG |= (0xf800);
+
+	/* Set cache line size */
+	*(vu_long *)MPC5XXX_PCI_CFG = (*(vu_long *)MPC5XXX_PCI_CFG & ~0xff) |
+		(CONFIG_SYS_CACHELINE_SIZE / 4);
+
+	/* Map MBAR to PCI space */
+	*(vu_long *)MPC5XXX_PCI_BAR0 = CONFIG_SYS_MBAR;
+	*(vu_long *)MPC5XXX_PCI_TBATR0 = CONFIG_SYS_MBAR | 1;
+
+	/* Map RAM to PCI space */
+	*(vu_long *)MPC5XXX_PCI_BAR1 = CONFIG_PCI_MEMORY_BUS | (1 << 3);
+	*(vu_long *)MPC5XXX_PCI_TBATR1 = CONFIG_PCI_MEMORY_PHYS | 1;
+
+	/* Park XLB on PCI */
+	*(vu_long *)(MPC5XXX_XLBARB + 0x40) &= ~((7 << 8) | (3 << 5));
+	*(vu_long *)(MPC5XXX_XLBARB + 0x40) |= (3 << 8) | (3 << 5);
+
+	/* Disable interrupts from PCI controller */
+	*(vu_long *)MPC5XXX_PCI_GSCR &= ~(7 << 12);
+	*(vu_long *)MPC5XXX_PCI_ICR  &= ~(7 << 24);
+
+	/* Set PCI retry counter to 0 = infinite retry. */
+	/* The default of 255 is too short for slow devices. */
+	*(vu_long *)MPC5XXX_PCI_ICR &= 0xFFFFFF00;
+
+	/* Disable initiator windows */
+	*(vu_long *)MPC5XXX_PCI_IWCR = 0;
+
+	/* Map PCI memory to physical space */
+	*(vu_long *)MPC5XXX_PCI_IW0BTAR = CONFIG_PCI_MEM_PHYS |
+		(((CONFIG_PCI_MEM_SIZE - 1) >> 8) & 0x00ff0000) |
+		(CONFIG_PCI_MEM_BUS >> 16);
+	*(vu_long *)MPC5XXX_PCI_IWCR |= (IWCR_MEM | IWCR_READ | IWCR_EN) << 24;
+
+	/* Map PCI I/O to physical space */
+	*(vu_long *)MPC5XXX_PCI_IW1BTAR = CONFIG_PCI_IO_PHYS |
+		(((CONFIG_PCI_IO_SIZE - 1) >> 8) & 0x00ff0000) |
+		(CONFIG_PCI_IO_BUS >> 16);
+	*(vu_long *)MPC5XXX_PCI_IWCR |= (IWCR_IO | IWCR_READ | IWCR_EN) << 16;
+
+	/* Reset the PCI bus */
+	*(vu_long *)MPC5XXX_PCI_GSCR |= 1;
+	udelay(1000);
+	*(vu_long *)MPC5XXX_PCI_GSCR &= ~1;
+	udelay(1000);
+
+	pci_set_ops(hose,
+		pci_hose_read_config_byte_via_dword,
+		pci_hose_read_config_word_via_dword,
+		mpc5200_read_config_dword,
+		pci_hose_write_config_byte_via_dword,
+		pci_hose_write_config_word_via_dword,
+		mpc5200_write_config_dword);
+
+	udelay(1000);
+
+#ifdef CONFIG_PCI_SCAN_SHOW
+	printf("PCI:   Bus Dev VenId DevId Class Int\n");
+#endif
+
+	hose->last_busno = pci_hose_scan(hose);
+}
+#endif /* CONFIG_PCI */
diff --git a/arch/powerpc/cpu/mpc5xxx/serial.c b/arch/powerpc/cpu/mpc5xxx/serial.c
new file mode 100644
index 0000000000..bccdcf7973
--- /dev/null
+++ b/arch/powerpc/cpu/mpc5xxx/serial.c
@@ -0,0 +1,265 @@ 
+/*
+ * (C) Copyright 2000 - 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Hacked for MPC8260 by Murray.Jensen@cmst.csiro.au, 19-Oct-00, with
+ * changes based on the file arch/powerpc/mbxboot/m8260_tty.c from the
+ * Linux/PPC sources (m8260_tty.c had no copyright info in it).
+ *
+ * Martin Krause, 8 Jun 2006
+ * Added SERIAL_MULTI support
+ */
+
+/*
+ * Minimal serial functions needed to use one of the PSC ports
+ * as serial console interface.
+ */
+
+#include <common.h>
+#include <linux/compiler.h>
+#include <mpc5xxx.h>
+#include <serial.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_PSC_CONSOLE)
+
+#if CONFIG_PSC_CONSOLE == 1
+#define PSC_BASE MPC5XXX_PSC1
+#elif CONFIG_PSC_CONSOLE == 2
+#define PSC_BASE MPC5XXX_PSC2
+#elif CONFIG_PSC_CONSOLE == 3
+#define PSC_BASE MPC5XXX_PSC3
+#elif CONFIG_PSC_CONSOLE == 4
+#define PSC_BASE MPC5XXX_PSC4
+#elif CONFIG_PSC_CONSOLE == 5
+#define PSC_BASE MPC5XXX_PSC5
+#elif CONFIG_PSC_CONSOLE == 6
+#define PSC_BASE MPC5XXX_PSC6
+#else
+#error CONFIG_PSC_CONSOLE must be in 1 ... 6
+#endif
+
+#if defined(CONFIG_PSC_CONSOLE2)
+
+#if CONFIG_PSC_CONSOLE2 == 1
+#define PSC_BASE2 MPC5XXX_PSC1
+#elif CONFIG_PSC_CONSOLE2 == 2
+#define PSC_BASE2 MPC5XXX_PSC2
+#elif CONFIG_PSC_CONSOLE2 == 3
+#define PSC_BASE2 MPC5XXX_PSC3
+#elif CONFIG_PSC_CONSOLE2 == 4
+#define PSC_BASE2 MPC5XXX_PSC4
+#elif CONFIG_PSC_CONSOLE2 == 5
+#define PSC_BASE2 MPC5XXX_PSC5
+#elif CONFIG_PSC_CONSOLE2 == 6
+#define PSC_BASE2 MPC5XXX_PSC6
+#else
+#error CONFIG_PSC_CONSOLE2 must be in 1 ... 6
+#endif
+
+#endif
+
+int serial_init_dev (unsigned long dev_base)
+{
+	volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)dev_base;
+	unsigned long baseclk;
+	int div;
+
+	/* reset PSC */
+	psc->command = PSC_SEL_MODE_REG_1;
+
+	/* select clock sources */
+	psc->psc_clock_select = 0;
+	baseclk = (gd->arch.ipb_clk + 16) / 32;
+
+	/* switch to UART mode */
+	psc->sicr = 0;
+
+	/* configure parity, bit length and so on */
+	psc->mode = PSC_MODE_8_BITS | PSC_MODE_PARNONE;
+	psc->mode = PSC_MODE_ONE_STOP;
+
+	/* set up UART divisor */
+	div = (baseclk + (gd->baudrate/2)) / gd->baudrate;
+	psc->ctur = (div >> 8) & 0xff;
+	psc->ctlr = div & 0xff;
+
+	/* disable all interrupts */
+	psc->psc_imr = 0;
+
+	/* reset and enable Rx/Tx */
+	psc->command = PSC_RST_RX;
+	psc->command = PSC_RST_TX;
+	psc->command = PSC_RX_ENABLE | PSC_TX_ENABLE;
+
+	return (0);
+}
+
+void serial_putc_dev (unsigned long dev_base, const char c)
+{
+	volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)dev_base;
+
+	if (c == '\n')
+		serial_putc_dev (dev_base, '\r');
+
+	/* Wait for last character to go. */
+	while (!(psc->psc_status & PSC_SR_TXEMP))
+		;
+
+	psc->psc_buffer_8 = c;
+}
+
+void serial_puts_dev (unsigned long dev_base, const char *s)
+{
+	while (*s) {
+		serial_putc_dev (dev_base, *s++);
+	}
+}
+
+int serial_getc_dev (unsigned long dev_base)
+{
+	volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)dev_base;
+
+	/* Wait for a character to arrive. */
+	while (!(psc->psc_status & PSC_SR_RXRDY))
+		;
+
+	return psc->psc_buffer_8;
+}
+
+int serial_tstc_dev (unsigned long dev_base)
+{
+	volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)dev_base;
+
+	return (psc->psc_status & PSC_SR_RXRDY);
+}
+
+void serial_setbrg_dev (unsigned long dev_base)
+{
+	volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)dev_base;
+	unsigned long baseclk, div;
+
+	baseclk = (gd->arch.ipb_clk + 16) / 32;
+
+	/* set up UART divisor */
+	div = (baseclk + (gd->baudrate/2)) / gd->baudrate;
+	psc->ctur = (div >> 8) & 0xFF;
+	psc->ctlr =  div & 0xff;
+}
+
+void serial_setrts_dev (unsigned long dev_base, int s)
+{
+	volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)dev_base;
+
+	if (s) {
+		/* Assert RTS (become LOW) */
+		psc->op1 = 0x1;
+	}
+	else {
+		/* Negate RTS (become HIGH) */
+		psc->op0 = 0x1;
+	}
+}
+
+int serial_getcts_dev (unsigned long dev_base)
+{
+	volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)dev_base;
+
+	return (psc->ip & 0x1) ? 0 : 1;
+}
+
+int serial0_init(void)
+{
+	return (serial_init_dev(PSC_BASE));
+}
+
+void serial0_setbrg (void)
+{
+	serial_setbrg_dev(PSC_BASE);
+}
+
+void serial0_putc(const char c)
+{
+	serial_putc_dev(PSC_BASE,c);
+}
+
+void serial0_puts(const char *s)
+{
+	serial_puts_dev(PSC_BASE, s);
+}
+
+int serial0_getc(void)
+{
+	return(serial_getc_dev(PSC_BASE));
+}
+
+int serial0_tstc(void)
+{
+	return (serial_tstc_dev(PSC_BASE));
+}
+
+struct serial_device serial0_device =
+{
+	.name	= "serial0",
+	.start	= serial0_init,
+	.stop	= NULL,
+	.setbrg	= serial0_setbrg,
+	.getc	= serial0_getc,
+	.tstc	= serial0_tstc,
+	.putc	= serial0_putc,
+	.puts	= serial0_puts,
+};
+
+__weak struct serial_device *default_serial_console(void)
+{
+	return &serial0_device;
+}
+
+#ifdef CONFIG_PSC_CONSOLE2
+int serial1_init(void)
+{
+	return serial_init_dev(PSC_BASE2);
+}
+
+void serial1_setbrg(void)
+{
+	serial_setbrg_dev(PSC_BASE2);
+}
+
+void serial1_putc(const char c)
+{
+	serial_putc_dev(PSC_BASE2, c);
+}
+
+void serial1_puts(const char *s)
+{
+	serial_puts_dev(PSC_BASE2, s);
+}
+
+int serial1_getc(void)
+{
+	return serial_getc_dev(PSC_BASE2);
+}
+
+int serial1_tstc(void)
+{
+	return serial_tstc_dev(PSC_BASE2);
+}
+
+struct serial_device serial1_device =
+{
+	.name	= "serial1",
+	.start	= serial1_init,
+	.stop	= NULL,
+	.setbrg	= serial1_setbrg,
+	.getc	= serial1_getc,
+	.tstc	= serial1_tstc,
+	.putc	= serial1_putc,
+	.puts	= serial1_puts,
+};
+#endif /* CONFIG_PSC_CONSOLE2 */
+
+#endif /* CONFIG_PSC_CONSOLE */
diff --git a/arch/powerpc/cpu/mpc5xxx/speed.c b/arch/powerpc/cpu/mpc5xxx/speed.c
new file mode 100644
index 0000000000..b37c4a5208
--- /dev/null
+++ b/arch/powerpc/cpu/mpc5xxx/speed.c
@@ -0,0 +1,84 @@ 
+/*
+ * (C) Copyright 2000-2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <asm/processor.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+
+/* Bus-to-Core Multipliers */
+
+static int bus2core[] = {
+	3, 2, 2, 2, 4, 4, 5, 9,
+	6, 11, 8, 10, 3, 12, 7, 0,
+	6, 5, 13, 2, 14, 4, 15, 9,
+	0, 11, 8, 10, 16, 12, 7, 0
+};
+/* ------------------------------------------------------------------------- */
+
+/*
+ *
+ */
+
+int get_clocks (void)
+{
+	ulong val, vco;
+
+#if !defined(CONFIG_SYS_MPC5XXX_CLKIN)
+#error clock measuring not implemented yet - define CONFIG_SYS_MPC5XXX_CLKIN
+#endif
+
+	val = *(vu_long *)MPC5XXX_CDM_PORCFG;
+	if (val & (1 << 6)) {
+		vco = CONFIG_SYS_MPC5XXX_CLKIN * 12;
+	} else {
+		vco = CONFIG_SYS_MPC5XXX_CLKIN * 16;
+	}
+	if (val & (1 << 5)) {
+		gd->bus_clk = vco / 8;
+	} else {
+		gd->bus_clk = vco / 4;
+	}
+	gd->cpu_clk = gd->bus_clk * bus2core[val & 0x1f] / 2;
+
+	val = *(vu_long *)MPC5XXX_CDM_CFG;
+	if (val & (1 << 8)) {
+		gd->arch.ipb_clk = gd->bus_clk / 2;
+	} else {
+		gd->arch.ipb_clk = gd->bus_clk;
+	}
+	switch (val & 3) {
+	case 0:
+		gd->pci_clk = gd->arch.ipb_clk;
+		break;
+	case 1:
+		gd->pci_clk = gd->arch.ipb_clk / 2;
+		break;
+	default:
+		gd->pci_clk = gd->bus_clk / 4;
+		break;
+	}
+
+	return (0);
+}
+
+int print_cpuinfo(void)
+{
+	char buf1[32], buf2[32], buf3[32];
+
+	printf ("       Bus %s MHz, IPB %s MHz, PCI %s MHz\n",
+		strmhz(buf1, gd->bus_clk),
+		strmhz(buf2, gd->arch.ipb_clk),
+		strmhz(buf3, gd->pci_clk)
+	);
+	return (0);
+}
+
+/* ------------------------------------------------------------------------- */
diff --git a/arch/powerpc/cpu/mpc5xxx/spl_boot.c b/arch/powerpc/cpu/mpc5xxx/spl_boot.c
new file mode 100644
index 0000000000..2d7f6c4a93
--- /dev/null
+++ b/arch/powerpc/cpu/mpc5xxx/spl_boot.c
@@ -0,0 +1,76 @@ 
+/*
+ * Copyright (C) 2012 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Needed to align size SPL image to a 4-byte length
+ */
+u32 end_align __attribute__ ((section(".end_align")));
+
+/*
+ * Return selected boot device. On MPC5200 its only NOR flash right now.
+ */
+u32 spl_boot_device(void)
+{
+	return BOOT_DEVICE_NOR;
+}
+
+/*
+ * SPL version of board_init_f()
+ */
+void board_init_f(ulong bootflag)
+{
+	end_align = (u32)__spl_flash_end;
+
+	/*
+	 * On MPC5200, the initial RAM (and gd) is located in the internal
+	 * SRAM. So we can actually call the preloader console init code
+	 * before calling dram_init(). This makes serial output (printf)
+	 * available very early, even before SDRAM init, which has been
+	 * an U-Boot priciple from day 1.
+	 */
+
+	/*
+	 * Init global_data pointer. Has to be done before calling
+	 * get_clocks(), as it stores some clock values into gd needed
+	 * later on in the serial driver.
+	 */
+	/* Pointer is writable since we allocated a register for it */
+	gd = (gd_t *)(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
+	/* Clear initial global data */
+	memset((void *)gd, 0, sizeof(gd_t));
+
+	/*
+	 * get_clocks() needs to be called so that the serial driver
+	 * works correctly
+	 */
+	get_clocks();
+
+	/*
+	 * Do rudimental console / serial setup
+	 */
+	preloader_console_init();
+
+	/*
+	 * First we need to initialize the SDRAM, so that the real
+	 * U-Boot or the OS (Linux) can be loaded
+	 */
+	dram_init();
+
+	/* Clear bss */
+	memset(__bss_start, '\0', __bss_end - __bss_start);
+
+	/*
+	 * Call board_init_r() (SPL framework version) to load and boot
+	 * real U-Boot or OS
+	 */
+	board_init_r(NULL, 0);
+	/* Does not return!!! */
+}
diff --git a/arch/powerpc/cpu/mpc5xxx/start.S b/arch/powerpc/cpu/mpc5xxx/start.S
new file mode 100644
index 0000000000..b4c5543eb5
--- /dev/null
+++ b/arch/powerpc/cpu/mpc5xxx/start.S
@@ -0,0 +1,780 @@ 
+/*
+ *  Copyright (C) 1998	Dan Malek <dmalek@jlc.net>
+ *  Copyright (C) 1999	Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
+ *  Copyright (C) 2000 - 2003 Wolfgang Denk <wd@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ *  U-Boot - Startup Code for MPC5xxx CPUs
+ */
+#include <asm-offsets.h>
+#include <config.h>
+#include <mpc5xxx.h>
+#include <version.h>
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+
+#include <asm/cache.h>
+#include <asm/mmu.h>
+#include <asm/u-boot.h>
+
+/* We don't want the  MMU yet.
+*/
+#undef	MSR_KERNEL
+/* Floating Point enable, Machine Check and Recoverable Interr. */
+#ifdef DEBUG
+#define MSR_KERNEL (MSR_FP|MSR_RI)
+#else
+#define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI)
+#endif
+
+#ifndef CONFIG_SPL_BUILD
+/*
+ * Set up GOT: Global Offset Table
+ *
+ * Use r12 to access the GOT
+ */
+	START_GOT
+	GOT_ENTRY(_GOT2_TABLE_)
+	GOT_ENTRY(_FIXUP_TABLE_)
+
+	GOT_ENTRY(_start)
+	GOT_ENTRY(_start_of_vectors)
+	GOT_ENTRY(_end_of_vectors)
+	GOT_ENTRY(transfer_to_handler)
+
+	GOT_ENTRY(__init_end)
+	GOT_ENTRY(__bss_end)
+	GOT_ENTRY(__bss_start)
+	END_GOT
+#endif
+
+/*
+ * Version string
+ */
+	.data
+	.globl	version_string
+version_string:
+	.ascii U_BOOT_VERSION_STRING, "\0"
+
+/*
+ * Exception vectors
+ */
+	.text
+	. = EXC_OFF_SYS_RESET
+	.globl	_start
+_start:
+
+#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
+	/*
+	 * This is the entry of the real U-Boot from a board port
+	 * that supports SPL booting on the MPC5200. We only need
+	 * to call board_init_f() here. Everything else has already
+	 * been done in the SPL u-boot version.
+	 */
+	GET_GOT			/* initialize GOT access		*/
+
+	/*
+	 * The GD (global data) struct needs to get cleared. Lets do
+	 * this by calling memset().
+	 * This function is called when the platform is build with SPL
+	 * support from the main (full-blown) U-Boot. And the GD needs
+	 * to get cleared (again) so that the following generic
+	 * board support code initializes all variables correctly.
+	 */
+	mr	r3, r2		/* parameter 1:	 GD pointer		*/
+	li	r4,0		/* parameter 2:	 value to fill		*/
+	li	r5,GD_SIZE	/* parameter 3:	 count			*/
+	bl	memset
+
+	li	r3, 0		/* parameter 1:	 bootflag		*/
+	bl	board_init_f	/* run 1st part of board init code (in Flash)*/
+	/* NOTREACHED - board_init_f() does not return */
+#else
+	mfmsr	r5			/* save msr contents		*/
+
+	/* Move CSBoot and adjust instruction pointer                   */
+	/*--------------------------------------------------------------*/
+
+#if defined(CONFIG_SYS_LOWBOOT)
+# if defined(CONFIG_SYS_RAMBOOT)
+#  error CONFIG_SYS_LOWBOOT is incompatible with CONFIG_SYS_RAMBOOT
+# endif /* CONFIG_SYS_RAMBOOT */
+	lis	r4, CONFIG_SYS_DEFAULT_MBAR@h
+	lis	r3,	START_REG(CONFIG_SYS_BOOTCS_START)@h
+	ori	r3, r3, START_REG(CONFIG_SYS_BOOTCS_START)@l
+	stw	r3, 0x4(r4)		/* CS0 start */
+	lis	r3,	STOP_REG(CONFIG_SYS_BOOTCS_START, CONFIG_SYS_BOOTCS_SIZE)@h
+	ori	r3, r3, STOP_REG(CONFIG_SYS_BOOTCS_START, CONFIG_SYS_BOOTCS_SIZE)@l
+	stw	r3, 0x8(r4)		/* CS0 stop */
+	lis	r3,     0x02010000@h
+	ori	r3, r3, 0x02010000@l
+	stw	r3, 0x54(r4)		/* CS0 and Boot enable */
+
+	lis     r3,	lowboot_reentry@h	/* jump from bootlow address space (0x0000xxxx) */
+	ori     r3, r3, lowboot_reentry@l	/* to the address space the linker used */
+	mtlr	r3
+	blr
+
+lowboot_reentry:
+	lis	r3,	START_REG(CONFIG_SYS_BOOTCS_START)@h
+	ori	r3, r3, START_REG(CONFIG_SYS_BOOTCS_START)@l
+	stw	r3, 0x4c(r4)		/* Boot start */
+	lis	r3,	STOP_REG(CONFIG_SYS_BOOTCS_START, CONFIG_SYS_BOOTCS_SIZE)@h
+	ori	r3, r3, STOP_REG(CONFIG_SYS_BOOTCS_START, CONFIG_SYS_BOOTCS_SIZE)@l
+	stw	r3, 0x50(r4)		/* Boot stop */
+	lis	r3,     0x02000001@h
+	ori	r3, r3, 0x02000001@l
+	stw	r3, 0x54(r4)		/* Boot enable, CS0 disable */
+#endif	/* CONFIG_SYS_LOWBOOT */
+
+#if defined(CONFIG_SYS_DEFAULT_MBAR) && !defined(CONFIG_SYS_RAMBOOT)
+	lis	r3, CONFIG_SYS_MBAR@h
+	ori	r3, r3, CONFIG_SYS_MBAR@l
+	/* MBAR is mirrored into the MBAR SPR */
+	mtspr	MBAR,r3
+	rlwinm	r3, r3, 16, 16, 31
+	lis	r4, CONFIG_SYS_DEFAULT_MBAR@h
+	stw	r3, 0(r4)
+#endif /* CONFIG_SYS_DEFAULT_MBAR */
+
+	/* Initialise the MPC5xxx processor core			*/
+	/*--------------------------------------------------------------*/
+
+	bl	init_5xxx_core
+
+	/* initialize some things that are hard to access from C	*/
+	/*--------------------------------------------------------------*/
+
+	/* set up stack in on-chip SRAM */
+	lis	r3, CONFIG_SYS_INIT_RAM_ADDR@h
+	ori	r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l
+	ori	r1, r3, CONFIG_SYS_INIT_SP_OFFSET
+	li	r0, 0			/* Make room for stack frame header and	*/
+	stwu	r0, -4(r1)		/* clear final stack frame so that	*/
+	stwu	r0, -4(r1)		/* stack backtraces terminate cleanly	*/
+
+	/* let the C-code set up the rest				*/
+	/*								*/
+	/* Be careful to keep code relocatable !			*/
+	/*--------------------------------------------------------------*/
+
+#ifndef CONFIG_SPL_BUILD
+	GET_GOT			/* initialize GOT access		*/
+#endif
+
+	/* r3: IMMR */
+	bl	cpu_init_f	/* run low-level CPU init code (in Flash)*/
+
+	li	r3, 0		/* parameter 1:	 bootflag		*/
+	bl	board_init_f	/* run 1st part of board init code (in Flash)*/
+
+	/* NOTREACHED - board_init_f() does not return */
+#endif
+
+#ifndef CONFIG_SPL_BUILD
+/*
+ * Vector Table
+ */
+
+	.globl	_start_of_vectors
+_start_of_vectors:
+
+/* Machine check */
+	STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
+
+/* Data Storage exception. */
+	STD_EXCEPTION(0x300, DataStorage, UnknownException)
+
+/* Instruction Storage exception. */
+	STD_EXCEPTION(0x400, InstStorage, UnknownException)
+
+/* External Interrupt exception. */
+	STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
+
+/* Alignment exception. */
+	. = 0x600
+Alignment:
+	EXCEPTION_PROLOG(SRR0, SRR1)
+	mfspr	r4,DAR
+	stw	r4,_DAR(r21)
+	mfspr	r5,DSISR
+	stw	r5,_DSISR(r21)
+	addi	r3,r1,STACK_FRAME_OVERHEAD
+	EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
+
+/* Program check exception */
+	. = 0x700
+ProgramCheck:
+	EXCEPTION_PROLOG(SRR0, SRR1)
+	addi	r3,r1,STACK_FRAME_OVERHEAD
+	EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
+		MSR_KERNEL, COPY_EE)
+
+	STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
+
+	/* I guess we could implement decrementer, and may have
+	 * to someday for timekeeping.
+	 */
+	STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
+
+	STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
+	STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
+	STD_EXCEPTION(0xc00, SystemCall, UnknownException)
+	STD_EXCEPTION(0xd00, SingleStep, UnknownException)
+
+	STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
+	STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
+
+	STD_EXCEPTION(0x1000, InstructionTLBMiss, UnknownException)
+	STD_EXCEPTION(0x1100, DataLoadTLBMiss, UnknownException)
+	STD_EXCEPTION(0x1200, DataStoreTLBMiss, UnknownException)
+#ifdef DEBUG
+	. = 0x1300
+	/*
+	 * This exception occurs when the program counter matches the
+	 * Instruction Address Breakpoint Register (IABR).
+	 *
+	 * I want the cpu to halt if this occurs so I can hunt around
+	 * with the debugger and look at things.
+	 *
+	 * When DEBUG is defined, both machine check enable (in the MSR)
+	 * and checkstop reset enable (in the reset mode register) are
+	 * turned off and so a checkstop condition will result in the cpu
+	 * halting.
+	 *
+	 * I force the cpu into a checkstop condition by putting an illegal
+	 * instruction here (at least this is the theory).
+	 *
+	 * well - that didnt work, so just do an infinite loop!
+	 */
+1:	b	1b
+#else
+	STD_EXCEPTION(0x1300, InstructionBreakpoint, DebugException)
+#endif
+	STD_EXCEPTION(0x1400, SMI, UnknownException)
+
+	STD_EXCEPTION(0x1500, Trap_15, UnknownException)
+	STD_EXCEPTION(0x1600, Trap_16, UnknownException)
+	STD_EXCEPTION(0x1700, Trap_17, UnknownException)
+	STD_EXCEPTION(0x1800, Trap_18, UnknownException)
+	STD_EXCEPTION(0x1900, Trap_19, UnknownException)
+	STD_EXCEPTION(0x1a00, Trap_1a, UnknownException)
+	STD_EXCEPTION(0x1b00, Trap_1b, UnknownException)
+	STD_EXCEPTION(0x1c00, Trap_1c, UnknownException)
+	STD_EXCEPTION(0x1d00, Trap_1d, UnknownException)
+	STD_EXCEPTION(0x1e00, Trap_1e, UnknownException)
+	STD_EXCEPTION(0x1f00, Trap_1f, UnknownException)
+	STD_EXCEPTION(0x2000, Trap_20, UnknownException)
+	STD_EXCEPTION(0x2100, Trap_21, UnknownException)
+	STD_EXCEPTION(0x2200, Trap_22, UnknownException)
+	STD_EXCEPTION(0x2300, Trap_23, UnknownException)
+	STD_EXCEPTION(0x2400, Trap_24, UnknownException)
+	STD_EXCEPTION(0x2500, Trap_25, UnknownException)
+	STD_EXCEPTION(0x2600, Trap_26, UnknownException)
+	STD_EXCEPTION(0x2700, Trap_27, UnknownException)
+	STD_EXCEPTION(0x2800, Trap_28, UnknownException)
+	STD_EXCEPTION(0x2900, Trap_29, UnknownException)
+	STD_EXCEPTION(0x2a00, Trap_2a, UnknownException)
+	STD_EXCEPTION(0x2b00, Trap_2b, UnknownException)
+	STD_EXCEPTION(0x2c00, Trap_2c, UnknownException)
+	STD_EXCEPTION(0x2d00, Trap_2d, UnknownException)
+	STD_EXCEPTION(0x2e00, Trap_2e, UnknownException)
+	STD_EXCEPTION(0x2f00, Trap_2f, UnknownException)
+
+
+	.globl	_end_of_vectors
+_end_of_vectors:
+
+	. = 0x3000
+
+/*
+ * This code finishes saving the registers to the exception frame
+ * and jumps to the appropriate handler for the exception.
+ * Register r21 is pointer into trap frame, r1 has new stack pointer.
+ */
+	.globl	transfer_to_handler
+transfer_to_handler:
+	stw	r22,_NIP(r21)
+	lis	r22,MSR_POW@h
+	andc	r23,r23,r22
+	stw	r23,_MSR(r21)
+	SAVE_GPR(7, r21)
+	SAVE_4GPRS(8, r21)
+	SAVE_8GPRS(12, r21)
+	SAVE_8GPRS(24, r21)
+	mflr	r23
+	andi.	r24,r23,0x3f00		/* get vector offset */
+	stw	r24,TRAP(r21)
+	li	r22,0
+	stw	r22,RESULT(r21)
+	lwz	r24,0(r23)		/* virtual address of handler */
+	lwz	r23,4(r23)		/* where to go when done */
+	mtspr	SRR0,r24
+	mtspr	SRR1,r20
+	mtlr	r23
+	SYNC
+	rfi				/* jump to handler, enable MMU */
+
+int_return:
+	mfmsr	r28		/* Disable interrupts */
+	li	r4,0
+	ori	r4,r4,MSR_EE
+	andc	r28,r28,r4
+	SYNC			/* Some chip revs need this... */
+	mtmsr	r28
+	SYNC
+	lwz	r2,_CTR(r1)
+	lwz	r0,_LINK(r1)
+	mtctr	r2
+	mtlr	r0
+	lwz	r2,_XER(r1)
+	lwz	r0,_CCR(r1)
+	mtspr	XER,r2
+	mtcrf	0xFF,r0
+	REST_10GPRS(3, r1)
+	REST_10GPRS(13, r1)
+	REST_8GPRS(23, r1)
+	REST_GPR(31, r1)
+	lwz	r2,_NIP(r1)	/* Restore environment */
+	lwz	r0,_MSR(r1)
+	mtspr	SRR0,r2
+	mtspr	SRR1,r0
+	lwz	r0,GPR0(r1)
+	lwz	r2,GPR2(r1)
+	lwz	r1,GPR1(r1)
+	SYNC
+	rfi
+#endif /* CONFIG_SPL_BUILD */
+
+/*
+ * This code initialises the MPC5xxx processor core
+ * (conforms to PowerPC 603e spec)
+ * Note: expects original MSR contents to be in r5.
+ */
+
+	.globl	init_5xx_core
+init_5xxx_core:
+
+	/* Initialize machine status; enable machine check interrupt	*/
+	/*--------------------------------------------------------------*/
+
+	li	r3, MSR_KERNEL		/* Set ME and RI flags */
+	rlwimi	r3, r5, 0, 25, 25	/* preserve IP bit set by HRCW */
+#ifdef DEBUG
+	rlwimi	r3, r5, 0, 21, 22	/* debugger might set SE & BE bits */
+#endif
+	SYNC				/* Some chip revs need this... */
+	mtmsr	r3
+	SYNC
+	mtspr	SRR1, r3		/* Make SRR1 match MSR */
+
+	/* Initialize the Hardware Implementation-dependent Registers	*/
+	/* HID0 also contains cache control				*/
+	/*--------------------------------------------------------------*/
+
+	lis	r3, CONFIG_SYS_HID0_INIT@h
+	ori	r3, r3, CONFIG_SYS_HID0_INIT@l
+	SYNC
+	mtspr	HID0, r3
+
+	lis	r3, CONFIG_SYS_HID0_FINAL@h
+	ori	r3, r3, CONFIG_SYS_HID0_FINAL@l
+	SYNC
+	mtspr	HID0, r3
+
+	/* clear all BAT's						*/
+	/*--------------------------------------------------------------*/
+
+	li	r0, 0
+	mtspr	DBAT0U, r0
+	mtspr	DBAT0L, r0
+	mtspr	DBAT1U, r0
+	mtspr	DBAT1L, r0
+	mtspr	DBAT2U, r0
+	mtspr	DBAT2L, r0
+	mtspr	DBAT3U, r0
+	mtspr	DBAT3L, r0
+	mtspr	DBAT4U, r0
+	mtspr	DBAT4L, r0
+	mtspr	DBAT5U, r0
+	mtspr	DBAT5L, r0
+	mtspr	DBAT6U, r0
+	mtspr	DBAT6L, r0
+	mtspr	DBAT7U, r0
+	mtspr	DBAT7L, r0
+	mtspr	IBAT0U, r0
+	mtspr	IBAT0L, r0
+	mtspr	IBAT1U, r0
+	mtspr	IBAT1L, r0
+	mtspr	IBAT2U, r0
+	mtspr	IBAT2L, r0
+	mtspr	IBAT3U, r0
+	mtspr	IBAT3L, r0
+	mtspr	IBAT4U, r0
+	mtspr	IBAT4L, r0
+	mtspr	IBAT5U, r0
+	mtspr	IBAT5L, r0
+	mtspr	IBAT6U, r0
+	mtspr	IBAT6L, r0
+	mtspr	IBAT7U, r0
+	mtspr	IBAT7L, r0
+	SYNC
+
+	/* invalidate all tlb's						*/
+	/*								*/
+	/* From the 603e User Manual: "The 603e provides the ability to	*/
+	/* invalidate a TLB entry. The TLB Invalidate Entry (tlbie)	*/
+	/* instruction invalidates the TLB entry indexed by the EA, and	*/
+	/* operates on both the instruction and data TLBs simultaneously*/
+	/* invalidating four TLB entries (both sets in each TLB). The	*/
+	/* index corresponds to bits 15-19 of the EA. To invalidate all	*/
+	/* entries within both TLBs, 32 tlbie instructions should be	*/
+	/* issued, incrementing this field by one each time."		*/
+	/*								*/
+	/* "Note that the tlbia instruction is not implemented on the	*/
+	/* 603e."							*/
+	/*								*/
+	/* bits 15-19 correspond to addresses 0x00000000 to 0x0001F000	*/
+	/* incrementing by 0x1000 each time. The code below is sort of	*/
+	/* based on code in "flush_tlbs" from arch/powerpc/kernel/head.S	*/
+	/*								*/
+	/*--------------------------------------------------------------*/
+
+	li	r3, 32
+	mtctr	r3
+	li	r3, 0
+1:	tlbie	r3
+	addi	r3, r3, 0x1000
+	bdnz	1b
+	SYNC
+
+	/* Done!							*/
+	/*--------------------------------------------------------------*/
+
+	blr
+
+/* Cache functions.
+ *
+ * Note: requires that all cache bits in
+ * HID0 are in the low half word.
+ */
+	.globl	icache_enable
+icache_enable:
+	mfspr	r3, HID0
+	ori	r3, r3, HID0_ICE
+	lis	r4, 0
+	ori	r4, r4, HID0_ILOCK
+	andc	r3, r3, r4
+	ori	r4, r3, HID0_ICFI
+	isync
+	mtspr	HID0, r4	/* sets enable and invalidate, clears lock */
+	isync
+	mtspr	HID0, r3	/* clears invalidate */
+	blr
+
+	.globl	icache_disable
+icache_disable:
+	mfspr	r3, HID0
+	lis	r4, 0
+	ori	r4, r4, HID0_ICE|HID0_ILOCK
+	andc	r3, r3, r4
+	ori	r4, r3, HID0_ICFI
+	isync
+	mtspr	HID0, r4	/* sets invalidate, clears enable and lock */
+	isync
+	mtspr	HID0, r3	/* clears invalidate */
+	blr
+
+	.globl	icache_status
+icache_status:
+	mfspr	r3, HID0
+	rlwinm	r3, r3, HID0_ICE_BITPOS + 1, 31, 31
+	blr
+
+	.globl	dcache_enable
+dcache_enable:
+	mfspr	r3, HID0
+	ori	r3, r3, HID0_DCE
+	lis	r4, 0
+	ori	r4, r4, HID0_DLOCK
+	andc	r3, r3, r4
+	ori	r4, r3, HID0_DCI
+	sync
+	mtspr	HID0, r4	/* sets enable and invalidate, clears lock */
+	sync
+	mtspr	HID0, r3	/* clears invalidate */
+	blr
+
+	.globl	dcache_disable
+dcache_disable:
+	mfspr	r3, HID0
+	lis	r4, 0
+	ori	r4, r4, HID0_DCE|HID0_DLOCK
+	andc	r3, r3, r4
+	ori	r4, r3, HID0_DCI
+	sync
+	mtspr	HID0, r4	/* sets invalidate, clears enable and lock */
+	sync
+	mtspr	HID0, r3	/* clears invalidate */
+	blr
+
+	.globl	dcache_status
+dcache_status:
+	mfspr	r3, HID0
+	rlwinm	r3, r3, HID0_DCE_BITPOS + 1, 31, 31
+	blr
+
+	.globl get_svr
+get_svr:
+	mfspr	r3, SVR
+	blr
+
+	.globl get_pvr
+get_pvr:
+	mfspr	r3, PVR
+	blr
+
+#ifndef CONFIG_SPL_BUILD
+/*------------------------------------------------------------------------------*/
+
+/*
+ * void relocate_code (addr_sp, gd, addr_moni)
+ *
+ * This "function" does not return, instead it continues in RAM
+ * after relocating the monitor code.
+ *
+ * r3 = dest
+ * r4 = src
+ * r5 = length in bytes
+ * r6 = cachelinesize
+ */
+	.globl	relocate_code
+relocate_code:
+	mr	r1,  r3		/* Set new stack pointer		*/
+	mr	r9,  r4		/* Save copy of Global Data pointer	*/
+	mr	r10, r5		/* Save copy of Destination Address	*/
+
+	GET_GOT
+	mr	r3,  r5				/* Destination Address	*/
+	lis	r4, CONFIG_SYS_MONITOR_BASE@h		/* Source      Address	*/
+	ori	r4, r4, CONFIG_SYS_MONITOR_BASE@l
+	lwz	r5, GOT(__init_end)
+	sub	r5, r5, r4
+	li	r6, CONFIG_SYS_CACHELINE_SIZE		/* Cache Line Size	*/
+
+	/*
+	 * Fix GOT pointer:
+	 *
+	 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
+	 *
+	 * Offset:
+	 */
+	sub	r15, r10, r4
+
+	/* First our own GOT */
+	add	r12, r12, r15
+	/* then the one used by the C code */
+	add	r30, r30, r15
+
+	/*
+	 * Now relocate code
+	 */
+
+	cmplw	cr1,r3,r4
+	addi	r0,r5,3
+	srwi.	r0,r0,2
+	beq	cr1,4f		/* In place copy is not necessary	*/
+	beq	7f		/* Protect against 0 count		*/
+	mtctr	r0
+	bge	cr1,2f
+
+	la	r8,-4(r4)
+	la	r7,-4(r3)
+1:	lwzu	r0,4(r8)
+	stwu	r0,4(r7)
+	bdnz	1b
+	b	4f
+
+2:	slwi	r0,r0,2
+	add	r8,r4,r0
+	add	r7,r3,r0
+3:	lwzu	r0,-4(r8)
+	stwu	r0,-4(r7)
+	bdnz	3b
+
+/*
+ * Now flush the cache: note that we must start from a cache aligned
+ * address. Otherwise we might miss one cache line.
+ */
+4:	cmpwi	r6,0
+	add	r5,r3,r5
+	beq	7f		/* Always flush prefetch queue in any case */
+	subi	r0,r6,1
+	andc	r3,r3,r0
+	mfspr	r7,HID0		/* don't do dcbst if dcache is disabled */
+	rlwinm	r7,r7,HID0_DCE_BITPOS+1,31,31
+	cmpwi	r7,0
+	beq	9f
+	mr	r4,r3
+5:	dcbst	0,r4
+	add	r4,r4,r6
+	cmplw	r4,r5
+	blt	5b
+	sync			/* Wait for all dcbst to complete on bus */
+9:	mfspr	r7,HID0		/* don't do icbi if icache is disabled */
+	rlwinm	r7,r7,HID0_ICE_BITPOS+1,31,31
+	cmpwi	r7,0
+	beq	7f
+	mr	r4,r3
+6:	icbi	0,r4
+	add	r4,r4,r6
+	cmplw	r4,r5
+	blt	6b
+7:	sync			/* Wait for all icbi to complete on bus	*/
+	isync
+
+/*
+ * We are done. Do not return, instead branch to second part of board
+ * initialization, now running from RAM.
+ */
+
+	addi	r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
+	mtlr	r0
+	blr
+
+in_ram:
+
+	/*
+	 * Relocation Function, r12 point to got2+0x8000
+	 *
+	 * Adjust got2 pointers, no need to check for 0, this code
+	 * already puts a few entries in the table.
+	 */
+	li	r0,__got2_entries@sectoff@l
+	la	r3,GOT(_GOT2_TABLE_)
+	lwz	r11,GOT(_GOT2_TABLE_)
+	mtctr	r0
+	sub	r11,r3,r11
+	addi	r3,r3,-4
+1:	lwzu	r0,4(r3)
+	cmpwi	r0,0
+	beq-	2f
+	add	r0,r0,r11
+	stw	r0,0(r3)
+2:	bdnz	1b
+
+	/*
+	 * Now adjust the fixups and the pointers to the fixups
+	 * in case we need to move ourselves again.
+	 */
+	li	r0,__fixup_entries@sectoff@l
+	lwz	r3,GOT(_FIXUP_TABLE_)
+	cmpwi	r0,0
+	mtctr	r0
+	addi	r3,r3,-4
+	beq	4f
+3:	lwzu	r4,4(r3)
+	lwzux	r0,r4,r11
+	cmpwi	r0,0
+	add	r0,r0,r11
+	stw	r4,0(r3)
+	beq-	5f
+	stw	r0,0(r4)
+5:	bdnz	3b
+4:
+clear_bss:
+	/*
+	 * Now clear BSS segment
+	 */
+	lwz	r3,GOT(__bss_start)
+	lwz	r4,GOT(__bss_end)
+
+	cmplw	0, r3, r4
+	beq	6f
+
+	li	r0, 0
+5:
+	stw	r0, 0(r3)
+	addi	r3, r3, 4
+	cmplw	0, r3, r4
+	bne	5b
+6:
+
+	mr	r3, r9		/* Global Data pointer		*/
+	mr	r4, r10		/* Destination Address		*/
+	bl	board_init_r
+
+	/*
+	 * Copy exception vector code to low memory
+	 *
+	 * r3: dest_addr
+	 * r7: source address, r8: end address, r9: target address
+	 */
+	.globl	trap_init
+trap_init:
+	mflr	r4			/* save link register		*/
+	GET_GOT
+	lwz	r7, GOT(_start)
+	lwz	r8, GOT(_end_of_vectors)
+
+	li	r9, 0x100		/* reset vector always at 0x100 */
+
+	cmplw	0, r7, r8
+	bgelr				/* return if r7>=r8 - just in case */
+1:
+	lwz	r0, 0(r7)
+	stw	r0, 0(r9)
+	addi	r7, r7, 4
+	addi	r9, r9, 4
+	cmplw	0, r7, r8
+	bne	1b
+
+	/*
+	 * relocate `hdlr' and `int_return' entries
+	 */
+	li	r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
+	li	r8, Alignment - _start + EXC_OFF_SYS_RESET
+2:
+	bl	trap_reloc
+	addi	r7, r7, 0x100		/* next exception vector	*/
+	cmplw	0, r7, r8
+	blt	2b
+
+	li	r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
+	bl	trap_reloc
+
+	li	r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
+	bl	trap_reloc
+
+	li	r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
+	li	r8, SystemCall - _start + EXC_OFF_SYS_RESET
+3:
+	bl	trap_reloc
+	addi	r7, r7, 0x100		/* next exception vector	*/
+	cmplw	0, r7, r8
+	blt	3b
+
+	li	r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
+	li	r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
+4:
+	bl	trap_reloc
+	addi	r7, r7, 0x100		/* next exception vector	*/
+	cmplw	0, r7, r8
+	blt	4b
+
+	mfmsr	r3			/* now that the vectors have	*/
+	lis	r7, MSR_IP@h		/* relocated into low memory	*/
+	ori	r7, r7, MSR_IP@l	/* MSR[IP] can be turned off	*/
+	andc	r3, r3, r7		/* (if it was on)		*/
+	SYNC				/* Some chip revs need this... */
+	mtmsr	r3
+	SYNC
+
+	mtlr	r4			/* restore link register    */
+	blr
+
+#endif /* CONFIG_SPL_BUILD */
diff --git a/arch/powerpc/cpu/mpc5xxx/traps.c b/arch/powerpc/cpu/mpc5xxx/traps.c
new file mode 100644
index 0000000000..5498b7e699
--- /dev/null
+++ b/arch/powerpc/cpu/mpc5xxx/traps.c
@@ -0,0 +1,220 @@ 
+/*
+ * linux/arch/powerpc/kernel/traps.c
+ *
+ * Copyright (C) 1995-1996  Gary Thomas (gdt@linuxppc.org)
+ *
+ * Modified by Cort Dougan (cort@cs.nmt.edu)
+ * and Paul Mackerras (paulus@cs.anu.edu.au)
+ * fixed Machine Check Reasons by Reinhard Meyer (r.meyer@emk-elektronik.de)
+ *
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * This file handles the architecture-dependent parts of hardware exceptions
+ */
+
+#include <common.h>
+#include <command.h>
+#include <kgdb.h>
+#include <asm/processor.h>
+
+/* Returns 0 if exception not found and fixup otherwise.  */
+extern unsigned long search_exception_table(unsigned long);
+
+/* THIS NEEDS CHANGING to use the board info structure.
+*/
+#define END_OF_MEM	0x02000000
+
+/*
+ * Trap & Exception support
+ */
+
+static void print_backtrace(unsigned long *sp)
+{
+	int cnt = 0;
+	unsigned long i;
+
+	printf("Call backtrace: ");
+	while (sp) {
+		if ((uint)sp > END_OF_MEM)
+			break;
+
+		i = sp[1];
+		if (cnt++ % 7 == 0)
+			printf("\n");
+		printf("%08lX ", i);
+		if (cnt > 32) break;
+		sp = (unsigned long *)*sp;
+	}
+	printf("\n");
+}
+
+void show_regs(struct pt_regs *regs)
+{
+	int i;
+
+	printf("NIP: %08lX XER: %08lX LR: %08lX REGS: %p TRAP: %04lx DAR: %08lX\n",
+	       regs->nip, regs->xer, regs->link, regs, regs->trap, regs->dar);
+	printf("MSR: %08lx EE: %01x PR: %01x FP: %01x ME: %01x IR/DR: %01x%01x\n",
+	       regs->msr, regs->msr&MSR_EE ? 1 : 0, regs->msr&MSR_PR ? 1 : 0,
+	       regs->msr & MSR_FP ? 1 : 0,regs->msr&MSR_ME ? 1 : 0,
+	       regs->msr&MSR_IR ? 1 : 0,
+	       regs->msr&MSR_DR ? 1 : 0);
+
+	printf("\n");
+	for (i = 0;  i < 32;  i++) {
+		if ((i % 8) == 0)
+		{
+			printf("GPR%02d: ", i);
+		}
+
+		printf("%08lX ", regs->gpr[i]);
+		if ((i % 8) == 7)
+		{
+			printf("\n");
+		}
+	}
+}
+
+
+static void _exception(int signr, struct pt_regs *regs)
+{
+	show_regs(regs);
+	print_backtrace((unsigned long *)regs->gpr[1]);
+	panic("Exception in kernel pc %lx signal %d",regs->nip,signr);
+}
+
+void MachineCheckException(struct pt_regs *regs)
+{
+	unsigned long fixup;
+
+	/* Probing PCI using config cycles cause this exception
+	 * when a device is not present.  Catch it and return to
+	 * the PCI exception handler.
+	 */
+	if ((fixup = search_exception_table(regs->nip)) != 0) {
+		regs->nip = fixup;
+		return;
+	}
+
+#if defined(CONFIG_CMD_KGDB)
+	if (debugger_exception_handler && (*debugger_exception_handler)(regs))
+		return;
+#endif
+
+	printf("Machine check in kernel mode.\n");
+	printf("Caused by (from msr): ");
+	printf("regs %p ",regs);
+	/* refer to 603e Manual (MPC603EUM/AD), chapter 4.5.2.1 */
+	switch( regs->msr & 0x000F0000)
+	{
+	case (0x80000000>>12) :
+		printf("Machine check signal - probably due to mm fault\n"
+			"with mmu off\n");
+		break;
+	case (0x80000000>>13) :
+		printf("Transfer error ack signal\n");
+		break;
+	case (0x80000000>>14) :
+		printf("Data parity signal\n");
+		break;
+	case (0x80000000>>15) :
+		printf("Address parity signal\n");
+		break;
+	default:
+		printf("Unknown values in msr\n");
+	}
+	show_regs(regs);
+	print_backtrace((unsigned long *)regs->gpr[1]);
+	panic("machine check");
+}
+
+void AlignmentException(struct pt_regs *regs)
+{
+#if defined(CONFIG_CMD_KGDB)
+	if (debugger_exception_handler && (*debugger_exception_handler)(regs))
+		return;
+#endif
+	show_regs(regs);
+	print_backtrace((unsigned long *)regs->gpr[1]);
+	panic("Alignment Exception");
+}
+
+void ProgramCheckException(struct pt_regs *regs)
+{
+#if defined(CONFIG_CMD_KGDB)
+	if (debugger_exception_handler && (*debugger_exception_handler)(regs))
+		return;
+#endif
+	show_regs(regs);
+	print_backtrace((unsigned long *)regs->gpr[1]);
+	panic("Program Check Exception");
+}
+
+void SoftEmuException(struct pt_regs *regs)
+{
+#if defined(CONFIG_CMD_KGDB)
+	if (debugger_exception_handler && (*debugger_exception_handler)(regs))
+		return;
+#endif
+	show_regs(regs);
+	print_backtrace((unsigned long *)regs->gpr[1]);
+	panic("Software Emulation Exception");
+}
+
+
+void UnknownException(struct pt_regs *regs)
+{
+#if defined(CONFIG_CMD_KGDB)
+	if (debugger_exception_handler && (*debugger_exception_handler)(regs))
+		return;
+#endif
+	printf("Bad trap at PC: %lx, SR: %lx, vector=%lx\n",
+	       regs->nip, regs->msr, regs->trap);
+	_exception(0, regs);
+}
+
+#if defined(CONFIG_CMD_BEDBUG)
+extern void do_bedbug_breakpoint(struct pt_regs *);
+#endif
+
+void DebugException(struct pt_regs *regs)
+{
+
+  printf("Debugger trap at @ %lx\n", regs->nip );
+  show_regs(regs);
+#if defined(CONFIG_CMD_BEDBUG)
+  do_bedbug_breakpoint( regs );
+#endif
+}
+
+/* Probe an address by reading.  If not present, return -1, otherwise
+ * return 0.
+ */
+int addr_probe(uint *addr)
+{
+#if 0
+	int	retval;
+
+	__asm__ __volatile__(			\
+		"1:	lwz %0,0(%1)\n"		\
+		"	eieio\n"		\
+		"	li %0,0\n"		\
+		"2:\n"				\
+		".section .fixup,\"ax\"\n"	\
+		"3:	li %0,-1\n"		\
+		"	b 2b\n"			\
+		".section __ex_table,\"a\"\n"	\
+		"	.align 2\n"		\
+		"	.long 1b,3b\n"		\
+		".text"				\
+		: "=r" (retval) : "r"(addr));
+
+	return (retval);
+#endif
+	return 0;
+}
diff --git a/arch/powerpc/cpu/mpc5xxx/u-boot-customlayout.lds b/arch/powerpc/cpu/mpc5xxx/u-boot-customlayout.lds
new file mode 100644
index 0000000000..5354172af0
--- /dev/null
+++ b/arch/powerpc/cpu/mpc5xxx/u-boot-customlayout.lds
@@ -0,0 +1,80 @@ 
+/*
+ * (C) Copyright 2003-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+OUTPUT_ARCH(powerpc)
+
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within  */
+    /* the sector layout of our flash chips!    XXX FIXME XXX   */
+
+    arch/powerpc/cpu/mpc5xxx/start.o	(.text*)
+    arch/powerpc/cpu/mpc5xxx/traps.o	(.text*)
+
+    . = DEFINED(env_offset) ? env_offset : .;
+    common/env_embedded.o		(.ppcenv*)
+
+    *(.text*)
+    . = ALIGN(16);
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    KEEP(*(.got))
+    _GOT2_TABLE_ = .;
+    KEEP(*(.got2))
+    _FIXUP_TABLE_ = .;
+    KEEP(*(.fixup))
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data*)
+    *(.sdata*)
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+
+  .u_boot_list : {
+	KEEP(*(SORT(.u_boot_list*)));
+  }
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   *(.bss*)
+   *(.sbss*)
+   *(COMMON)
+   . = ALIGN(4);
+  }
+  __bss_end = . ;
+  PROVIDE (end = .);
+}
diff --git a/arch/powerpc/cpu/mpc5xxx/u-boot-spl.lds b/arch/powerpc/cpu/mpc5xxx/u-boot-spl.lds
new file mode 100644
index 0000000000..1aa925e932
--- /dev/null
+++ b/arch/powerpc/cpu/mpc5xxx/u-boot-spl.lds
@@ -0,0 +1,44 @@ 
+/*
+ * Copyright 2012 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+MEMORY
+{
+	sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR,
+		LENGTH = CONFIG_SPL_BSS_MAX_SIZE
+	flash : ORIGIN = CONFIG_SPL_TEXT_BASE,
+		LENGTH = CONFIG_SYS_SPL_MAX_LEN
+}
+
+OUTPUT_ARCH(powerpc)
+ENTRY(_start)
+SECTIONS
+{
+	.text :
+	{
+		__start = .;
+		arch/powerpc/cpu/mpc5xxx/start.o	(.text)
+		*(.text*)
+	} > flash
+
+	. = ALIGN(4);
+	.data : { *(SORT_BY_ALIGNMENT(.data*)) } > flash
+
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } > flash
+
+	. = ALIGN(4);
+	.end_align : { *(.end_align*) } > flash
+	__spl_flash_end = .;
+
+	.bss :
+	{
+		. = ALIGN(4);
+		__bss_start = .;
+		*(.bss*)
+		. = ALIGN(4);
+		__bss_end = .;
+	} > sdram
+}
diff --git a/arch/powerpc/cpu/mpc5xxx/u-boot.lds b/arch/powerpc/cpu/mpc5xxx/u-boot.lds
new file mode 100644
index 0000000000..aa80d3dbb1
--- /dev/null
+++ b/arch/powerpc/cpu/mpc5xxx/u-boot.lds
@@ -0,0 +1,75 @@ 
+/*
+ * (C) Copyright 2003-2010
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+OUTPUT_ARCH(powerpc)
+
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  .text      :
+  {
+    arch/powerpc/cpu/mpc5xxx/start.o	(.text*)
+    arch/powerpc/cpu/mpc5xxx/traps.o	(.text*)
+    *(.text*)
+    . = ALIGN(16);
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    _GOT2_TABLE_ = .;
+    KEEP(*(.got2))
+    KEEP(*(.got))
+    _FIXUP_TABLE_ = .;
+    KEEP(*(.fixup))
+  }
+  __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data*)
+    *(.sdata*)
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	KEEP(*(SORT(.u_boot_list*)));
+  }
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   *(COMMON)
+   *(.bss*)
+   *(.sbss*)
+   . = ALIGN(4);
+  }
+  __bss_end = . ;
+  PROVIDE (end = .);
+}
diff --git a/arch/powerpc/cpu/mpc5xxx/usb.c b/arch/powerpc/cpu/mpc5xxx/usb.c
new file mode 100644
index 0000000000..bdf1484e25
--- /dev/null
+++ b/arch/powerpc/cpu/mpc5xxx/usb.c
@@ -0,0 +1,42 @@ 
+/*
+ * (C) Copyright 2007
+ * Markus Klotzbuecher, DENX Software Engineering <mk@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+
+#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT)
+
+#include <mpc5xxx.h>
+
+int usb_cpu_init(void)
+{
+	/* Set the USB Clock						     */
+	*(vu_long *)MPC5XXX_CDM_48_FDC = CONFIG_USB_CLOCK;
+
+#ifdef CONFIG_PSC3_USB /* USB is using the alternate configuration */
+	/* remove all PSC3 USB bits first before ORing in ours */
+	*(vu_long *)MPC5XXX_GPS_PORT_CONFIG &= ~0x00804f00;
+#else
+	/* remove all USB bits first before ORing in ours */
+	*(vu_long *)MPC5XXX_GPS_PORT_CONFIG &= ~0x00807000;
+#endif
+	/* Activate USB port						     */
+	*(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= CONFIG_USB_CONFIG;
+
+	return 0;
+}
+
+int usb_cpu_stop(void)
+{
+	return 0;
+}
+
+int usb_cpu_init_fail(void)
+{
+	return 0;
+}
+
+#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) */
diff --git a/arch/powerpc/cpu/ppc4xx/usb_ohci.c b/arch/powerpc/cpu/mpc5xxx/usb_ohci.c
similarity index 98%
copy from arch/powerpc/cpu/ppc4xx/usb_ohci.c
copy to arch/powerpc/cpu/mpc5xxx/usb_ohci.c
index 45f0093855..cf36954fe7 100644
--- a/arch/powerpc/cpu/ppc4xx/usb_ohci.c
+++ b/arch/powerpc/cpu/mpc5xxx/usb_ohci.c
@@ -1,5 +1,5 @@ 
 /*
- * URB OHCI HCD (Host Controller Driver) for USB on the PPC440EP.
+ * URB OHCI HCD (Host Controller Driver) for USB on the MPC5200.
  *
  * (C) Copyright 2003-2004
  * Gary Jennejohn, DENX Software Engineering <garyj@denx.de>
@@ -27,6 +27,8 @@ 
 #include <usb.h>
 #include "usb_ohci.h"
 
+#include <mpc5xxx.h>
+
 #define OHCI_USE_NPS		/* force NoPowerSwitching mode */
 #undef OHCI_VERBOSE_DEBUG	/* not always helpful */
 #undef DEBUG
@@ -55,13 +57,8 @@ 
 #define m16_swap(x) swap_16(x)
 #define m32_swap(x) swap_32(x)
 
-#if defined(CONFIG_405EZ) || defined(CONFIG_440EP) || defined(CONFIG_440EPX)
 #define ohci_cpu_to_le16(x) (x)
 #define ohci_cpu_to_le32(x) (x)
-#else
-#define ohci_cpu_to_le16(x) swap_16(x)
-#define ohci_cpu_to_le32(x) swap_32(x)
-#endif
 
 /* global ohci_t */
 static ohci_t gohci;
@@ -782,6 +779,7 @@  static td_t * dl_reverse_done_list (ohci_t *ohci)
 				} else
 					td_list->ed->hwHeadP &= ohci_cpu_to_le32 (0xfffffff2);
 			}
+			td_list->hwNextTD = 0;
 		}
 
 		td_list->next_dl_td = td_rev;
@@ -1450,6 +1448,20 @@  static char ohci_inited = 0;
 
 int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
 {
+
+	/* Set the USB Clock						     */
+	*(vu_long *)MPC5XXX_CDM_48_FDC = CONFIG_USB_CLOCK;
+
+#ifdef CONFIG_PSC3_USB /* USB is using the alternate configuration */
+	/* remove all PSC3 USB bits first before ORing in ours */
+	*(vu_long *)MPC5XXX_GPS_PORT_CONFIG &= ~0x00804f00;
+#else
+	/* remove all USB bits first before ORing in ours */
+	*(vu_long *)MPC5XXX_GPS_PORT_CONFIG &= ~0x00807000;
+#endif
+	/* Activate USB port						     */
+	*(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= CONFIG_USB_CONFIG;
+
 	memset (&gohci, 0, sizeof (ohci_t));
 	memset (&urb_priv, 0, sizeof (urb_priv_t));
 
@@ -1477,14 +1489,10 @@  int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
 	gohci.disabled = 1;
 	gohci.sleeping = 0;
 	gohci.irq = -1;
-#if defined(CONFIG_440EP)
-	gohci.regs = (struct ohci_regs *)(CONFIG_SYS_PERIPHERAL_BASE | 0x1000);
-#elif defined(CONFIG_440EPX) || defined(CONFIG_SYS_USB_HOST)
-	gohci.regs = (struct ohci_regs *)(CONFIG_SYS_USB_HOST);
-#endif
+	gohci.regs = (struct ohci_regs *)MPC5XXX_USB;
 
 	gohci.flags = 0;
-	gohci.slot_name = "ppc440";
+	gohci.slot_name = "mpc5200";
 
 	if (hc_reset (&gohci) < 0) {
 		hc_release_ohci (&gohci);
diff --git a/drivers/usb/host/ohci.h b/arch/powerpc/cpu/mpc5xxx/usb_ohci.h
similarity index 82%
copy from drivers/usb/host/ohci.h
copy to arch/powerpc/cpu/mpc5xxx/usb_ohci.h
index 2350831932..629b529a69 100644
--- a/drivers/usb/host/ohci.h
+++ b/arch/powerpc/cpu/mpc5xxx/usb_ohci.h
@@ -7,40 +7,30 @@ 
  * usb-ohci.h
  */
 
-/*
- * e.g. PCI controllers need this
- */
-
-#include <asm/io.h>
-
-#ifdef CONFIG_SYS_OHCI_SWAP_REG_ACCESS
-# define ohci_readl(a) __swap_32(readl(a))
-# define ohci_writel(v, a) writel(__swap_32(v), a)
-#else
-# define ohci_readl(a) readl(a)
-# define ohci_writel(v, a) writel(v, a)
-#endif /* CONFIG_SYS_OHCI_SWAP_REG_ACCESS */
 
-#if ARCH_DMA_MINALIGN > 16
-#define ED_ALIGNMENT ARCH_DMA_MINALIGN
-#else
-#define ED_ALIGNMENT 16
-#endif
-
-#if defined CONFIG_DM_USB && ARCH_DMA_MINALIGN > 32
-#define TD_ALIGNMENT ARCH_DMA_MINALIGN
-#else
-#define TD_ALIGNMENT 32
-#endif
-
-/* functions for doing board or CPU specific setup/cleanup */
-int usb_board_stop(void);
-
-int usb_cpu_init(void);
-int usb_cpu_stop(void);
-int usb_cpu_init_fail(void);
+static int cc_to_error[16] = {
+
+/* mapping of the OHCI CC status to error codes */
+	/* No  Error  */	       0,
+	/* CRC Error  */	       USB_ST_CRC_ERR,
+	/* Bit Stuff  */	       USB_ST_BIT_ERR,
+	/* Data Togg  */	       USB_ST_CRC_ERR,
+	/* Stall      */	       USB_ST_STALLED,
+	/* DevNotResp */	       -1,
+	/* PIDCheck   */	       USB_ST_BIT_ERR,
+	/* UnExpPID   */	       USB_ST_BIT_ERR,
+	/* DataOver   */	       USB_ST_BUF_ERR,
+	/* DataUnder  */	       USB_ST_BUF_ERR,
+	/* reservd    */	       -1,
+	/* reservd    */	       -1,
+	/* BufferOver */	       USB_ST_BUF_ERR,
+	/* BuffUnder  */	       USB_ST_BUF_ERR,
+	/* Not Access */	       -1,
+	/* Not Access */	       -1
+};
 
 /* ED States */
+
 #define ED_NEW		0x00
 #define ED_UNLINK	0x01
 #define ED_OPER		0x02
@@ -65,9 +55,8 @@  struct ed {
 	struct ed *ed_rm_list;
 
 	struct usb_device *usb_dev;
-	void *purb;
-	__u32 unused[2];
-} __attribute__((aligned(ED_ALIGNMENT)));
+	__u32 unused[3];
+} __attribute__((aligned(16)));
 typedef struct ed ed_t;
 
 
@@ -115,7 +104,6 @@  struct td {
 	__u32 hwNextTD;		/* Next TD Pointer */
 	__u32 hwBE;		/* Memory Buffer End Pointer */
 
-	__u16 hwPSW[MAXPSW];
 	__u8 unused;
 	__u8 index;
 	struct ed *ed;
@@ -125,7 +113,7 @@  struct td {
 	__u32 data;
 
 	__u32 unused2[2];
-} __attribute__((aligned(TD_ALIGNMENT)));
+} __attribute__((aligned(32)));
 typedef struct td td_t;
 
 #define OHCI_ED_SKIP	(1 << 14)
@@ -139,8 +127,8 @@  typedef struct td td_t;
 #define NUM_INTS 32	/* part of the OHCI standard */
 struct ohci_hcca {
 	__u32	int_table[NUM_INTS];	/* Interrupt ED table */
-	__u16	frame_no;		/* current frame number */
 	__u16	pad1;			/* set to 0 on each frame_no change */
+	__u16	frame_no;		/* current frame number */
 	__u32	done_head;		/* info returned for an interrupt */
 	u8		reserved_for_hc[116];
 } __attribute__((aligned(256)));
@@ -149,14 +137,12 @@  struct ohci_hcca {
 /*
  * Maximum number of root hub ports.
  */
-#ifndef CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS
-# error "CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS undefined!"
-#endif
+#define MAX_ROOT_PORTS	15	/* maximum OHCI root hub ports */
 
 /*
  * This is the structure of the OHCI controller's memory mapped I/O
- * region.  This is Memory Mapped I/O.	You must use the ohci_readl() and
- * ohci_writel() macros defined in this file to access these!!
+ * region.  This is Memory Mapped I/O.	You must use the readl() and
+ * writel() macros defined in asm/io.h to access these!!
  */
 struct ohci_regs {
 	/* control and status registers */
@@ -185,13 +171,10 @@  struct ohci_regs {
 		__u32	a;
 		__u32	b;
 		__u32	status;
-		__u32	portstatus[CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS];
+		__u32	portstatus[MAX_ROOT_PORTS];
 	} roothub;
 } __attribute__((aligned(32)));
 
-/* Some EHCI controls */
-#define EHCI_USBCMD_OFF		0x20
-#define EHCI_USBCMD_HCRESET	(1 << 1)
 
 /* OHCI CONTROL AND STATUS REGISTER MASKS */
 
@@ -347,31 +330,13 @@  typedef struct
 	ed_t *ed;
 	__u16 length;	/* number of tds associated with this request */
 	__u16 td_cnt;	/* number of tds already serviced */
-	struct usb_device *dev;
 	int   state;
 	unsigned long pipe;
-	void *transfer_buffer;
-	int transfer_buffer_length;
-	int interval;
 	int actual_length;
-	int finished;
 	td_t *td[N_URB_TD];	/* list pointer to all corresponding TDs associated with this request */
 } urb_priv_t;
 #define URB_DEL 1
 
-#define NUM_EDS 8		/* num of preallocated endpoint descriptors */
-
-#define NUM_TD 64		/* we need more TDs than EDs */
-
-#define NUM_INT_DEVS 8		/* num of ohci_dev structs for int endpoints */
-
-typedef struct ohci_device {
-	ed_t ed[NUM_EDS] __aligned(ED_ALIGNMENT);
-	td_t tds[NUM_TD] __aligned(TD_ALIGNMENT);
-	int ed_cnt;
-	int devnum;
-} ohci_dev_t;
-
 /*
  * This is the full ohci controller description
  *
@@ -381,9 +346,6 @@  typedef struct ohci_device {
 
 
 typedef struct ohci {
-	/* this allocates EDs for all possible endpoints */
-	struct ohci_device ohci_dev __aligned(TD_ALIGNMENT);
-	struct ohci_device int_dev[NUM_INT_DEVS] __aligned(TD_ALIGNMENT);
 	struct ohci_hcca *hcca;		/* hcca */
 	/*dma_addr_t hcca_dma;*/
 
@@ -394,7 +356,6 @@  typedef struct ohci {
 
 	struct ohci_regs *regs; /* OHCI controller's memory */
 
-	int ohci_int_load[32];	 /* load of the 32 Interrupt Chains (for load balancing)*/
 	ed_t *ed_rm_list[2];	 /* lists of all endpoints to be removed */
 	ed_t *ed_bulktail;	 /* last endpoint of bulk list */
 	ed_t *ed_controltail;	 /* last endpoint of control list */
@@ -406,9 +367,52 @@  typedef struct ohci {
 	const char	*slot_name;
 } ohci_t;
 
-#ifdef CONFIG_DM_USB
-extern struct dm_usb_ops ohci_usb_ops;
+#define NUM_EDS 8		/* num of preallocated endpoint descriptors */
+
+struct ohci_device {
+	ed_t	ed[NUM_EDS];
+	int ed_cnt;
+};
+
+/* hcd */
+/* endpoint */
+static int ep_link(ohci_t * ohci, ed_t * ed);
+static int ep_unlink(ohci_t * ohci, ed_t * ed);
+static ed_t * ep_add_ed(struct usb_device * usb_dev, unsigned long pipe);
+
+/*-------------------------------------------------------------------------*/
+
+/* we need more TDs than EDs */
+#define NUM_TD 64
 
-int ohci_register(struct udevice *dev, struct ohci_regs *regs);
-int ohci_deregister(struct udevice *dev);
-#endif
+/* +1 so we can align the storage */
+td_t gtd[NUM_TD+1];
+/* pointers to aligned storage */
+td_t *ptd;
+
+/* TDs ... */
+static inline struct td *
+td_alloc (struct usb_device *usb_dev)
+{
+	int i;
+	struct td	*td;
+
+	td = NULL;
+	for (i = 0; i < NUM_TD; i++)
+	{
+		if (ptd[i].usb_dev == NULL)
+		{
+			td = &ptd[i];
+			td->usb_dev = usb_dev;
+			break;
+		}
+	}
+
+	return td;
+}
+
+static inline void
+ed_free (struct ed *ed)
+{
+	ed->usb_dev = NULL;
+}
diff --git a/arch/powerpc/cpu/ppc4xx/usb_ohci.c b/arch/powerpc/cpu/ppc4xx/usb_ohci.c
index 45f0093855..27423e3779 100644
--- a/arch/powerpc/cpu/ppc4xx/usb_ohci.c
+++ b/arch/powerpc/cpu/ppc4xx/usb_ohci.c
@@ -782,6 +782,9 @@  static td_t * dl_reverse_done_list (ohci_t *ohci)
 				} else
 					td_list->ed->hwHeadP &= ohci_cpu_to_le32 (0xfffffff2);
 			}
+#ifdef CONFIG_MPC5200
+			td_list->hwNextTD = 0;
+#endif
 		}
 
 		td_list->next_dl_td = td_rev;
diff --git a/arch/powerpc/cpu/ppc4xx/usb_ohci.h b/arch/powerpc/cpu/ppc4xx/usb_ohci.h
index 9e7da0d162..2c3dc4f99c 100644
--- a/arch/powerpc/cpu/ppc4xx/usb_ohci.h
+++ b/arch/powerpc/cpu/ppc4xx/usb_ohci.h
@@ -125,8 +125,13 @@  typedef struct td td_t;
 #define NUM_INTS 32		/* part of the OHCI standard */
 struct ohci_hcca {
 	__u32 int_table[NUM_INTS];	/* Interrupt ED table */
+#if defined(CONFIG_MPC5200)
+	__u16 pad1;		/* set to 0 on each frame_no change */
+	__u16 frame_no;		/* current frame number */
+#else
 	__u16 frame_no;		/* current frame number */
 	__u16 pad1;		/* set to 0 on each frame_no change */
+#endif
 	__u32 done_head;	/* info returned for an interrupt */
 	u8 reserved_for_hc[116];
 } __attribute__((aligned(256)));
diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h
index d0c3fa05f8..cdf4be2c76 100644
--- a/arch/powerpc/include/asm/global_data.h
+++ b/arch/powerpc/include/asm/global_data.h
@@ -81,6 +81,13 @@  struct arch_global_data {
 #if defined(CONFIG_E500)
 	u32 used_tlb_cams[(CONFIG_SYS_NUM_TLBCAMS+31)/32];
 #endif
+#if defined(CONFIG_MPC5xxx)
+	unsigned long ipb_clk;
+#endif
+#if defined(CONFIG_MPC512X)
+	u32 ips_clk;
+	u32 csb_clk;
+#endif /* CONFIG_MPC512X */
 	unsigned long reset_status;	/* reset status register at boot */
 #if defined(CONFIG_MPC83xx)
 	unsigned long arbiter_event_attributes;
diff --git a/arch/powerpc/include/asm/immap_512x.h b/arch/powerpc/include/asm/immap_512x.h
new file mode 100644
index 0000000000..bed80aa933
--- /dev/null
+++ b/arch/powerpc/include/asm/immap_512x.h
@@ -0,0 +1,1264 @@ 
+/*
+ * (C) Copyright 2007-2009 DENX Software Engineering
+ *
+ * MPC512x Internal Memory Map
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Based on the MPC83xx header.
+ */
+
+#ifndef __IMMAP_512x__
+#define __IMMAP_512x__
+
+#include <asm/types.h>
+#if defined(CONFIG_E300)
+#include <asm/e300.h>
+#endif
+
+/*
+ * System reset offset (PowerPC standard)
+ */
+#define EXC_OFF_SYS_RESET	0x0100
+#define	_START_OFFSET		EXC_OFF_SYS_RESET
+
+#define SPR_5121E		0x80180000
+
+/*
+ * IMMRBAR - Internal Memory Register Base Address
+ */
+#define CONFIG_DEFAULT_IMMR	0xFF400000	/* Default IMMR base address */
+#define IMMRBAR			0x0000		/* Register offset to immr */
+#define IMMRBAR_BASE_ADDR	0xFFF00000	/* Base address mask */
+#define IMMRBAR_RES		~(IMMRBAR_BASE_ADDR)
+
+
+#ifndef __ASSEMBLY__
+typedef struct law512x {
+	u32 bar;	/* Base Addr Register */
+	u32 ar;		/* Attributes Register */
+} law512x_t;
+
+/*
+ * System configuration registers
+ */
+typedef struct sysconf512x {
+	u32 immrbar;		/* Internal memory map base address register */
+	u8 res0[0x1c];
+	u32 lpbaw;		/* LP Boot Access Window */
+	u32 lpcs0aw;		/* LP CS0 Access Window */
+	u32 lpcs1aw;		/* LP CS1 Access Window */
+	u32 lpcs2aw;		/* LP CS2 Access Window */
+	u32 lpcs3aw;		/* LP CS3 Access Window */
+	u32 lpcs4aw;		/* LP CS4 Access Window */
+	u32 lpcs5aw;		/* LP CS5 Access Window */
+	u32 lpcs6aw;		/* LP CS6 Access Window */
+	u32 lpcs7aw;		/* LP CS7 Access Window */
+	u8 res1[0x1c];
+	law512x_t pcilaw[3];	/* PCI Local Access Window 0-2 Registers */
+	u8 res2[0x28];
+	law512x_t ddrlaw;	/* DDR Local Access Window */
+	u8 res3[0x18];
+	u32 mbxbar;		/* MBX Base Address */
+	u32 srambar;		/* SRAM Base Address */
+	u32 nfcbar;		/* NFC Base Address */
+	u8 res4[0x34];
+	u32 spridr;		/* System Part and Revision ID Register */
+	u32 spcr;		/* System Priority Configuration Register */
+	u8 res5[0xf8];
+} sysconf512x_t;
+
+#define LAWBAR_BAR	0xFFFFF000	/* Base address mask */
+
+/*
+ * Watch Dog Timer (WDT) Registers
+ */
+typedef struct wdt512x {
+	u8 res0[4];
+	u32 swcrr;		/* System watchdog control register */
+	u32 swcnr;		/* System watchdog count register */
+	u8 res1[2];
+	u16 swsrr;		/* System watchdog service register */
+	u8 res2[0xF0];
+} wdt512x_t;
+
+/*
+ * RTC Module Registers
+ */
+typedef struct rtclk512x {
+	u8 fixme[0x100];
+} rtclk512x_t;
+
+/*
+ * General Purpose Timer
+ */
+typedef struct gpt512x {
+	u8 fixme[0x100];
+} gpt512x_t;
+
+/*
+ * Integrated Programmable Interrupt Controller
+ */
+typedef struct ipic512x {
+	u8 fixme[0x100];
+} ipic512x_t;
+
+/*
+ * System Arbiter Registers
+ */
+typedef struct arbiter512x {
+	u32 acr;		/* Arbiter Configuration Register */
+	u32 atr;		/* Arbiter Timers Register */
+	u32 ater;		/* Arbiter Transfer Error Register */
+	u32 aer;		/* Arbiter Event Register */
+	u32 aidr;		/* Arbiter Interrupt Definition Register */
+	u32 amr;		/* Arbiter Mask Register */
+	u32 aeatr;		/* Arbiter Event Attributes Register */
+	u32 aeadr;		/* Arbiter Event Address Register */
+	u32 aerr;		/* Arbiter Event Response Register */
+	u8 res1[0xDC];
+} arbiter512x_t;
+
+/*
+ * Reset Module
+ */
+typedef struct reset512x {
+	u32 rcwl;		/* Reset Configuration Word Low Register */
+	u32 rcwh;		/* Reset Configuration Word High Register */
+	u8 res0[8];
+	u32 rsr;		/* Reset Status Register */
+	u32 rmr;		/* Reset Mode Register */
+	u32 rpr;		/* Reset protection Register */
+	u32 rcr;		/* Reset Control Register */
+	u32 rcer;		/* Reset Control Enable Register */
+	u8 res1[0xDC];
+} reset512x_t;
+
+/* RSR - Reset Status Register */
+#define RSR_SWSR	0x00002000	/* software soft reset */
+#define RSR_SWHR	0x00001000	/* software hard reset */
+#define RSR_JHRS	0x00000200	/* jtag hreset */
+#define RSR_JSRS	0x00000100	/* jtag sreset status */
+#define RSR_CSHR	0x00000010	/* checkstop reset status */
+#define RSR_SWRS	0x00000008	/* software watchdog reset status */
+#define RSR_BMRS	0x00000004	/* bus monitop reset status */
+#define RSR_SRS		0x00000002	/* soft reset status */
+#define RSR_HRS		0x00000001	/* hard reset status */
+#define RSR_RES		~(RSR_SWSR | RSR_SWHR |\
+			 RSR_JHRS | RSR_JSRS | RSR_CSHR | RSR_SWRS |\
+			 RSR_BMRS | RSR_SRS | RSR_HRS)
+
+/* RMR - Reset Mode Register */
+#define RMR_CSRE	0x00000001	/* checkstop reset enable */
+#define RMR_CSRE_SHIFT	0
+#define RMR_RES		(~(RMR_CSRE))
+
+/* RCR - Reset Control Register */
+#define RCR_SWHR	0x00000002	/* software hard reset */
+#define RCR_SWSR	0x00000001	/* software soft reset */
+#define RCR_RES		(~(RCR_SWHR | RCR_SWSR))
+
+/* RCER - Reset Control Enable Register */
+#define RCER_CRE	0x00000001	/* software hard reset */
+#define RCER_RES	(~(RCER_CRE))
+
+/*
+ * Clock Module
+ */
+typedef struct clk512x {
+	u32 spmr;		/* System PLL Mode Register */
+	u32 sccr[2];		/* System Clock Control Registers */
+	u32 scfr[2];		/* System Clock Frequency Registers */
+	u8 res0[4];
+	u32 bcr;		/* Bread Crumb Register */
+	u32 pscccr[12];		/* PSC0-11 Clock Control Registers */
+	u32 spccr;		/* SPDIF Clock Control Register */
+	u32 cccr;		/* CFM Clock Control Register */
+	u32 dccr;		/* DIU Clock Control Register */
+	u32 msccr[4];		/* MSCAN1-4 Clock Control Registers */
+	u8 res1[0x98];
+} clk512x_t;
+
+/* SPMR - System PLL Mode Register */
+#define SPMR_SPMF		0x0F000000
+#define SPMR_SPMF_SHIFT		24
+#define SPMR_CPMF		0x000F0000
+#define SPMR_CPMF_SHIFT		16
+
+/* System Clock Control Register 1 commands */
+#define CLOCK_SCCR1_CFG_EN		0x80000000
+#define CLOCK_SCCR1_LPC_EN		0x40000000
+#define CLOCK_SCCR1_NFC_EN		0x20000000
+#define CLOCK_SCCR1_PATA_EN		0x10000000
+#define CLOCK_SCCR1_PSC_EN(cn)		(0x08000000 >> (cn))
+#define CLOCK_SCCR1_PSCFIFO_EN		0x00008000
+#define CLOCK_SCCR1_SATA_EN		0x00004000
+#define CLOCK_SCCR1_FEC_EN		0x00002000
+#define CLOCK_SCCR1_TPR_EN		0x00001000
+#define CLOCK_SCCR1_PCI_EN		0x00000800
+#define CLOCK_SCCR1_DDR_EN		0x00000400
+
+/* System Clock Control Register 2 commands */
+#define CLOCK_SCCR2_DIU_EN		0x80000000
+#define CLOCK_SCCR2_AXE_EN		0x40000000
+#define CLOCK_SCCR2_MEM_EN		0x20000000
+#define CLOCK_SCCR2_USB1_EN		0x10000000
+#define CLOCK_SCCR2_USB2_EN		0x08000000
+#define CLOCK_SCCR2_I2C_EN		0x04000000
+#define CLOCK_SCCR2_BDLC_EN		0x02000000
+#define CLOCK_SCCR2_SDHC_EN		0x01000000
+#define CLOCK_SCCR2_SPDIF_EN		0x00800000
+#define CLOCK_SCCR2_MBX_BUS_EN		0x00400000
+#define CLOCK_SCCR2_MBX_EN		0x00200000
+#define CLOCK_SCCR2_MBX_3D_EN		0x00100000
+#define CLOCK_SCCR2_IIM_EN		0x00080000
+
+/* SCFR1 System Clock Frequency Register 1 */
+#ifndef SCFR1_IPS_DIV
+#define SCFR1_IPS_DIV		0x3
+#endif
+#define SCFR1_IPS_DIV_MASK	0x03800000
+#define SCFR1_IPS_DIV_SHIFT	23
+
+#define SCFR1_PCI_DIV		0x6
+#define SCFR1_PCI_DIV_MASK	0x00700000
+#define SCFR1_PCI_DIV_SHIFT	20
+
+#define SCFR1_LPC_DIV_MASK	0x00003800
+#define SCFR1_LPC_DIV_SHIFT	11
+
+#define SCFR1_NFC_DIV_MASK	0x00000700
+#define SCFR1_NFC_DIV_SHIFT	8
+
+#define SCFR1_DIU_DIV_MASK	0x000000FF
+#define SCFR1_DIU_DIV_SHIFT	0
+
+/* SCFR2 System Clock Frequency Register 2 */
+#define SCFR2_SYS_DIV		0xFC000000
+#define SCFR2_SYS_DIV_SHIFT	26
+
+/* SPCR - System Priority Configuration Register */
+#define SPCR_TBEN	0x00400000	/* E300 core time base unit enable */
+
+/*
+ * Power Management Control Module
+ */
+typedef struct pmc512x {
+	u8 fixme[0x100];
+} pmc512x_t;
+
+/*
+ * General purpose I/O module
+ */
+typedef struct gpio512x {
+	u32 gpdir;
+	u32 gpodr;
+	u32 gpdat;
+	u32 gpier;
+	u32 gpimr;
+	u32 gpicr1;
+	u32 gpicr2;
+	u8 res0[0xE4];
+} gpio512x_t;
+
+/*
+ * DDR Memory Controller Memory Map
+ */
+typedef struct ddr512x {
+	u32 ddr_sys_config;	/* System Configuration Register */
+	u32 ddr_time_config0;	/* Timing Configuration Register */
+	u32 ddr_time_config1;	/* Timing Configuration Register */
+	u32 ddr_time_config2;	/* Timing Configuration Register */
+	u32 ddr_command;	/* Command Register */
+	u32 ddr_compact_command;	/* Compact Command Register */
+	u32 self_refresh_cmd_0;	/* Enter/Exit Self Refresh Registers */
+	u32 self_refresh_cmd_1;	/* Enter/Exit Self Refresh Registers */
+	u32 self_refresh_cmd_2;	/* Enter/Exit Self Refresh Registers */
+	u32 self_refresh_cmd_3;	/* Enter/Exit Self Refresh Registers */
+	u32 self_refresh_cmd_4;	/* Enter/Exit Self Refresh Registers */
+	u32 self_refresh_cmd_5;	/* Enter/Exit Self Refresh Registers */
+	u32 self_refresh_cmd_6;	/* Enter/Exit Self Refresh Registers */
+	u32 self_refresh_cmd_7;	/* Enter/Exit Self Refresh Registers */
+	u32 dqs_config_offset_count;	/* DQS Config Offset Count */
+	u32 dqs_config_offset_time;	/* DQS Config Offset Time */
+	u32 DQS_delay_status;	/* DQS Delay Status */
+	u32 res0[0xF];
+	u32 prioman_config1;	/* Priority Manager Configuration */
+	u32 prioman_config2;	/* Priority Manager Configuration */
+	u32 hiprio_config;	/* High Priority Configuration */
+	u32 lut_table0_main_upper;	/* LUT0 Main Upper */
+	u32 lut_table1_main_upper;	/* LUT1 Main Upper */
+	u32 lut_table2_main_upper;	/* LUT2 Main Upper */
+	u32 lut_table3_main_upper;	/* LUT3 Main Upper */
+	u32 lut_table4_main_upper;	/* LUT4 Main Upper */
+	u32 lut_table0_main_lower;	/* LUT0 Main Lower */
+	u32 lut_table1_main_lower;	/* LUT1 Main Lower */
+	u32 lut_table2_main_lower;	/* LUT2 Main Lower */
+	u32 lut_table3_main_lower;	/* LUT3 Main Lower */
+	u32 lut_table4_main_lower;	/* LUT4 Main Lower */
+	u32 lut_table0_alternate_upper;	/* LUT0 Alternate Upper */
+	u32 lut_table1_alternate_upper; /* LUT1 Alternate Upper */
+	u32 lut_table2_alternate_upper; /* LUT2 Alternate Upper */
+	u32 lut_table3_alternate_upper; /* LUT3 Alternate Upper */
+	u32 lut_table4_alternate_upper; /* LUT4 Alternate Upper */
+	u32 lut_table0_alternate_lower; /* LUT0 Alternate Lower */
+	u32 lut_table1_alternate_lower; /* LUT1 Alternate Lower */
+	u32 lut_table2_alternate_lower; /* LUT2 Alternate Lower */
+	u32 lut_table3_alternate_lower; /* LUT3 Alternate Lower */
+	u32 lut_table4_alternate_lower; /* LUT4 Alternate Lower */
+	u32 performance_monitor_config;
+	u32 event_time_counter;
+	u32 event_time_preset;
+	u32 performance_monitor1_address_low;
+	u32 performance_monitor2_address_low;
+	u32 performance_monitor1_address_hi;
+	u32 performance_monitor2_address_hi;
+	u32 res1[2];
+	u32 performance_monitor1_read_counter;
+	u32 performance_monitor2_read_counter;
+	u32 performance_monitor1_write_counter;
+	u32 performance_monitor2_write_counter;
+	u32 granted_ack_counter0;
+	u32 granted_ack_counter1;
+	u32 granted_ack_counter2;
+	u32 granted_ack_counter3;
+	u32 granted_ack_counter4;
+	u32 cumulative_wait_counter0;
+	u32 cumulative_wait_counter1;
+	u32 cumulative_wait_counter2;
+	u32 cumulative_wait_counter3;
+	u32 cumulative_wait_counter4;
+	u32 summed_priority_counter0;
+	u32 summed_priority_counter1;
+	u32 summed_priority_counter2;
+	u32 summed_priority_counter3;
+	u32 summed_priority_counter4;
+	u32 res2[0x3AD];
+} ddr512x_t;
+
+/* MDDRC SYS CFG and Timing CFG0 Registers */
+#define MDDRC_SYS_CFG_EN	0xF0000000
+#define MDDRC_SYS_CFG_CKE_MASK	0x40000000
+#define MDDRC_SYS_CFG_CMD_MASK	0x10000000
+#define MDDRC_REFRESH_ZERO_MASK	0x0000FFFF
+
+/*
+ * DDR Memory Controller Configuration settings
+ */
+typedef struct ddr512x_config {
+	u32 ddr_sys_config;	/* System Configuration Register */
+	u32 ddr_time_config0;	/* Timing Configuration Register */
+	u32 ddr_time_config1;	/* Timing Configuration Register */
+	u32 ddr_time_config2;	/* Timing Configuration Register */
+} ddr512x_config_t;
+
+typedef struct sdram_conf_s {
+	unsigned long size;
+	ddr512x_config_t cfg;
+} sdram_conf_t;
+
+/*
+ * DMA/Messaging Unit
+ */
+typedef struct dma512x {
+	u8 fixme[0x1800];
+} dma512x_t;
+
+/*
+ * PCI Software Configuration Registers
+ */
+typedef struct pciconf512x {
+	u32 config_address;
+	u32 config_data;
+	u32 int_ack;
+	u8 res[116];
+} pciconf512x_t;
+
+/*
+ * PCI Outbound Translation Register
+ */
+typedef struct pci_outbound_window {
+	u32 potar;
+	u8 res0[4];
+	u32 pobar;
+	u8 res1[4];
+	u32 pocmr;
+	u8 res2[4];
+} pot512x_t;
+
+/* POTAR - PCI Outbound Translation Address Register */
+#define POTAR_TA_MASK	0x000fffff
+
+/* POBAR - PCI Outbound Base Address Register */
+#define POBAR_BA_MASK	0x000fffff
+
+/* POCMR - PCI Outbound Comparision Mask Register */
+#define POCMR_EN	0x80000000
+#define POCMR_IO	0x40000000	/* 0-memory space 1-I/O space */
+#define POCMR_PRE	0x20000000	/* prefetch enable */
+#define POCMR_SBS	0x00100000	/* special byte swap enable */
+#define POCMR_CM_MASK	0x000fffff
+#define POCMR_CM_4G	0x00000000
+#define POCMR_CM_2G	0x00080000
+#define POCMR_CM_1G	0x000C0000
+#define POCMR_CM_512M	0x000E0000
+#define POCMR_CM_256M	0x000F0000
+#define POCMR_CM_128M	0x000F8000
+#define POCMR_CM_64M	0x000FC000
+#define POCMR_CM_32M	0x000FE000
+#define POCMR_CM_16M	0x000FF000
+#define POCMR_CM_8M	0x000FF800
+#define POCMR_CM_4M	0x000FFC00
+#define POCMR_CM_2M	0x000FFE00
+#define POCMR_CM_1M	0x000FFF00
+#define POCMR_CM_512K	0x000FFF80
+#define POCMR_CM_256K	0x000FFFC0
+#define POCMR_CM_128K	0x000FFFE0
+#define POCMR_CM_64K	0x000FFFF0
+#define POCMR_CM_32K	0x000FFFF8
+#define POCMR_CM_16K	0x000FFFFC
+#define POCMR_CM_8K	0x000FFFFE
+#define POCMR_CM_4K	0x000FFFFF
+
+/*
+ * Sequencer
+ */
+typedef struct ios512x {
+	pot512x_t pot[6];
+	u8 res0[0x60];
+	u32 pmcr;
+	u8 res1[4];
+	u32 dtcr;
+	u8 res2[4];
+} ios512x_t;
+
+/*
+ * PCI Controller
+ */
+typedef struct pcictrl512x {
+	u32 esr;
+	u32 ecdr;
+	u32 eer;
+	u32 eatcr;
+	u32 eacr;
+	u32 eeacr;
+	u32 edlcr;
+	u32 edhcr;
+	u32 gcr;
+	u32 ecr;
+	u32 gsr;
+	u8 res0[12];
+	u32 pitar2;
+	u8 res1[4];
+	u32 pibar2;
+	u32 piebar2;
+	u32 piwar2;
+	u8 res2[4];
+	u32 pitar1;
+	u8 res3[4];
+	u32 pibar1;
+	u32 piebar1;
+	u32 piwar1;
+	u8 res4[4];
+	u32 pitar0;
+	u8 res5[4];
+	u32 pibar0;
+	u8 res6[4];
+	u32 piwar0;
+	u8 res7[132];
+} pcictrl512x_t;
+
+
+/* PITAR - PCI Inbound Translation Address Register
+ */
+#define PITAR_TA_MASK	0x000fffff
+
+/* PIBAR - PCI Inbound Base/Extended Address Register
+ */
+#define PIBAR_MASK	0xffffffff
+#define PIEBAR_EBA_MASK	0x000fffff
+
+/* PIWAR - PCI Inbound Windows Attributes Register
+ */
+#define PIWAR_EN	0x80000000
+#define PIWAR_SBS	0x40000000
+#define PIWAR_PF	0x20000000
+#define PIWAR_RTT_MASK	0x000f0000
+#define PIWAR_RTT_NO_SNOOP 0x00040000
+#define PIWAR_RTT_SNOOP	0x00050000
+#define PIWAR_WTT_MASK	0x0000f000
+#define PIWAR_WTT_NO_SNOOP 0x00004000
+#define PIWAR_WTT_SNOOP	0x00005000
+
+/*
+ * MSCAN
+ */
+typedef struct mscan512x {
+	u8 fixme[0x100];
+} mscan512x_t;
+
+/*
+ * BDLC
+ */
+typedef struct bdlc512x {
+	u8 fixme[0x100];
+} bdlc512x_t;
+
+/*
+ * SDHC
+ */
+typedef struct sdhc512x {
+	u8 fixme[0x100];
+} sdhc512x_t;
+
+/*
+ * SPDIF
+ */
+typedef struct spdif512x {
+	u8 fixme[0x100];
+} spdif512x_t;
+
+/*
+ * I2C
+ */
+typedef struct i2c512x_dev {
+	volatile u32 madr;		/* I2Cn + 0x00 */
+	volatile u32 mfdr;		/* I2Cn + 0x04 */
+	volatile u32 mcr;		/* I2Cn + 0x08 */
+	volatile u32 msr;		/* I2Cn + 0x0C */
+	volatile u32 mdr;		/* I2Cn + 0x10 */
+	u8 res0[0x0C];
+} i2c512x_dev_t;
+
+/* Number of I2C buses */
+#define I2C_BUS_CNT	3
+
+typedef struct i2c512x {
+	i2c512x_dev_t dev[I2C_BUS_CNT];
+	volatile u32 icr;
+	volatile u32 mifr;
+	u8 res0[0x98];
+} i2c512x_t;
+
+/* I2Cn control register bits */
+#define I2C_EN		0x80
+#define I2C_IEN		0x40
+#define I2C_STA		0x20
+#define I2C_TX		0x10
+#define I2C_TXAK	0x08
+#define I2C_RSTA	0x04
+#define I2C_INIT_MASK	(I2C_EN | I2C_STA | I2C_TX | I2C_RSTA)
+
+/* I2Cn status register bits */
+#define I2C_CF		0x80
+#define I2C_AAS		0x40
+#define I2C_BB		0x20
+#define I2C_AL		0x10
+#define I2C_SRW		0x04
+#define I2C_IF		0x02
+#define I2C_RXAK	0x01
+
+/*
+ * AXE
+ */
+typedef struct axe512x {
+	u8 fixme[0x100];
+} axe512x_t;
+
+/*
+ * DIU
+ */
+typedef struct diu512x {
+	u8 fixme[0x100];
+} diu512x_t;
+
+/*
+ * CFM
+ */
+typedef struct cfm512x {
+	u8 fixme[0x100];
+} cfm512x_t;
+
+/*
+ * FEC
+ */
+typedef struct fec512x {
+	u32	fec_id;		/* FEC_ID register */
+	u32	ievent;		/* Interrupt event register */
+	u32	imask;		/* Interrupt mask register */
+	u32	reserved_01;
+	u32	r_des_active;	/* Receive ring updated flag */
+	u32	x_des_active;	/* Transmit ring updated flag */
+	u32	reserved_02[3];
+	u32	ecntrl;		/* Ethernet control register */
+	u32	reserved_03[6];
+	u32	mii_data;	/* MII data register */
+	u32	mii_speed;	/* MII speed register */
+	u32	reserved_04[7];
+	u32	mib_control;	/* MIB control/status register */
+	u32	reserved_05[7];
+	u32	r_cntrl;	/* Receive control register */
+	u32	r_hash;		/* Receive hash */
+	u32	reserved_06[14];
+	u32	x_cntrl;	/* Transmit control register */
+	u32	reserved_07[7];
+	u32	paddr1;		/* Physical address low */
+	u32	paddr2;		/* Physical address high + type field */
+	u32	op_pause;	/* Opcode + pause duration */
+	u32	reserved_08[10];
+	u32	iaddr1;		/* Upper 32 bits of individual hash table */
+	u32	iaddr2;		/* Lower 32 bits of individual hash table */
+	u32	gaddr1;		/* Upper 32 bits of group hash table */
+	u32	gaddr2;		/* Lower 32 bits of group hash table */
+	u32	reserved_09[7];
+	u32	x_wmrk;		/* Transmit FIFO watermark */
+	u32	reserved_10;
+	u32	r_bound;	/* End of RAM */
+	u32	r_fstart;	/* Receive FIFO start address */
+	u32	reserved_11[11];
+	u32	r_des_start;	/* Beginning of receive descriptor ring */
+	u32	x_des_start;	/* Pointer to beginning of transmit descriptor ring */
+	u32	r_buff_size;	/* Receive buffer size */
+	u32	reserved_12[26];
+	u32	dma_control;	/* DMA control for IP bus, AMBA IF + DMA revision */
+	u32	reserved_13[2];
+
+	u32	mib[128];	/* MIB Block Counters */
+
+	u32	fifo[256];	/*  used by FEC, can only be accessed by DMA */
+} fec512x_t;
+
+/*
+ * ULPI
+ */
+typedef struct ulpi512x {
+	u8 fixme[0x600];
+} ulpi512x_t;
+
+/*
+ * UTMI
+ */
+typedef struct utmi512x {
+	u8 fixme[0x3000];
+} utmi512x_t;
+
+/*
+ * PCI DMA
+ */
+typedef struct pcidma512x {
+	u8 fixme[0x300];
+} pcidma512x_t;
+
+/*
+ * IO Control
+ */
+typedef struct ioctrl512x {
+	u32	io_control_mem;			/* MEM pad ctrl reg */
+	u32	io_control_gp;			/* GP pad ctrl reg */
+	u32	io_control_lpc_clk;		/* LPC_CLK pad ctrl reg */
+	u32	io_control_lpc_oe;		/* LPC_OE pad ctrl reg */
+	u32	io_control_lpc_rw;		/* LPC_R/W pad ctrl reg */
+	u32	io_control_lpc_ack;		/* LPC_ACK pad ctrl reg */
+	u32	io_control_lpc_cs0;		/* LPC_CS0 pad ctrl reg */
+	u32	io_control_nfc_ce0;		/* NFC_CE0 pad ctrl reg */
+	u32	io_control_lpc_cs1;		/* LPC_CS1 pad ctrl reg */
+	u32	io_control_lpc_cs2;		/* LPC_CS2 pad ctrl reg */
+	u32	io_control_lpc_ax03;		/* LPC_AX03 pad ctrl reg */
+	u32	io_control_emb_ax02;		/* EMB_AX02 pad ctrl reg */
+	u32	io_control_emb_ax01;		/* EMB_AX01 pad ctrl reg */
+	u32	io_control_emb_ax00;		/* EMB_AX00 pad ctrl reg */
+	u32	io_control_emb_ad31;		/* EMB_AD31 pad ctrl reg */
+	u32	io_control_emb_ad30;		/* EMB_AD30 pad ctrl reg */
+	u32	io_control_emb_ad29;		/* EMB_AD29 pad ctrl reg */
+	u32	io_control_emb_ad28;		/* EMB_AD28 pad ctrl reg */
+	u32	io_control_emb_ad27;		/* EMB_AD27 pad ctrl reg */
+	u32	io_control_emb_ad26;		/* EMB_AD26 pad ctrl reg */
+	u32	io_control_emb_ad25;		/* EMB_AD25 pad ctrl reg */
+	u32	io_control_emb_ad24;		/* EMB_AD24 pad ctrl reg */
+	u32	io_control_emb_ad23;		/* EMB_AD23 pad ctrl reg */
+	u32	io_control_emb_ad22;		/* EMB_AD22 pad ctrl reg */
+	u32	io_control_emb_ad21;		/* EMB_AD21 pad ctrl reg */
+	u32	io_control_emb_ad20;		/* EMB_AD20 pad ctrl reg */
+	u32	io_control_emb_ad19;		/* EMB_AD19 pad ctrl reg */
+	u32	io_control_emb_ad18;		/* EMB_AD18 pad ctrl reg */
+	u32	io_control_emb_ad17;		/* EMB_AD17 pad ctrl reg */
+	u32	io_control_emb_ad16;		/* EMB_AD16 pad ctrl reg */
+	u32	io_control_emb_ad15;		/* EMB_AD15 pad ctrl reg */
+	u32	io_control_emb_ad14;		/* EMB_AD14 pad ctrl reg */
+	u32	io_control_emb_ad13;		/* EMB_AD13 pad ctrl reg */
+	u32	io_control_emb_ad12;		/* EMB_AD12 pad ctrl reg */
+	u32	io_control_emb_ad11;		/* EMB_AD11 pad ctrl reg */
+	u32	io_control_emb_ad10;		/* EMB_AD10 pad ctrl reg */
+	u32	io_control_emb_ad09;		/* EMB_AD09 pad ctrl reg */
+	u32	io_control_emb_ad08;		/* EMB_AD08 pad ctrl reg */
+	u32	io_control_emb_ad07;		/* EMB_AD07 pad ctrl reg */
+	u32	io_control_emb_ad06;		/* EMB_AD06 pad ctrl reg */
+	u32	io_control_emb_ad05;		/* EMB_AD05 pad ctrl reg */
+	u32	io_control_emb_ad04;		/* EMB_AD04 pad ctrl reg */
+	u32	io_control_emb_ad03;		/* EMB_AD03 pad ctrl reg */
+	u32	io_control_emb_ad02;		/* EMB_AD02 pad ctrl reg */
+	u32	io_control_emb_ad01;		/* EMB_AD01 pad ctrl reg */
+	u32	io_control_emb_ad00;		/* EMB_AD00 pad ctrl reg */
+	u32	io_control_pata_ce1;		/* PATA_CE1 pad ctrl reg */
+	u32	io_control_pata_ce2;		/* PATA_CE2 pad ctrl reg */
+	u32	io_control_pata_isolate;	/* PATA_ISOLATE pad ctrl reg */
+	u32	io_control_pata_ior;		/* PATA_IOR pad ctrl reg */
+	u32	io_control_pata_iow;		/* PATA_IOW pad ctrl reg */
+	u32	io_control_pata_iochrdy;	/* PATA_IOCHRDY pad ctrl reg */
+	u32	io_control_pata_intrq;		/* PATA_INTRQ pad ctrl reg */
+	u32	io_control_pata_drq;		/* PATA_DRQ pad ctrl reg */
+	u32	io_control_pata_dack;		/* PATA_DACK pad ctrl reg */
+	u32	io_control_nfc_wp;		/* NFC_WP pad ctrl reg */
+	u32	io_control_nfc_rb;		/* NFC_RB pad ctrl reg */
+	u32	io_control_nfc_ale;		/* NFC_ALE pad ctrl reg */
+	u32	io_control_nfc_cle;		/* NFC_CLE pad ctrl reg */
+	u32	io_control_nfc_we;		/* NFC_WE pad ctrl reg */
+	u32	io_control_nfc_re;		/* NFC_RE pad ctrl reg */
+	u32	io_control_pci_ad31;		/* PCI_AD31 pad ctrl reg */
+	u32	io_control_pci_ad30;		/* PCI_AD30 pad ctrl reg */
+	u32	io_control_pci_ad29;		/* PCI_AD29 pad ctrl reg */
+	u32	io_control_pci_ad28;		/* PCI_AD28 pad ctrl reg */
+	u32	io_control_pci_ad27;		/* PCI_AD27 pad ctrl reg */
+	u32	io_control_pci_ad26;		/* PCI_AD26 pad ctrl reg */
+	u32	io_control_pci_ad25;		/* PCI_AD25 pad ctrl reg */
+	u32	io_control_pci_ad24;		/* PCI_AD24 pad ctrl reg */
+	u32	io_control_pci_ad23;		/* PCI_AD23 pad ctrl reg */
+	u32	io_control_pci_ad22;		/* PCI_AD22 pad ctrl reg */
+	u32	io_control_pci_ad21;		/* PCI_AD21 pad ctrl reg */
+	u32	io_control_pci_ad20;		/* PCI_AD20 pad ctrl reg */
+	u32	io_control_pci_ad19;		/* PCI_AD19 pad ctrl reg */
+	u32	io_control_pci_ad18;		/* PCI_AD18 pad ctrl reg */
+	u32	io_control_pci_ad17;		/* PCI_AD17 pad ctrl reg */
+	u32	io_control_pci_ad16;		/* PCI_AD16 pad ctrl reg */
+	u32	io_control_pci_ad15;		/* PCI_AD15 pad ctrl reg */
+	u32	io_control_pci_ad14;		/* PCI_AD14 pad ctrl reg */
+	u32	io_control_pci_ad13;		/* PCI_AD13 pad ctrl reg */
+	u32	io_control_pci_ad12;		/* PCI_AD12 pad ctrl reg */
+	u32	io_control_pci_ad11;		/* PCI_AD11 pad ctrl reg */
+	u32	io_control_pci_ad10;		/* PCI_AD10 pad ctrl reg */
+	u32	io_control_pci_ad09;		/* PCI_AD09 pad ctrl reg */
+	u32	io_control_pci_ad08;		/* PCI_AD08 pad ctrl reg */
+	u32	io_control_pci_ad07;		/* PCI_AD07 pad ctrl reg */
+	u32	io_control_pci_ad06;		/* PCI_AD06 pad ctrl reg */
+	u32	io_control_pci_ad05;		/* PCI_AD05 pad ctrl reg */
+	u32	io_control_pci_ad04;		/* PCI_AD04 pad ctrl reg */
+	u32	io_control_pci_ad03;		/* PCI_AD03 pad ctrl reg */
+	u32	io_control_pci_ad02;		/* PCI_AD02 pad ctrl reg */
+	u32	io_control_pci_ad01;		/* PCI_AD01 pad ctrl reg */
+	u32	io_control_pci_ad00;		/* PCI_AD00 pad ctrl reg */
+	u32	io_control_pci_cbe0;		/* PCI_CBE0 pad ctrl reg */
+	u32	io_control_pci_cbe1;		/* PCI_CBE1 pad ctrl reg */
+	u32	io_control_pci_cbe2;		/* PCI_CBE2 pad ctrl reg */
+	u32	io_control_pci_cbe3;		/* PCI_CBE3 pad ctrl reg */
+	u32	io_control_pci_grant2;		/* PCI_GRANT2 pad ctrl reg */
+	u32	io_control_pci_req2;		/* PCI_REQ2 pad ctrl reg */
+	u32	io_control_pci_grant1;		/* PCI_GRANT1 pad ctrl reg */
+	u32	io_control_pci_req1;		/* PCI_REQ1 pad ctrl reg */
+	u32	io_control_pci_grant0;		/* PCI_GRANT0 pad ctrl reg */
+	u32	io_control_pci_req0;		/* PCI_REQ0 pad ctrl reg */
+	u32	io_control_pci_inta;		/* PCI_INTA pad ctrl reg */
+	u32	io_control_pci_clk;		/* PCI_CLK pad ctrl reg */
+	u32	io_control_pci_rst;		/* PCI_RST- pad ctrl reg */
+	u32	io_control_pci_frame;		/* PCI_FRAME pad ctrl reg */
+	u32	io_control_pci_idsel;		/* PCI_IDSEL pad ctrl reg */
+	u32	io_control_pci_devsel;		/* PCI_DEVSEL pad ctrl reg */
+	u32	io_control_pci_irdy;		/* PCI_IRDY pad ctrl reg */
+	u32	io_control_pci_trdy;		/* PCI_TRDY pad ctrl reg */
+	u32	io_control_pci_stop;		/* PCI_STOP pad ctrl reg */
+	u32	io_control_pci_par;		/* PCI_PAR pad ctrl reg */
+	u32	io_control_pci_perr;		/* PCI_PERR pad ctrl reg */
+	u32	io_control_pci_serr;		/* PCI_SERR pad ctrl reg */
+	u32	io_control_spdif_txclk;		/* SPDIF_TXCLK pad ctrl reg */
+	u32	io_control_spdif_tx;		/* SPDIF_TX pad ctrl reg */
+	u32	io_control_spdif_rx;		/* SPDIF_RX pad ctrl reg */
+	u32	io_control_i2c0_scl;		/* I2C0_SCL pad ctrl reg */
+	u32	io_control_i2c0_sda;		/* I2C0_SDA pad ctrl reg */
+	u32	io_control_i2c1_scl;		/* I2C1_SCL pad ctrl reg */
+	u32	io_control_i2c1_sda;		/* I2C1_SDA pad ctrl reg */
+	u32	io_control_i2c2_scl;		/* I2C2_SCL pad ctrl reg */
+	u32	io_control_i2c2_sda;		/* I2C2_SDA pad ctrl reg */
+	u32	io_control_irq0;		/* IRQ0 pad ctrl reg */
+	u32	io_control_irq1;		/* IRQ1 pad ctrl reg */
+	u32	io_control_can1_tx;		/* CAN1_TX pad ctrl reg */
+	u32	io_control_can2_tx;		/* CAN2_TX pad ctrl reg */
+	u32	io_control_j1850_tx;		/* J1850_TX pad ctrl reg */
+	u32	io_control_j1850_rx;		/* J1850_RX pad ctrl reg */
+	u32	io_control_psc_mclk_in;		/* PSC_MCLK_IN pad ctrl reg */
+	u32	io_control_psc0_0;		/* PSC0_0 pad ctrl reg */
+	u32	io_control_psc0_1;		/* PSC0_1 pad ctrl reg */
+	u32	io_control_psc0_2;		/* PSC0_2 pad ctrl reg */
+	u32	io_control_psc0_3;		/* PSC0_3 pad ctrl reg */
+	u32	io_control_psc0_4;		/* PSC0_4 pad ctrl reg */
+	u32	io_control_psc1_0;		/* PSC1_0 pad ctrl reg */
+	u32	io_control_psc1_1;		/* PSC1_1 pad ctrl reg */
+	u32	io_control_psc1_2;		/* PSC1_2 pad ctrl reg */
+	u32	io_control_psc1_3;		/* PSC1_3 pad ctrl reg */
+	u32	io_control_psc1_4;		/* PSC1_4 pad ctrl reg */
+	u32	io_control_psc2_0;		/* PSC2_0 pad ctrl reg */
+	u32	io_control_psc2_1;		/* PSC2_1 pad ctrl reg */
+	u32	io_control_psc2_2;		/* PSC2_2 pad ctrl reg */
+	u32	io_control_psc2_3;		/* PSC2_3 pad ctrl reg */
+	u32	io_control_psc2_4;		/* PSC2_4 pad ctrl reg */
+	u32	io_control_psc3_0;		/* PSC3_0 pad ctrl reg */
+	u32	io_control_psc3_1;		/* PSC3_1 pad ctrl reg */
+	u32	io_control_psc3_2;		/* PSC3_2 pad ctrl reg */
+	u32	io_control_psc3_3;		/* PSC3_3 pad ctrl reg */
+	u32	io_control_psc3_4;		/* PSC3_4 pad ctrl reg */
+	u32	io_control_psc4_0;		/* PSC4_0 pad ctrl reg */
+	u32	io_control_psc4_1;		/* PSC4_1 pad ctrl reg */
+	u32	io_control_psc4_2;		/* PSC4_2 pad ctrl reg */
+	u32	io_control_psc4_3;		/* PSC4_3 pad ctrl reg */
+	u32	io_control_psc4_4;		/* PSC4_4 pad ctrl reg */
+	u32	io_control_psc5_0;		/* PSC5_0 pad ctrl reg */
+	u32	io_control_psc5_1;		/* PSC5_1 pad ctrl reg */
+	u32	io_control_psc5_2;		/* PSC5_2 pad ctrl reg */
+	u32	io_control_psc5_3;		/* PSC5_3 pad ctrl reg */
+	u32	io_control_psc5_4;		/* PSC5_4 pad ctrl reg */
+	u32	io_control_psc6_0;		/* PSC6_0 pad ctrl reg */
+	u32	io_control_psc6_1;		/* PSC6_1 pad ctrl reg */
+	u32	io_control_psc6_2;		/* PSC6_2 pad ctrl reg */
+	u32	io_control_psc6_3;		/* PSC6_3 pad ctrl reg */
+	u32	io_control_psc6_4;		/* PSC6_4 pad ctrl reg */
+	u32	io_control_psc7_0;		/* PSC7_0 pad ctrl reg */
+	u32	io_control_psc7_1;		/* PSC7_1 pad ctrl reg */
+	u32	io_control_psc7_2;		/* PSC7_2 pad ctrl reg */
+	u32	io_control_psc7_3;		/* PSC7_3 pad ctrl reg */
+	u32	io_control_psc7_4;		/* PSC7_4 pad ctrl reg */
+	u32	io_control_psc8_0;		/* PSC8_0 pad ctrl reg */
+	u32	io_control_psc8_1;		/* PSC8_1 pad ctrl reg */
+	u32	io_control_psc8_2;		/* PSC8_2 pad ctrl reg */
+	u32	io_control_psc8_3;		/* PSC8_3 pad ctrl reg */
+	u32	io_control_psc8_4;		/* PSC8_4 pad ctrl reg */
+	u32	io_control_psc9_0;		/* PSC9_0 pad ctrl reg */
+	u32	io_control_psc9_1;		/* PSC9_1 pad ctrl reg */
+	u32	io_control_psc9_2;		/* PSC9_2 pad ctrl reg */
+	u32	io_control_psc9_3;		/* PSC9_3 pad ctrl reg */
+	u32	io_control_psc9_4;		/* PSC9_4 pad ctrl reg */
+	u32	io_control_psc10_0;		/* PSC10_0 pad ctrl reg */
+	u32	io_control_psc10_1;		/* PSC10_1 pad ctrl reg */
+	u32	io_control_psc10_2;		/* PSC10_2 pad ctrl reg */
+	u32	io_control_psc10_3;		/* PSC10_3 pad ctrl reg */
+	u32	io_control_psc10_4;		/* PSC10_4 pad ctrl reg */
+	u32	io_control_psc11_0;		/* PSC11_0 pad ctrl reg */
+	u32	io_control_psc11_1;		/* PSC11_1 pad ctrl reg */
+	u32	io_control_psc11_2;		/* PSC11_2 pad ctrl reg */
+	u32	io_control_psc11_3;		/* PSC11_3 pad ctrl reg */
+	u32	io_control_psc11_4;		/* PSC11_4 pad ctrl reg */
+	u32	io_control_ckstp_out;		/* CKSTP_OUT pad ctrl reg */
+	u32	io_control_usb_phy_drvvbus;	/* USB2_DRVVBUS pad ctrl reg */
+	u8	reserved[0x0cfc];		/* fill to 4096 bytes size */
+} ioctrl512x_t;
+
+/* IO pin fields */
+#define IO_PIN_FMUX(v)	((v) << 7)	/* pin function */
+#define IO_PIN_HOLD(v)	((v) << 5)	/* hold time, pci only */
+#define IO_PIN_PUD(v)	((v) << 4)	/* if PUE, 0=pull-down, 1=pull-up */
+#define IO_PIN_PUE(v)	((v) << 3)	/* pull up/down enable */
+#define IO_PIN_ST(v)	((v) << 2)	/* schmitt trigger */
+#define IO_PIN_DS(v)	((v))		/* slew rate */
+
+typedef struct iopin_t {
+	int p_offset;		/* offset from IOCTL_MEM_OFFSET */
+	int nr_pins;		/* number of pins to set this way */
+	int bit_or;		/* or in the value instead of overwrite */
+	u_long val;		/* value to write or or */
+}iopin_t;
+
+void iopin_initialize(iopin_t *,int);
+
+/*
+ * support to adjust individual parts of the IO pin setup
+ */
+
+#define IO_PIN_OVER_EACH	(1 << 0) /* for compatibility */
+#define IO_PIN_OVER_FMUX	(1 << 1)
+#define IO_PIN_OVER_HOLD	(1 << 2)
+#define IO_PIN_OVER_PULL	(1 << 3)
+#define IO_PIN_OVER_STRIG	(1 << 4)
+#define IO_PIN_OVER_DRVSTR	(1 << 5)
+
+void iopin_initialize_bits(iopin_t *, int);
+
+/*
+ * IIM
+ */
+typedef struct iim512x {
+	u32 stat;		/* IIM status register */
+	u32 statm;		/* IIM status IRQ mask */
+	u32 err;		/* IIM errors register */
+	u32 emask;		/* IIM error IRQ mask  */
+	u32 fctl;		/* IIM fuse control register */
+	u32 ua;			/* IIM upper address register */
+	u32 la;			/* IIM lower address register */
+	u32 sdat;		/* IIM explicit sense data */
+	u8 res0[0x08];
+	u32 prg_p;		/* IIM program protection register */
+	u8 res1[0x10];
+	u32 divide;		/* IIM divide factor register */
+	u8 res2[0x7c0];
+	u32 fbac0;		/* IIM fuse bank 0 prot (for Freescale use) */
+	u32 fb0w0[0x1f];	/* IIM fuse bank 0 data (for Freescale use) */
+	u8 res3[0x380];
+	u32 fbac1;		/* IIM fuse bank 1 protection */
+	u32 fb1w1[0x01f];	/* IIM fuse bank 1 data */
+	u8 res4[0x380];
+} iim512x_t;
+
+/*
+ * LPC
+ */
+typedef struct lpc512x {
+	u32	cs_cfg[8];	/* Chip Select N Configuration Registers
+				   No dedicated entry for CS Boot as == CS0 */
+	u32	cs_cr;		/* Chip Select Control Register */
+	u32	cs_sr;		/* Chip Select Status Register */
+	u32	cs_bcr;		/* Chip Select Burst Control Register */
+	u32	cs_dccr;	/* Chip Select Deadcycle Control Register */
+	u32	cs_hccr;	/* Chip Select Holdcycle Control Register */
+	u32	altr;		/* Address Latch Timing Register */
+	u8	res0[0xc8];
+	u32	sclpc_psr;	/* SCLPC Packet Size Register */
+	u32	sclpc_sar;	/* SCLPC Start Address Register */
+	u32	sclpc_cr;	/* SCLPC Control Register */
+	u32	sclpc_er;	/* SCLPC Enable Register */
+	u32	sclpc_nar;	/* SCLPC NextAddress Register */
+	u32	sclpc_sr;	/* SCLPC Status Register */
+	u32	sclpc_bdr;	/* SCLPC Bytes Done Register */
+	u32	emb_scr;	/* EMB Share Counter Register */
+	u32	emb_pcr;	/* EMB Pause Control Register */
+	u8	res1[0x1c];
+	u32	lpc_fdwr;	/* LPC RX/TX FIFO Data Word Register */
+	u32	lpc_fsr;	/* LPC RX/TX FIFO Status Register */
+	u32	lpc_cr;		/* LPC RX/TX FIFO Control Register */
+	u32	lpc_ar;		/* LPC RX/TX FIFO Alarm Register */
+	u8	res2[0xb0];
+} lpc512x_t;
+
+/*
+ * PATA
+ */
+typedef struct pata512x {
+	/* LOCAL Registers */
+	u32 pata_time1;		/* Time register 1: PIO and tx timing parameter */
+	u32 pata_time2;		/* Time register 2: PIO timing parameter */
+	u32 pata_time3;		/* Time register 3: PIO and MDMA timing parameter */
+	u32 pata_time4;		/* Time register 4: MDMA and UDMA timing parameter */
+	u32 pata_time5;		/* Time register 5: UDMA timing parameter */
+	u32 pata_time6;		/* Time register 6: UDMA timing parameter */
+	u32 pata_fifo_data32;   /* 32bit wide dataport to/from FIFO */
+	u32 pata_fifo_data16;   /* 16bit wide dataport to/from FIFO */
+	u32 pata_fifo_fill;	/* FIFO filling in halfwords (READONLY)*/
+	u32 pata_ata_control;   /* ATA Interface control register */
+	u32 pata_irq_pending;   /* Interrupt pending register (READONLY) */
+	u32 pata_irq_enable;	/* Interrupt enable register */
+	u32 pata_irq_clear;	/* Interrupt clear register (WRITEONLY)*/
+	u32 pata_fifo_alarm;	/* fifo alarm threshold */
+	u32 res1[0x1A];
+	/* DRIVE Registers */
+	u32 pata_drive_data;	/* drive data register*/
+	u32 pata_drive_features;/* drive features register */
+	u32 pata_drive_sectcnt; /* drive sector count register */
+	u32 pata_drive_sectnum; /* drive sector number register */
+	u32 pata_drive_cyllow;  /* drive cylinder low register */
+	u32 pata_drive_cylhigh; /* drive cylinder high register */
+	u32 pata_drive_dev_head;/* drive device head register */
+	u32 pata_drive_command; /* write = drive command, read = drive status reg */
+	u32 res2[0x06];
+	u32 pata_drive_alt_stat;/* write = drive control, read = drive alt status reg */
+	u32 res3[0x09];
+} pata512x_t;
+
+/*
+ * PSC
+ */
+typedef struct psc512x {
+	volatile u8	mode;		/* PSC + 0x00 */
+	volatile u8	res0[3];
+	union {				/* PSC + 0x04 */
+		volatile u16	status;
+		volatile u16	clock_select;
+	} sr_csr;
+#define psc_status	sr_csr.status
+#define psc_clock_select sr_csr.clock_select
+	volatile u16	res1;
+	volatile u8	command;	/* PSC + 0x08 */
+	volatile u8	res2[3];
+	union {				/* PSC + 0x0c */
+		volatile u8	buffer_8;
+		volatile u16	buffer_16;
+		volatile u32	buffer_32;
+	} buffer;
+#define psc_buffer_8	buffer.buffer_8
+#define psc_buffer_16	buffer.buffer_16
+#define psc_buffer_32	buffer.buffer_32
+	union {				/* PSC + 0x10 */
+		volatile u8	ipcr;
+		volatile u8	acr;
+	} ipcr_acr;
+#define psc_ipcr	ipcr_acr.ipcr
+#define psc_acr		ipcr_acr.acr
+	volatile u8	res3[3];
+	union {				/* PSC + 0x14 */
+		volatile u16	isr;
+		volatile u16	imr;
+	} isr_imr;
+#define psc_isr		isr_imr.isr
+#define psc_imr		isr_imr.imr
+	volatile u16	res4;
+	volatile u8	ctur;		/* PSC + 0x18 */
+	volatile u8	res5[3];
+	volatile u8	ctlr;		/* PSC + 0x1c */
+	volatile u8	res6[3];
+	volatile u32	ccr;		/* PSC + 0x20 */
+	volatile u8	res7[12];
+	volatile u8	ivr;		/* PSC + 0x30 */
+	volatile u8	res8[3];
+	volatile u8	ip;		/* PSC + 0x34 */
+	volatile u8	res9[3];
+	volatile u8	op1;		/* PSC + 0x38 */
+	volatile u8	res10[3];
+	volatile u8	op0;		/* PSC + 0x3c */
+	volatile u8	res11[3];
+	volatile u32	sicr;		/* PSC + 0x40 */
+	volatile u8	res12[60];
+	volatile u32	tfcmd;		/* PSC + 0x80 */
+	volatile u32	tfalarm;	/* PSC + 0x84 */
+	volatile u32	tfstat;		/* PSC + 0x88 */
+	volatile u32	tfintstat;	/* PSC + 0x8C */
+	volatile u32	tfintmask;	/* PSC + 0x90 */
+	volatile u32	tfcount;	/* PSC + 0x94 */
+	volatile u16	tfwptr;		/* PSC + 0x98 */
+	volatile u16	tfrptr;		/* PSC + 0x9A */
+	volatile u32	tfsize;		/* PSC + 0x9C */
+	volatile u8	res13[28];
+	union {				/* PSC + 0xBC */
+		volatile u8	buffer_8;
+		volatile u16	buffer_16;
+		volatile u32	buffer_32;
+	} tfdata_buffer;
+#define tfdata_8	tfdata_buffer.buffer_8
+#define tfdata_16	tfdata_buffer.buffer_16
+#define tfdata_32	tfdata_buffer.buffer_32
+
+	volatile u32	rfcmd;		/* PSC + 0xC0 */
+	volatile u32	rfalarm;	/* PSC + 0xC4 */
+	volatile u32	rfstat;		/* PSC + 0xC8 */
+	volatile u32	rfintstat;	/* PSC + 0xCC */
+	volatile u32	rfintmask;	/* PSC + 0xD0 */
+	volatile u32	rfcount;	/* PSC + 0xD4 */
+	volatile u16	rfwptr;		/* PSC + 0xD8 */
+	volatile u16	rfrptr;		/* PSC + 0xDA */
+	volatile u32	rfsize;		/* PSC + 0xDC */
+	volatile u8	res18[28];
+	union {				/* PSC + 0xFC */
+		volatile u8	buffer_8;
+		volatile u16	buffer_16;
+		volatile u32	buffer_32;
+	} rfdata_buffer;
+#define rfdata_8	rfdata_buffer.buffer_8
+#define rfdata_16	rfdata_buffer.buffer_16
+#define rfdata_32	rfdata_buffer.buffer_32
+} psc512x_t;
+
+/* PSC FIFO Command values */
+#define PSC_FIFO_RESET_SLICE		0x80
+#define PSC_FIFO_ENABLE_SLICE		0x01
+
+/* PSC FIFO Controller Command values */
+#define FIFOC_ENABLE_CLOCK_GATE		0x01
+#define FIFOC_DISABLE_CLOCK_GATE	0x00
+
+/* PSC FIFO status */
+#define PSC_FIFO_EMPTY			0x01
+
+/* PSC Command values */
+#define PSC_RX_ENABLE		0x01
+#define PSC_RX_DISABLE		0x02
+#define PSC_TX_ENABLE		0x04
+#define PSC_TX_DISABLE		0x08
+#define PSC_SEL_MODE_REG_1	0x10
+#define PSC_RST_RX		0x20
+#define PSC_RST_TX		0x30
+#define PSC_RST_ERR_STAT	0x40
+#define PSC_RST_BRK_CHG_INT	0x50
+#define PSC_START_BRK		0x60
+#define PSC_STOP_BRK		0x70
+
+/* PSC status register bits */
+#define PSC_SR_CDE		0x0080
+#define PSC_SR_TXEMP		0x0800
+#define PSC_SR_OE		0x1000
+#define PSC_SR_PE		0x2000
+#define PSC_SR_FE		0x4000
+#define PSC_SR_RB		0x8000
+
+/* PSC mode fields */
+#define PSC_MODE_5_BITS		0x00
+#define PSC_MODE_6_BITS		0x01
+#define PSC_MODE_7_BITS		0x02
+#define PSC_MODE_8_BITS		0x03
+#define PSC_MODE_PAREVEN	0x00
+#define PSC_MODE_PARODD		0x04
+#define PSC_MODE_PARFORCE	0x08
+#define PSC_MODE_PARNONE	0x10
+#define PSC_MODE_ENTIMEOUT	0x20
+#define PSC_MODE_RXRTS		0x80
+#define PSC_MODE_1_STOPBIT	0x07
+
+/*
+ * FIFOC
+ */
+typedef struct fifoc512x {
+	u32 fifoc_cmd;
+	u32 fifoc_int;
+	u32 fifoc_dma;
+	u32 fifoc_axe;
+	u32 fifoc_debug;
+	u8 fixme[0xEC];
+} fifoc512x_t;
+
+/*
+ * Centralized FIFO Controller has internal memory for all 12 PSCs FIFOs
+ *
+ * NOTE: individual PSC units are free to use whatever area (and size) of the
+ * FIFOC internal memory, so make sure memory areas for FIFO slices used by
+ * different PSCs do not overlap!
+ *
+ * Overall size of FIFOC memory is not documented in the MPC5121e RM, but
+ * tests indicate that it is 1024 words total.
+ *
+ * *_TX_SIZE and *_RX_SIZE is the number of 4-byte words for FIFO slice.
+ */
+#define FIFOC_PSC0_TX_SIZE	0x04
+#define FIFOC_PSC0_TX_ADDR	0x0
+#define FIFOC_PSC0_RX_SIZE	0x04
+#define FIFOC_PSC0_RX_ADDR	0x10
+
+#define FIFOC_PSC1_TX_SIZE	0x04
+#define FIFOC_PSC1_TX_ADDR	0x20
+#define FIFOC_PSC1_RX_SIZE	0x04
+#define FIFOC_PSC1_RX_ADDR	0x30
+
+#define FIFOC_PSC2_TX_SIZE	0x04
+#define FIFOC_PSC2_TX_ADDR	0x40
+#define FIFOC_PSC2_RX_SIZE	0x04
+#define FIFOC_PSC2_RX_ADDR	0x50
+
+#define FIFOC_PSC3_TX_SIZE	0x04
+#define FIFOC_PSC3_TX_ADDR	0x60
+#define FIFOC_PSC3_RX_SIZE	0x04
+#define FIFOC_PSC3_RX_ADDR	0x70
+
+#define FIFOC_PSC4_TX_SIZE	0x04
+#define FIFOC_PSC4_TX_ADDR	0x80
+#define FIFOC_PSC4_RX_SIZE	0x04
+#define FIFOC_PSC4_RX_ADDR	0x90
+
+#define FIFOC_PSC5_TX_SIZE	0x04
+#define FIFOC_PSC5_TX_ADDR	0xa0
+#define FIFOC_PSC5_RX_SIZE	0x04
+#define FIFOC_PSC5_RX_ADDR	0xb0
+
+#define FIFOC_PSC6_TX_SIZE	0x04
+#define FIFOC_PSC6_TX_ADDR	0xc0
+#define FIFOC_PSC6_RX_SIZE	0x04
+#define FIFOC_PSC6_RX_ADDR	0xd0
+
+#define FIFOC_PSC7_TX_SIZE	0x04
+#define FIFOC_PSC7_TX_ADDR	0xe0
+#define FIFOC_PSC7_RX_SIZE	0x04
+#define FIFOC_PSC7_RX_ADDR	0xf0
+
+#define FIFOC_PSC8_TX_SIZE	0x04
+#define FIFOC_PSC8_TX_ADDR	0x100
+#define FIFOC_PSC8_RX_SIZE	0x04
+#define FIFOC_PSC8_RX_ADDR	0x110
+
+#define FIFOC_PSC9_TX_SIZE	0x04
+#define FIFOC_PSC9_TX_ADDR	0x120
+#define FIFOC_PSC9_RX_SIZE	0x04
+#define FIFOC_PSC9_RX_ADDR	0x130
+
+#define FIFOC_PSC10_TX_SIZE	0x04
+#define FIFOC_PSC10_TX_ADDR	0x140
+#define FIFOC_PSC10_RX_SIZE	0x04
+#define FIFOC_PSC10_RX_ADDR	0x150
+
+#define FIFOC_PSC11_TX_SIZE	0x04
+#define FIFOC_PSC11_TX_ADDR	0x160
+#define FIFOC_PSC11_RX_SIZE	0x04
+#define FIFOC_PSC11_RX_ADDR	0x170
+
+/*
+ * SATA
+ */
+typedef struct sata512x {
+	u8 fixme[0x2000];
+} sata512x_t;
+
+typedef struct immap {
+	sysconf512x_t		sysconf;	/* System configuration */
+	u8			res0[0x700];
+	wdt512x_t		wdt;		/* Watch Dog Timer (WDT) */
+	rtclk512x_t		rtc;		/* Real Time Clock Module */
+	gpt512x_t		gpt;		/* General Purpose Timer */
+	ipic512x_t		ipic;		/* Integrated Programmable Interrupt Controller */
+	arbiter512x_t		arbiter;	/* CSB Arbiter */
+	reset512x_t		reset;		/* Reset Module */
+	clk512x_t		clk;		/* Clock Module */
+	pmc512x_t		pmc;		/* Power Management Control Module */
+	gpio512x_t		gpio;		/* General purpose I/O module */
+	u8			res1[0x100];
+	mscan512x_t		mscan;		/* MSCAN */
+	bdlc512x_t		bdlc;		/* BDLC */
+	sdhc512x_t		sdhc;		/* SDHC */
+	spdif512x_t		spdif;		/* SPDIF */
+	i2c512x_t		i2c;		/* I2C Controllers */
+	u8			res2[0x800];
+	axe512x_t		axe;		/* AXE */
+	diu512x_t		diu;		/* Display Interface Unit */
+	cfm512x_t		cfm;		/* Clock Frequency Measurement */
+	u8			res3[0x500];
+	fec512x_t		fec;		/* Fast Ethernet Controller */
+	ulpi512x_t		ulpi;		/* USB ULPI */
+	u8			res4[0xa00];
+	utmi512x_t		utmi;		/* USB UTMI */
+	u8			res5[0x1000];
+	pcidma512x_t		pci_dma;	/* PCI DMA */
+	pciconf512x_t		pci_conf;	/* PCI Configuration */
+	u8			res6[0x80];
+	ios512x_t		ios;		/* PCI Sequencer */
+	pcictrl512x_t		pci_ctrl;	/* PCI Controller Control and Status */
+	u8			res7[0xa00];
+	ddr512x_t		mddrc;		/* Multi-port DDR Memory Controller */
+	ioctrl512x_t		io_ctrl;	/* IO Control */
+	iim512x_t		iim;		/* IC Identification module */
+	u8			res8[0x4000];
+	lpc512x_t		lpc;		/* LocalPlus Controller */
+	pata512x_t		pata;		/* Parallel ATA */
+	u8			res9[0xd00];
+	psc512x_t		psc[12];	/* PSCs */
+	u8			res10[0x300];
+	fifoc512x_t		fifoc;		/* FIFO Controller */
+	u8			res11[0x2000];
+	dma512x_t		dma;		/* DMA */
+	u8			res12[0xa800];
+	sata512x_t		sata;		/* Serial ATA */
+	u8			res13[0xde000];
+} immap_t;
+
+/* provide interface to get PATA base address */
+static inline u32 get_pata_base (void)
+{
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+	return (u32)(&im->pata);
+}
+#endif	/* __ASSEMBLY__ */
+
+#define CONFIG_SYS_MPC512x_USB1_OFFSET   0x4000
+#define CONFIG_SYS_MPC512x_USB1_ADDR \
+			(CONFIG_SYS_IMMR + CONFIG_SYS_MPC512x_USB1_OFFSET)
+
+#define IIM_BASE_ADDR	(CONFIG_SYS_IMMR + offsetof(immap_t, iim))
+
+#endif /* __IMMAP_512x__ */
diff --git a/arch/powerpc/include/asm/mpc512x.h b/arch/powerpc/include/asm/mpc512x.h
new file mode 100644
index 0000000000..9167a57544
--- /dev/null
+++ b/arch/powerpc/include/asm/mpc512x.h
@@ -0,0 +1,42 @@ 
+/*
+ * include/asm-ppc/mpc512x.h
+ *
+ * Prototypes, etc. for the Freescale MPC512x embedded cpu chips
+ *
+ * 2009 (C) Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef __ASMPPC_MPC512X_H
+#define __ASMPPC_MPC512X_H
+
+/*
+ * macros for manipulating CSx_START/STOP
+ */
+#define CSAW_START(start)	((start) & 0xFFFF0000)
+#define CSAW_STOP(start, size)	(((start) + (size) - 1) >> 16)
+
+/*
+ * Inlines
+ */
+
+/*
+ * According to MPC5121e RM, configuring local access windows should
+ * be followed by a dummy read of the config register that was
+ * modified last and an isync.
+ */
+static inline void sync_law(volatile void *addr)
+{
+	in_be32(addr);
+	__asm__ __volatile__ ("isync");
+}
+
+/*
+ * Prototypes
+ */
+extern long int fixed_sdram(ddr512x_config_t *mddrc_config,
+				u32 *dram_init_seq, int seq_sz);
+extern int mpc5121_diu_init(void);
+extern void ide_set_reset(int idereset);
+
+#endif /* __ASMPPC_MPC512X_H */
diff --git a/arch/powerpc/include/asm/ppc.h b/arch/powerpc/include/asm/ppc.h
index 4d9af6c37c..f5e9334cc7 100644
--- a/arch/powerpc/include/asm/ppc.h
+++ b/arch/powerpc/include/asm/ppc.h
@@ -13,6 +13,11 @@ 
 
 #ifndef __ASSEMBLY__
 
+#if defined(CONFIG_MPC5xxx)
+#include <mpc5xxx.h>
+#elif defined(CONFIG_MPC512X)
+#include <asm/immap_512x.h>
+#endif
 #ifdef CONFIG_MPC86xx
 #include <mpc86xx.h>
 #include <asm/immap_86xx.h>
@@ -38,6 +43,9 @@ 
 #include <asm/arch/immap_lsch2.h>
 #endif
 
+#if defined(CONFIG_MPC5xxx)
+uint get_svr(void);
+#endif
 uint get_pvr(void);
 uint get_svr(void);
 uint rd_ic_cst(void);
@@ -48,6 +56,7 @@  void wr_dc_cst(uint);
 void wr_dc_adr(uint);
 
 #if defined(CONFIG_4xx)	|| \
+	defined(CONFIG_MPC5xxx)	|| \
 	defined(CONFIG_MPC85xx)	|| \
 	defined(CONFIG_MPC86xx)	|| \
 	defined(CONFIG_MPC83xx)
@@ -76,6 +85,10 @@  void ddr_enable_ecc(unsigned int dram_size);
 #endif
 #endif
 
+#if defined(CONFIG_MPC5xxx)
+int	prt_mpc5xxx_clks(void);
+#endif
+
 #if defined(CONFIG_MPC85xx)
 typedef MPC85xx_SYS_INFO sys_info_t;
 void get_sys_info(sys_info_t *);
diff --git a/arch/powerpc/lib/Makefile b/arch/powerpc/lib/Makefile
index 4e47e83930..4dd6b56c14 100644
--- a/arch/powerpc/lib/Makefile
+++ b/arch/powerpc/lib/Makefile
@@ -37,6 +37,24 @@  obj-y	+= interrupts.o
 obj-$(CONFIG_CMD_KGDB) += kgdb.o
 obj-y	+= stack.o
 obj-y	+= time.o
+
+# Don't include the MPC5xxx special memcpy into the
+# SPL U-Boot image. memcpy is used in the SPL NOR
+# flash driver. And we need the real, fast memcpy
+# here. We have no problems with unaligned access.
+ifndef CONFIG_SPL_BUILD
+# Workaround for local bus unaligned access problems
+# on MPC512x and MPC5200
+ifdef CONFIG_MPC512X
+AFLAGS_ppcstring.o += -Dmemcpy=__memcpy
+obj-y += memcpy_mpc5200.o
+endif
+ifdef CONFIG_MPC5200
+AFLAGS_ppcstring.o += -Dmemcpy=__memcpy
+obj-y += memcpy_mpc5200.o
+endif
+endif
+
 endif # not minimal
 
 ifdef CONFIG_SPL_BUILD
diff --git a/arch/powerpc/lib/bootm.c b/arch/powerpc/lib/bootm.c
index 42a6afbc31..17c5ed173c 100644
--- a/arch/powerpc/lib/bootm.c
+++ b/arch/powerpc/lib/bootm.c
@@ -283,6 +283,10 @@  static void set_clocks_in_mhz (bd_t *kbd)
 		kbd->bi_sccfreq /= 1000000L;
 		kbd->bi_vco	/= 1000000L;
 #endif
+#if defined(CONFIG_MPC5xxx)
+		kbd->bi_ipbfreq /= 1000000L;
+		kbd->bi_pcifreq /= 1000000L;
+#endif /* CONFIG_MPC5xxx */
 	}
 }
 
diff --git a/arch/powerpc/lib/memcpy_mpc5200.c b/arch/powerpc/lib/memcpy_mpc5200.c
new file mode 100644
index 0000000000..7e5a005789
--- /dev/null
+++ b/arch/powerpc/lib/memcpy_mpc5200.c
@@ -0,0 +1,55 @@ 
+/*
+ * (C) Copyright 2010
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * This is a workaround for issues on the MPC5200, where unaligned
+ * 32-bit-accesses to the local bus will deliver corrupted data. This
+ * happens for example when trying to use memcpy() from an odd NOR
+ * flash address; the behaviour can be also seen when using "md" on an
+ * odd NOR flash address (but there it is not a bug in U-Boot, which
+ * only shows the behaviour of this processor).
+ *
+ * For memcpy(), we test if either the source or the target address
+ * are not 32 bit aligned, and - if so - if the source address is in
+ * NOR flash: in this case we perform a byte-wise (slow) then; for
+ * aligned operations of non-flash areas we use the optimized (fast)
+ * real __memcpy().  This way we minimize the performance impact of
+ * this workaround.
+ *
+ */
+
+#include <common.h>
+#include <flash.h>
+#include <linux/types.h>
+
+void *memcpy(void *trg, const void *src, size_t len)
+{
+	extern void* __memcpy(void *, const void *, size_t);
+	char *s = (char *)src;
+	char *t = (char *)trg;
+	void *dest = (void *)trg;
+
+	/*
+	 * Check is source address is in flash:
+	 * If not, we use the fast assembler code
+	 */
+	if (((((unsigned long)s & 3) == 0)	/* source aligned  */
+		&&				/*	AND	   */
+	     (((unsigned long)t & 3) == 0))	/* target aligned, */
+		||				/*	or	   */
+	    (addr2info((ulong)s) == NULL)) {	/* source not in flash */
+		return __memcpy(trg, src, len);
+	}
+
+	/*
+	 * Copying from flash, perform byte by byte copy.
+	 */
+	while (len-- > 0)
+		*t++ = *s++;
+
+	return dest;
+}
diff --git a/board/a3m071/Kconfig b/board/a3m071/Kconfig
new file mode 100644
index 0000000000..444c450d8a
--- /dev/null
+++ b/board/a3m071/Kconfig
@@ -0,0 +1,9 @@ 
+if TARGET_A3M071
+
+config SYS_BOARD
+	default "a3m071"
+
+config SYS_CONFIG_NAME
+	default "a3m071"
+
+endif
diff --git a/board/a3m071/MAINTAINERS b/board/a3m071/MAINTAINERS
new file mode 100644
index 0000000000..975107d2c0
--- /dev/null
+++ b/board/a3m071/MAINTAINERS
@@ -0,0 +1,7 @@ 
+A3M071 BOARD
+M:	Stefan Roese <sr@denx.de>
+S:	Maintained
+F:	board/a3m071/
+F:	include/configs/a3m071.h
+F:	configs/a3m071_defconfig
+F:	configs/a4m2k_defconfig
diff --git a/board/a3m071/Makefile b/board/a3m071/Makefile
new file mode 100644
index 0000000000..4e31e33936
--- /dev/null
+++ b/board/a3m071/Makefile
@@ -0,0 +1,5 @@ 
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	:= a3m071.o
diff --git a/board/a3m071/README b/board/a3m071/README
new file mode 100644
index 0000000000..112c47b60d
--- /dev/null
+++ b/board/a3m071/README
@@ -0,0 +1,80 @@ 
+------------------------------------------------------------------------
+A3M071 board support
+------------------------------------------------------------------------
+
+
+SPL NOR flash support:
+----------------------
+To boot fast into the OS (Linux), this board port integrates the SPL
+framework. This means, that a special, stripped-down version of
+U-Boot runs in the beginning. In the case of the A3M071 board, this
+SPL U-Boot version is less than 16 KiB big. This SPL U-Boot can either
+boot the OS (Linux) or a "real", full-blown U-Boot. This detection
+on whether to boot Linux or U-Boot is done by using the "boot_os"
+environment variable. If "boot_os" is set to "yes", Linux will be
+loaded and booted from the SPL U-Boot version. Otherwise, the
+full-blown U-Boot version will be loaded and run.
+
+Enabling Linux booting:
+-----------------------
+From U-Boot:
+=> setenv boot_os yes
+=> saveenv
+
+From Linux:
+$ fw_setenv boot_os yes
+
+Enabling U-Boot booting:
+------------------------
+From U-Boot:
+=> setenv boot_os no
+=> saveenv
+
+From Linux:
+$ fw_setenv boot_os no
+
+
+Preparing Linux image(s) for booting from SPL U-Boot:
+-----------------------------------------------------
+To boot the Linux kernel from the SPL, the DT blob (fdt) needs to get
+prepard/patched first. U-Boot usually inserts some dynamic values into
+the DT binary (blob), e.g. autodetected memory size, MAC addresses,
+clocks speeds etc. To generate this patched DT blob, you can use
+the following command:
+
+1. Load fdt blob to SDRAM:
+=> tftp 1800000 a3m071/a3m071.dtb
+
+2. Set bootargs as desired for Linux booting (e.g. flash_mtd):
+=> run mtdargs addip2 addtty
+
+3. Use "fdt" commands to patch the DT blob:
+=> fdt addr 1800000
+=> fdt boardsetup
+=> fdt chosen
+
+4. Display patched DT blob (optional):
+=> fdt print
+
+5. Save fdt to NOR flash:
+=> erase fc180000 fc07ffff
+=> cp.b 1800000 fc180000 10000
+
+All this can be integrated into an environment command:
+=> setenv upd_fdt 'tftp 1800000 a3m071/a3m071.dtb;run mtdargs addip addtty; \
+	fdt addr 1800000;fdt boardsetup;fdt chosen;erase fc180000 fc07ffff; \
+	cp.b 1800000 fc180000 10000'
+=> saveenv
+
+After this, only "run upd_fdt" needs to get called to load, patch
+and save the DT blob into NOR flash.
+
+Additionally, the Linux kernel image has to be saved uncompressed in
+its uImage file (and not gzip compressed). This can be done with this
+command:
+
+$ mkimage -A ppc -O linux -T kernel -C none -a 0 -e 0 \
+	-n "Linux Kernel Image" -d vmlinux.bin uImage.uncompressed
+
+------------------------------------------------------------------------
+Stefan Roese, 2012-08-23
diff --git a/board/a3m071/a3m071.c b/board/a3m071/a3m071.c
new file mode 100644
index 0000000000..7e16aaf4b2
--- /dev/null
+++ b/board/a3m071/a3m071.c
@@ -0,0 +1,479 @@ 
+/*
+ * (C) Copyright 2003-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * (C) Copyright 2006
+ * MicroSys GmbH
+ *
+ * Copyright 2012-2013 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <mpc5xxx.h>
+#include <pci.h>
+#include <miiphy.h>
+#include <linux/compiler.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+
+#ifdef CONFIG_A4M2K
+#include "is46r16320d.h"
+#else
+#include "mt46v16m16-75.h"
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if !defined(CONFIG_SYS_RAMBOOT) && \
+	(defined(CONFIG_SPL) && defined(CONFIG_SPL_BUILD))
+static void sdram_start(int hi_addr)
+{
+	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
+	long control = SDRAM_CONTROL | hi_addr_bit;
+
+	/* unlock mode register */
+	out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000000);
+
+	/* precharge all banks */
+	out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000002);
+
+#ifdef SDRAM_DDR
+	/* set mode register: extended mode */
+	out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_EMODE);
+
+	/* set mode register: reset DLL */
+	out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_MODE | 0x04000000);
+#endif
+
+	/* precharge all banks */
+	out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000002);
+
+	/* auto refresh */
+	out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000004);
+
+	/* set mode register */
+	out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_MODE);
+
+	/* normal operation */
+	out_be32((void *)MPC5XXX_SDRAM_CTRL, control);
+
+	/*
+	 * Wait a short while for the DLL to lock before accessing
+	 * the SDRAM
+	 */
+	udelay(100);
+}
+#endif
+
+/*
+ * ATTENTION: Although partially referenced dram_init does NOT make real use
+ * use of CONFIG_SYS_SDRAM_BASE. The code does not work if
+ * CONFIG_SYS_SDRAM_BASE is something else than 0x00000000.
+ */
+int dram_init(void)
+{
+	ulong dramsize = 0;
+	ulong dramsize2 = 0;
+	uint svr, pvr;
+#if !defined(CONFIG_SYS_RAMBOOT) && \
+	(defined(CONFIG_SPL) && defined(CONFIG_SPL_BUILD))
+	ulong test1, test2;
+
+	/* setup SDRAM chip selects */
+	out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0x0000001e);	/* 2GB at 0x0 */
+	out_be32((void *)MPC5XXX_SDRAM_CS1CFG, 0x80000000);	/* disabled */
+
+	/* setup config registers */
+	out_be32((void *)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1);
+	out_be32((void *)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2);
+
+#ifdef SDRAM_DDR
+	/* set tap delay */
+	out_be32((void *)MPC5XXX_CDM_PORCFG, SDRAM_TAPDELAY);
+#endif
+
+	/* find RAM size using SDRAM CS0 only */
+	sdram_start(0);
+	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
+	sdram_start(1);
+	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
+	if (test1 > test2) {
+		sdram_start(0);
+		dramsize = test1;
+	} else {
+		dramsize = test2;
+	}
+
+	/* memory smaller than 1MB is impossible */
+	if (dramsize < (1 << 20))
+		dramsize = 0;
+
+	/* set SDRAM CS0 size according to the amount of RAM found */
+	if (dramsize > 0) {
+		out_be32((void *)MPC5XXX_SDRAM_CS0CFG,
+			 0x13 + __builtin_ffs(dramsize >> 20) - 1);
+	} else {
+		out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0);	/* disabled */
+	}
+#else /* CONFIG_SYS_RAMBOOT */
+
+	/* retrieve size of memory connected to SDRAM CS0 */
+	dramsize = in_be32((void *)MPC5XXX_SDRAM_CS0CFG) & 0xFF;
+	if (dramsize >= 0x13)
+		dramsize = (1 << (dramsize - 0x13)) << 20;
+	else
+		dramsize = 0;
+
+	/* retrieve size of memory connected to SDRAM CS1 */
+	dramsize2 = in_be32((void *)MPC5XXX_SDRAM_CS1CFG) & 0xFF;
+	if (dramsize2 >= 0x13)
+		dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
+	else
+		dramsize2 = 0;
+
+#endif /* CONFIG_SYS_RAMBOOT */
+
+	/*
+	 * On MPC5200B we need to set the special configuration delay in the
+	 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
+	 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
+	 *
+	 * "The SDelay should be written to a value of 0x00000004. It is
+	 * required to account for changes caused by normal wafer processing
+	 * parameters."
+	 */
+	svr = get_svr();
+	pvr = get_pvr();
+	if ((SVR_MJREV(svr) >= 2) && (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4))
+		out_be32((void *)MPC5XXX_SDRAM_SDELAY, 0x04);
+
+	gd->ram_size = dramsize + dramsize2;
+
+	return 0;
+}
+
+static void get_revisions(int *failsavelevel, int *digiboardversion,
+	int *fpgaversion)
+{
+	struct mpc5xxx_gpt_0_7 *gpt = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT;
+	u8 val;
+
+	/* read digitalboard-version from TMR[2..4] */
+	val = 0;
+	val |= (gpt->gpt2.sr & (1 << (31 - 23))) ? (1) : 0;
+	val |= (gpt->gpt3.sr & (1 << (31 - 23))) ? (1 << 1) : 0;
+	val |= (gpt->gpt4.sr & (1 << (31 - 23))) ? (1 << 2) : 0;
+	*digiboardversion = val;
+
+	/*
+	 * A4M2K only supports digiboardversion. No failsavelevel and
+	 * fpgaversion here.
+	 */
+#if !defined(CONFIG_A4M2K)
+	/*
+	 * Figure out failsavelevel
+	 * see ticket dsvk#59
+	 */
+	*failsavelevel = 0;	/* 0=failsave, 1=board ok, 2=fpga ok */
+
+	if (*digiboardversion == 0) {
+		*failsavelevel = 1;	/* digiboard-version ok */
+
+		/* read fpga-version from TMR[5..7] */
+		val = 0;
+		val |= (gpt->gpt5.sr & (1 << (31 - 23))) ? (1) : 0;
+		val |= (gpt->gpt6.sr & (1 << (31 - 23))) ? (1 << 1) : 0;
+		val |= (gpt->gpt7.sr & (1 << (31 - 23))) ? (1 << 2) : 0;
+		*fpgaversion = val;
+
+		if (*fpgaversion == 1)
+			*failsavelevel = 2;	/* fpga-version ok */
+	}
+#endif
+}
+
+/*
+ * This function is called from the SPL U-Boot version for
+ * early init stuff, that needs to be done for OS (e.g. Linux)
+ * booting. Doing it later in the real U-Boot would not work
+ * in case that the SPL U-Boot boots Linux directly.
+ */
+void spl_board_init(void)
+{
+	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
+	struct mpc5xxx_mmap_ctl *mm =
+		(struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR;
+
+#if defined(CONFIG_A4M2K)
+	/* enable CS3 and CS5 (FPGA) */
+	setbits_be32(&mm->ipbi_ws_ctrl, (1 << 19) | (1 << 21));
+#else
+	int digiboardversion;
+	int failsavelevel;
+	int fpgaversion;
+	u32 val;
+
+	get_revisions(&failsavelevel, &digiboardversion, &fpgaversion);
+
+	val = in_be32(&mm->ipbi_ws_ctrl);
+
+	/* first clear bits 19..21 (CS3...5) */
+	val &= ~((1 << 19) | (1 << 20) | (1 << 21));
+	if (failsavelevel == 2) {
+		/* FPGA ok */
+		val |= (1 << 19) | (1 << 21);
+	}
+
+	if (failsavelevel >= 1) {
+		/* at least digiboard-version ok */
+		val |= (1 << 20);
+	}
+
+	/* And write new value back to register */
+	out_be32(&mm->ipbi_ws_ctrl, val);
+
+
+	/* Setup pin multiplexing */
+	if (failsavelevel == 2) {
+		/* fpga-version ok */
+#if defined(CONFIG_SYS_GPS_PORT_CONFIG_2)
+		out_be32(&gpio->port_config, CONFIG_SYS_GPS_PORT_CONFIG_2);
+#endif
+	} else if (failsavelevel == 1) {
+		/* digiboard-version ok - fpga not */
+#if defined(CONFIG_SYS_GPS_PORT_CONFIG_1)
+		out_be32(&gpio->port_config, CONFIG_SYS_GPS_PORT_CONFIG_1);
+#endif
+	} else {
+		/* full failsave-mode */
+#if defined(CONFIG_SYS_GPS_PORT_CONFIG)
+		out_be32(&gpio->port_config, CONFIG_SYS_GPS_PORT_CONFIG);
+#endif
+	}
+#endif
+
+	/*
+	 * Setup gpio_wkup_7 as watchdog AS INPUT to disable it - see
+	 * ticket #60
+	 *
+	 * MPC5XXX_WU_GPIO_DIR direction is already 0 (INPUT)
+	 * set bit 0(msb) to 1
+	 */
+	setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, CONFIG_WDOG_GPIO_PIN);
+
+#if defined(CONFIG_A4M2K)
+	/* Setup USB[x] as MPCDiag[0..3] GPIO outputs */
+
+	/* set USB0,6,7,8 (MPCDiag[0..3]) direction to output */
+	gpio->simple_ddr |= 1 << (31 - 15);
+	gpio->simple_ddr |= 1 << (31 - 14);
+	gpio->simple_ddr |= 1 << (31 - 13);
+	gpio->simple_ddr |= 1 << (31 - 12);
+
+	/* enable USB0,6,7,8 (MPCDiag[0..3]) as GPIO */
+	gpio->simple_gpioe |= 1 << (31 - 15);
+	gpio->simple_gpioe |= 1 << (31 - 14);
+	gpio->simple_gpioe |= 1 << (31 - 13);
+	gpio->simple_gpioe |= 1 << (31 - 12);
+
+	/* Setup PSC2[0..2] as STSLED[0..2] GPIO outputs */
+
+	/* set PSC2[0..2] (STSLED[0..2]) direction to output */
+	gpio->simple_ddr |= 1 << (31 - 27);
+	gpio->simple_ddr |= 1 << (31 - 26);
+	gpio->simple_ddr |= 1 << (31 - 25);
+
+	/* enable PSC2[0..2] (STSLED[0..2]) as GPIO */
+	gpio->simple_gpioe |= 1 << (31 - 27);
+	gpio->simple_gpioe |= 1 << (31 - 26);
+	gpio->simple_gpioe |= 1 << (31 - 25);
+
+	/* Setup PSC6[2] as MRST2 self reset GPIO output */
+
+	/* set PSC6[2]/IRDA_TX (MRST2) direction to output */
+	gpio->simple_ddr |= 1 << (31 - 3);
+
+	/* set PSC6[2]/IRDA_TX (MRST2) output as open drain */
+	gpio->simple_ode |= 1 << (31 - 3);
+
+	/* set PSC6[2]/IRDA_TX (MRST2) output as default high */
+	gpio->simple_dvo |= 1 << (31 - 3);
+
+	/* enable PSC6[2]/IRDA_TX (MRST2) as GPIO */
+	gpio->simple_gpioe |= 1 << (31 - 3);
+
+	/* Setup PSC6[3] as HARNSSCD harness code GPIO input */
+
+	/* set PSC6[3]/IR_USB_CLK (HARNSSCD) direction to input */
+	gpio->simple_ddr |= 0 << (31 - 2);
+
+	/* enable PSC6[3]/IR_USB_CLK (HARNSSCD) as GPIO */
+	gpio->simple_gpioe |= 1 << (31 - 2);
+#else
+	/* setup GPIOs for status-leds if needed - see ticket #57 */
+	if (failsavelevel > 0) {
+		/* digiboard-version is OK */
+		/* LED is LOW ACTIVE - so deactivate by set output to 1 */
+		gpio->simple_dvo |= 1 << (31 - 12);
+		gpio->simple_dvo |= 1 << (31 - 13);
+		/* set GPIO direction to output */
+		gpio->simple_ddr |= 1 << (31 - 12);
+		gpio->simple_ddr |= 1 << (31 - 13);
+		/* open drain config is set to "normal output" at reset */
+		/* gpio->simple_ode &=~ ( 1 << (31-12) ); */
+		/* gpio->simple_ode &=~ ( 1 << (31-13) ); */
+		/* enable as GPIO */
+		gpio->simple_gpioe |= 1 << (31 - 12);
+		gpio->simple_gpioe |= 1 << (31 - 13);
+	}
+
+	/* setup fpga irq - see ticket #65 */
+	if (failsavelevel > 1) {
+		/*
+		 * The main irq initialisation is done in interrupts.c
+		 * mpc5xxx_init_irq
+		 */
+		struct mpc5xxx_intr *intr =
+		    (struct mpc5xxx_intr *)(MPC5XXX_ICTL);
+
+		setbits_be32(&intr->ctrl, 0x08C01801);
+
+		/*
+		 * The MBAR+0x0524 Bit 21:23 CSe are ignored here due to the
+		 * already cleared (intr_ctrl) MBAR+0x0510 ECLR[0] bit above
+		 */
+	}
+#endif
+}
+
+int checkboard(void)
+{
+	int digiboardversion;
+	int failsavelevel;
+	int fpgaversion;
+
+	get_revisions(&failsavelevel, &digiboardversion, &fpgaversion);
+
+#ifdef CONFIG_A4M2K
+	puts("Board: A4M2K\n");
+	printf("       digiboard IO version %u\n", digiboardversion);
+#else
+	puts("Board: A3M071\n");
+	printf("Rev:   failsave level       %u\n", failsavelevel);
+	printf("       digiboard IO version %u\n", digiboardversion);
+	if (failsavelevel > 0)	/* only if fpga-version red */
+		printf("       fpga IO version      %u\n", fpgaversion);
+#endif
+
+	return 0;
+}
+
+/* miscellaneous platform dependent initialisations */
+int misc_init_r(void)
+{
+	/* adjust flash start and offset to detected values */
+	gd->bd->bi_flashstart = flash_info[0].start[0];
+	gd->bd->bi_flashoffset = 0;
+
+	/* adjust mapping */
+	out_be32((void *)MPC5XXX_BOOTCS_START,
+		 START_REG(gd->bd->bi_flashstart));
+	out_be32((void *)MPC5XXX_CS0_START, START_REG(gd->bd->bi_flashstart));
+	out_be32((void *)MPC5XXX_BOOTCS_STOP,
+		 STOP_REG(gd->bd->bi_flashstart, gd->bd->bi_flashsize));
+	out_be32((void *)MPC5XXX_CS0_STOP,
+		 STOP_REG(gd->bd->bi_flashstart, gd->bd->bi_flashsize));
+
+	return 0;
+}
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, bd_t *bd)
+{
+	ft_cpu_setup(blob, bd);
+
+	return 0;
+}
+#endif /* CONFIG_OF_BOARD_SETUP */
+
+#ifdef CONFIG_SPL_OS_BOOT
+/*
+ * A3M071 specific implementation of spl_start_uboot()
+ *
+ * RETURN
+ * 0 if booting into OS is selected (default)
+ * 1 if booting into U-Boot is selected
+ */
+int spl_start_uboot(void)
+{
+	char s[8];
+
+	env_init();
+	getenv_f("boot_os", s, sizeof(s));
+	if ((s != NULL) && (*s == '1' || *s == 'y' || *s == 'Y' ||
+			    *s == 't' || *s == 'T'))
+		return 0;
+
+	return 1;
+}
+#endif
+
+#if defined(CONFIG_HW_WATCHDOG)
+static int watchdog_toggle;
+
+void hw_watchdog_reset(void)
+{
+	int val;
+
+	/*
+	 * Check if watchdog is enabled via user command
+	 */
+	if ((gd->flags & GD_FLG_RELOC) && watchdog_toggle) {
+		/* Set direction to output */
+		setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, CONFIG_WDOG_GPIO_PIN);
+
+		/*
+		 * Toggle watchdog output
+		 */
+		val = (in_be32((void *)MPC5XXX_WU_GPIO_DATA_O) &
+		       CONFIG_WDOG_GPIO_PIN);
+		if (val) {
+			clrbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O,
+				     CONFIG_WDOG_GPIO_PIN);
+		} else {
+			setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O,
+				     CONFIG_WDOG_GPIO_PIN);
+		}
+	}
+}
+
+int do_wdog_toggle(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	if (argc != 2)
+		goto usage;
+
+	if (strncmp(argv[1], "on", 2) == 0)
+		watchdog_toggle = 1;
+	else if (strncmp(argv[1], "off", 3) == 0)
+		watchdog_toggle = 0;
+	else
+		goto usage;
+
+	return 0;
+usage:
+	printf("Usage: wdogtoggle %s\n", cmdtp->usage);
+	return 1;
+}
+
+U_BOOT_CMD(
+	wdogtoggle, CONFIG_SYS_MAXARGS, 2, do_wdog_toggle,
+	"toggle GPIO pin to service watchdog",
+	"[on/off] - Switch watchdog toggling via GPIO pin on/off"
+);
+#endif
diff --git a/board/a3m071/is46r16320d.h b/board/a3m071/is46r16320d.h
new file mode 100644
index 0000000000..981359f22b
--- /dev/null
+++ b/board/a3m071/is46r16320d.h
@@ -0,0 +1,24 @@ 
+/*
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#define SDRAM_DDR		/* is DDR */
+
+#if defined(CONFIG_MPC5200)
+/* Settings for XLB = 132 MHz */
+/* see is46r16320d datasheet and MPC5200UM chap. 8.6.1. */
+
+/* SDRAM Config Standard timing */
+#define SDRAM_MODE	0x008d0000
+#define SDRAM_EMODE	0x40010000
+#define SDRAM_CONTROL	0x70430f00
+#define SDRAM_CONFIG1	0x33622930
+#define SDRAM_CONFIG2	0x46670000
+#define SDRAM_TAPDELAY	0x10000000
+
+#else
+#error CONFIG_MPC5200 not defined
+#endif
diff --git a/board/a3m071/mt46v16m16-75.h b/board/a3m071/mt46v16m16-75.h
new file mode 100644
index 0000000000..8f428306fe
--- /dev/null
+++ b/board/a3m071/mt46v16m16-75.h
@@ -0,0 +1,21 @@ 
+/*
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#define SDRAM_DDR		/* is DDR */
+
+#if defined(CONFIG_MPC5200)
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE	0x018D0000
+#define SDRAM_EMODE	0x40090000
+#define SDRAM_CONTROL	0x704f0f00
+#define SDRAM_CONFIG1	0x73722930
+#define SDRAM_CONFIG2	0x47770000
+#define SDRAM_TAPDELAY	0x10000000
+
+#else
+#error CONFIG_MPC5200 not defined
+#endif
diff --git a/board/a4m072/Kconfig b/board/a4m072/Kconfig
new file mode 100644
index 0000000000..ba5447fb9a
--- /dev/null
+++ b/board/a4m072/Kconfig
@@ -0,0 +1,9 @@ 
+if TARGET_A4M072
+
+config SYS_BOARD
+	default "a4m072"
+
+config SYS_CONFIG_NAME
+	default "a4m072"
+
+endif
diff --git a/board/a4m072/MAINTAINERS b/board/a4m072/MAINTAINERS
new file mode 100644
index 0000000000..83dc59e87f
--- /dev/null
+++ b/board/a4m072/MAINTAINERS
@@ -0,0 +1,6 @@ 
+A4M072 BOARD
+M:	Sergei Poselenov <sposelenov@emcraft.com>
+S:	Maintained
+F:	board/a4m072/
+F:	include/configs/a4m072.h
+F:	configs/a4m072_defconfig
diff --git a/board/a4m072/Makefile b/board/a4m072/Makefile
new file mode 100644
index 0000000000..2a40e5799e
--- /dev/null
+++ b/board/a4m072/Makefile
@@ -0,0 +1,8 @@ 
+#
+# (C) Copyright 2003-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	:= a4m072.o
diff --git a/board/a4m072/a4m072.c b/board/a4m072/a4m072.c
new file mode 100644
index 0000000000..6f0d4489a2
--- /dev/null
+++ b/board/a4m072/a4m072.c
@@ -0,0 +1,479 @@ 
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * (C) Copyright 2010
+ * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <libfdt.h>
+#include <netdev.h>
+#include <led-display.h>
+#include <linux/err.h>
+
+#include "mt46v32m16.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifndef CONFIG_SYS_RAMBOOT
+static void sdram_start (int hi_addr)
+{
+	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
+	long control = SDRAM_CONTROL | hi_addr_bit;
+
+	/* unlock mode register */
+	out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000000);
+	__asm__ volatile ("sync");
+
+	/* precharge all banks */
+	out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000002);
+	__asm__ volatile ("sync");
+
+#if SDRAM_DDR
+	/* set mode register: extended mode */
+	out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_EMODE);
+	__asm__ volatile ("sync");
+
+	/* set mode register: reset DLL */
+	out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_MODE | 0x04000000);
+	__asm__ volatile ("sync");
+#endif
+
+	/* precharge all banks */
+	out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000002);
+	__asm__ volatile ("sync");
+
+	/* auto refresh */
+	out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000004);
+	__asm__ volatile ("sync");
+
+	/* set mode register */
+	out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_MODE);
+	__asm__ volatile ("sync");
+
+	/* normal operation */
+	out_be32((void *)MPC5XXX_SDRAM_CTRL, control);
+	__asm__ volatile ("sync");
+}
+#endif
+
+/*
+ * ATTENTION: Although partially referenced dram_init does NOT make real use
+ *            use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
+ *            is something else than 0x00000000.
+ */
+
+int dram_init(void)
+{
+	ulong dramsize = 0;
+	uint svr, pvr;
+
+#ifndef CONFIG_SYS_RAMBOOT
+	ulong test1, test2;
+
+	/* setup SDRAM chip selects */
+	out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0x0000001e); /* 2GB at 0x0 */
+	out_be32((void *)MPC5XXX_SDRAM_CS1CFG, 0x80000000); /* disabled */
+	__asm__ volatile ("sync");
+
+	/* setup config registers */
+	out_be32((void *)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1);
+	out_be32((void *)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2);
+	__asm__ volatile ("sync");
+
+#if SDRAM_DDR
+	/* set tap delay */
+	out_be32((void *)MPC5XXX_CDM_PORCFG, SDRAM_TAPDELAY);
+	__asm__ volatile ("sync");
+#endif
+
+	/* find RAM size using SDRAM CS0 only */
+	sdram_start(0);
+	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
+	sdram_start(1);
+	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
+	if (test1 > test2) {
+		sdram_start(0);
+		dramsize = test1;
+	} else {
+		dramsize = test2;
+	}
+
+	/* memory smaller than 1MB is impossible */
+	if (dramsize < (1 << 20)) {
+		dramsize = 0;
+	}
+
+	/* set SDRAM CS0 size according to the amount of RAM found */
+	if (dramsize > 0) {
+		out_be32((void *)MPC5XXX_SDRAM_CS0CFG,
+				 0x13 + __builtin_ffs(dramsize >> 20) - 1);
+	} else {
+		out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0); /* disabled */
+	}
+
+#else /* CONFIG_SYS_RAMBOOT */
+
+	/* retrieve size of memory connected to SDRAM CS0 */
+	dramsize = in_be32((void *)MPC5XXX_SDRAM_CS0CFG) & 0xFF;
+	if (dramsize >= 0x13) {
+		dramsize = (1 << (dramsize - 0x13)) << 20;
+	} else {
+		dramsize = 0;
+	}
+
+#endif /* CONFIG_SYS_RAMBOOT */
+
+	/*
+	 * On MPC5200B we need to set the special configuration delay in the
+	 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
+	 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
+	 *
+	 * "The SDelay should be written to a value of 0x00000004. It is
+	 * required to account for changes caused by normal wafer processing
+	 * parameters."
+	 */
+	svr = get_svr();
+	pvr = get_pvr();
+	if ((SVR_MJREV(svr) >= 2) &&
+	    (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
+
+		out_be32((void *)MPC5XXX_SDRAM_SDELAY, 0x04);
+		__asm__ volatile ("sync");
+	}
+
+	gd->ram_size = dramsize;
+
+	return 0;
+}
+
+int checkboard (void)
+{
+	puts ("Board: A4M072\n");
+	return 0;
+}
+
+#ifdef	CONFIG_PCI
+static struct pci_controller hose;
+
+extern void pci_mpc5xxx_init(struct pci_controller *);
+
+void pci_init_board(void)
+{
+	pci_mpc5xxx_init(&hose);
+}
+#endif
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, bd_t *bd)
+{
+	ft_cpu_setup(blob, bd);
+
+	return 0;
+}
+#endif /* CONFIG_OF_BOARD_SETUP */
+
+int board_eth_init(bd_t *bis)
+{
+	int rv, num_if = 0;
+
+	/* Initialize TSECs first */
+	if ((rv = cpu_eth_init(bis)) >= 0)
+		num_if += rv;
+	else
+		printf("ERROR: failed to initialize FEC.\n");
+
+	if ((rv = pci_eth_init(bis)) >= 0)
+		num_if += rv;
+	else
+		printf("ERROR: failed to initialize PCI Ethernet.\n");
+
+	return num_if;
+}
+/*
+ * Miscellaneous late-boot configurations
+ *
+ * Initialize EEPROM write-protect GPIO pin.
+ */
+int misc_init_r(void)
+{
+#if defined(CONFIG_SYS_EEPROM_WREN)
+	/* Enable GPIO pin */
+	setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, CONFIG_SYS_EEPROM_WP);
+	/* Set direction, output */
+	setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, CONFIG_SYS_EEPROM_WP);
+	/* De-assert write enable */
+	setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, CONFIG_SYS_EEPROM_WP);
+#endif
+	return 0;
+}
+#if defined(CONFIG_SYS_EEPROM_WREN)
+/* Input: <dev_addr>  I2C address of EEPROM device to enable.
+ *         <state>     -1: deliver current state
+ *	               0: disable write
+ *		       1: enable write
+ *  Returns:           -1: wrong device address
+ *                      0: dis-/en- able done
+ *		     0/1: current state if <state> was -1.
+ */
+int eeprom_write_enable (unsigned dev_addr, int state)
+{
+	if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) {
+		return -1;
+	} else {
+		switch (state) {
+		case 1:
+			/* Enable write access */
+			clrbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, CONFIG_SYS_EEPROM_WP);
+			state = 0;
+			break;
+		case 0:
+			/* Disable write access */
+			setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, CONFIG_SYS_EEPROM_WP);
+			state = 0;
+			break;
+		default:
+			/* Read current status back. */
+			state = (0 == (in_be32((void *)MPC5XXX_WU_GPIO_DATA_O) &
+						   CONFIG_SYS_EEPROM_WP));
+			break;
+		}
+	}
+	return state;
+}
+#endif
+
+#ifdef CONFIG_CMD_DISPLAY
+#define DISPLAY_BUF_SIZE	2
+static u8 display_buf[DISPLAY_BUF_SIZE];
+static u8 display_putc_pos;
+static u8 display_out_pos;
+
+void display_set(int cmd) {
+
+	if (cmd & DISPLAY_CLEAR) {
+		display_buf[0] = display_buf[1] = 0;
+	}
+
+	if (cmd & DISPLAY_HOME) {
+		display_putc_pos = 0;
+	}
+}
+
+#define SEG_A    (1<<0)
+#define SEG_B    (1<<1)
+#define SEG_C    (1<<2)
+#define SEG_D    (1<<3)
+#define SEG_E    (1<<4)
+#define SEG_F    (1<<5)
+#define SEG_G    (1<<6)
+#define SEG_P    (1<<7)
+#define SEG__    0
+
+/*
+ * +- A -+
+ * |     |
+ * F     B
+ * |     |
+ * +- G -+
+ * |     |
+ * E     C
+ * |     |
+ * +- D -+  P
+ *
+ * 0..9		index 0..9
+ * A..Z		index 10..35
+ * -		index 36
+ * _		index 37
+ * .		index 38
+ */
+
+#define SYMBOL_DASH		(36)
+#define SYMBOL_UNDERLINE	(37)
+#define SYMBOL_DOT		(38)
+
+static u8 display_char2seg7_tbl[]=
+{
+	SEG_A | SEG_B | SEG_C | SEG_D | SEG_E | SEG_F,		/* 0 */
+	SEG_B | SEG_C,						/* 1 */
+	SEG_A | SEG_B | SEG_D | SEG_E | SEG_G,			/* 2 */
+	SEG_A | SEG_B | SEG_C | SEG_D | SEG_G,			/* 3 */
+	SEG_B | SEG_C | SEG_F | SEG_G,				/* 4 */
+	SEG_A | SEG_C | SEG_D | SEG_F | SEG_G,			/* 5 */
+	SEG_A | SEG_C | SEG_D | SEG_E | SEG_F | SEG_G,		/* 6 */
+	SEG_A | SEG_B | SEG_C,					/* 7 */
+	SEG_A | SEG_B | SEG_C | SEG_D | SEG_E | SEG_F | SEG_G,	/* 8 */
+	SEG_A | SEG_B | SEG_C | SEG_D | SEG_F | SEG_G,		/* 9 */
+	SEG_A | SEG_B | SEG_C | SEG_E | SEG_F | SEG_G,		/* A */
+	SEG_C | SEG_D | SEG_E | SEG_F | SEG_G,			/* b */
+	SEG_A | SEG_D | SEG_E | SEG_F,				/* C */
+	SEG_B | SEG_C | SEG_D | SEG_E | SEG_G,			/* d */
+	SEG_A | SEG_D | SEG_E | SEG_F | SEG_G,			/* E */
+	SEG_A | SEG_E | SEG_F | SEG_G,				/* F */
+	0,					/* g - not displayed */
+	SEG_B | SEG_C | SEG_E | SEG_F | SEG_G,			/* H */
+	SEG_B | SEG_C,						/* I */
+	0,					/* J - not displayed */
+	0,					/* K - not displayed */
+	SEG_D | SEG_E | SEG_F,					/* L */
+	0,					/* m - not displayed */
+	0,					/* n - not displayed */
+	SEG_A | SEG_B | SEG_C | SEG_D | SEG_E | SEG_F,		/* O */
+	SEG_A | SEG_B | SEG_E | SEG_F | SEG_G,			/* P */
+	0,					/* q - not displayed */
+	0,					/* r - not displayed */
+	SEG_A | SEG_C | SEG_D | SEG_F | SEG_G,			/* S */
+	SEG_D | SEG_E | SEG_F | SEG_G,				/* t */
+	SEG_B | SEG_C | SEG_D | SEG_E | SEG_F,			/* U */
+	0,					/* V - not displayed */
+	0,					/* w - not displayed */
+	0,					/* X - not displayed */
+	SEG_B | SEG_C | SEG_D | SEG_F | SEG_G,			/* Y */
+	0,					/* Z - not displayed */
+	SEG_G,							/* - */
+	SEG_D,							/* _ */
+	SEG_P							/* . */
+};
+
+/* Convert char to the LED segments representation */
+static u8 display_char2seg7(char c)
+{
+	u8 val = 0;
+
+	if (c >= '0' && c <= '9')
+		c -= '0';
+	else if (c >= 'a' && c <= 'z')
+		c -= 'a' - 10;
+	else if (c >= 'A' && c <= 'Z')
+		c -= 'A' - 10;
+	else if (c == '-')
+		c = SYMBOL_DASH;
+	else if (c == '_')
+		c = SYMBOL_UNDERLINE;
+	else if (c == '.')
+		c = SYMBOL_DOT;
+	else
+		c = ' ';	/* display unsupported symbols as space */
+
+	if (c != ' ')
+		val = display_char2seg7_tbl[(int)c];
+
+	return val;
+}
+
+int display_putc(char c)
+{
+	if (display_putc_pos >= DISPLAY_BUF_SIZE)
+		return -1;
+
+	display_buf[display_putc_pos++] = display_char2seg7(c);
+	/* one-symbol message should be steady */
+	if (display_putc_pos == 1)
+		display_buf[display_putc_pos] = display_char2seg7(c);
+
+	return c;
+}
+
+/*
+ * Flush current symbol to the LED display hardware
+ */
+static inline void display_flush(void)
+{
+	u32 val = display_buf[display_out_pos];
+
+	val |= (val << 8) | (val << 16) | (val << 24);
+	out_be32((void *)CONFIG_SYS_DISP_CHR_RAM, val);
+}
+
+/*
+ * Output contents of the software display buffer to the LED display every 0.5s
+ */
+void board_show_activity(ulong timestamp)
+{
+	static ulong last;
+	static u8 once;
+
+	if (!once || (timestamp - last >= (CONFIG_SYS_HZ / 2))) {
+		display_flush();
+		display_out_pos ^= 1;
+		last = timestamp;
+		once = 1;
+	}
+}
+
+/*
+ * Empty fake function
+ */
+void show_activity(int arg)
+{
+}
+#endif
+#if defined (CONFIG_SHOW_BOOT_PROGRESS)
+static int a4m072_status2code(int status, char *buf)
+{
+	char c = 0;
+
+	if (((status > 0) && (status <= 8)) ||
+				((status >= 100) && (status <= 108)) ||
+				((status < 0) && (status >= -9)) ||
+				(status == -100) || (status == -101) ||
+				((status <= -103) && (status >= -113))) {
+		c = '5';
+	} else if (((status >= 9) && (status <= 14)) ||
+			((status >= 120) && (status <= 123)) ||
+			((status >= 125) && (status <= 129)) ||
+			((status >= -13) && (status <= -10)) ||
+			(status == -120) || (status == -122) ||
+			((status <= -124) && (status >= -127)) ||
+			(status == -129)) {
+		c = '8';
+	} else if (status == 15) {
+		c = '9';
+	} else if ((status <= -30) && (status >= -32)) {
+		c = 'A';
+	} else if (((status <= -35) && (status >= -40)) ||
+			((status <= -42) && (status >= -51)) ||
+			((status <= -53) && (status >= -58)) ||
+			(status == -64) ||
+			((status <= -80) && (status >= -83)) ||
+			(status == -130) || (status == -140) ||
+			(status == -150)) {
+		c = 'B';
+	}
+
+	if (c == 0)
+		return -EINVAL;
+
+	buf[0] = (status < 0) ? '-' : c;
+	buf[1] = c;
+
+	return 0;
+}
+
+void show_boot_progress(int status)
+{
+	char buf[2];
+
+	if (a4m072_status2code(status, buf) < 0)
+		return;
+
+	display_putc(buf[0]);
+	display_putc(buf[1]);
+	display_set(DISPLAY_HOME);
+	display_out_pos = 0;	/* reset output position */
+
+	/* we want to flush status 15 now */
+	if (status == BOOTSTAGE_ID_RUN_OS)
+		display_flush();
+}
+#endif
diff --git a/board/a4m072/mt46v32m16.h b/board/a4m072/mt46v32m16.h
new file mode 100644
index 0000000000..c0a08a8452
--- /dev/null
+++ b/board/a4m072/mt46v32m16.h
@@ -0,0 +1,21 @@ 
+/*
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#define SDRAM_DDR	1		/* is DDR */
+
+#if defined(CONFIG_MPC5200)
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE	0x018D0000
+#define SDRAM_EMODE	0x40010000
+#define SDRAM_CONTROL	0x704f0f00
+#define SDRAM_CONFIG1	0x73722930
+#define SDRAM_CONFIG2	0x47770000
+#define SDRAM_TAPDELAY	0x10000000
+
+#else
+#error CONFIG_MPC5200 not defined
+#endif
diff --git a/board/canmb/Kconfig b/board/canmb/Kconfig
new file mode 100644
index 0000000000..b5cf2057f4
--- /dev/null
+++ b/board/canmb/Kconfig
@@ -0,0 +1,9 @@ 
+if TARGET_CANMB
+
+config SYS_BOARD
+	default "canmb"
+
+config SYS_CONFIG_NAME
+	default "canmb"
+
+endif
diff --git a/board/canmb/MAINTAINERS b/board/canmb/MAINTAINERS
new file mode 100644
index 0000000000..71750ead47
--- /dev/null
+++ b/board/canmb/MAINTAINERS
@@ -0,0 +1,6 @@ 
+CANMB BOARD
+#M:	-
+S:	Maintained
+F:	board/canmb/
+F:	include/configs/canmb.h
+F:	configs/canmb_defconfig
diff --git a/board/canmb/Makefile b/board/canmb/Makefile
new file mode 100644
index 0000000000..4286a9123c
--- /dev/null
+++ b/board/canmb/Makefile
@@ -0,0 +1,9 @@ 
+#
+# (C) Copyright 2005-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	:= canmb.o
+
diff --git a/board/canmb/canmb.c b/board/canmb/canmb.c
new file mode 100644
index 0000000000..54de0e2673
--- /dev/null
+++ b/board/canmb/canmb.c
@@ -0,0 +1,187 @@ 
+/*
+ * (C) Copyright 2005
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <pci.h>
+
+#if defined(CONFIG_MPC5200_DDR)
+#include "mt46v16m16-75.h"
+#else
+#include "mt48lc16m32s2-75.h"
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifndef CONFIG_SYS_RAMBOOT
+static void sdram_start (int hi_addr)
+{
+	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
+
+	/* unlock mode register */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* precharge all banks */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+#if SDRAM_DDR
+	/* set mode register: extended mode */
+	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
+	__asm__ volatile ("sync");
+
+	/* set mode register: reset DLL */
+	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
+	__asm__ volatile ("sync");
+#endif
+
+	/* precharge all banks */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* auto refresh */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* set mode register */
+	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
+	__asm__ volatile ("sync");
+
+	/* normal operation */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
+	__asm__ volatile ("sync");
+}
+#endif
+
+/*
+ * ATTENTION: Although partially referenced dram_init does NOT make real use
+ *            use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
+ *            is something else than 0x00000000.
+ */
+
+int dram_init(void)
+{
+	ulong dramsize = 0;
+	ulong dramsize2 = 0;
+#ifndef CONFIG_SYS_RAMBOOT
+	ulong test1, test2;
+
+	/* setup SDRAM chip selects */
+	*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
+	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
+	__asm__ volatile ("sync");
+
+	/* setup config registers */
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
+	__asm__ volatile ("sync");
+
+#if SDRAM_DDR
+	/* set tap delay */
+	*(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
+	__asm__ volatile ("sync");
+#endif
+
+	/* find RAM size using SDRAM CS0 only */
+	sdram_start(0);
+	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
+	sdram_start(1);
+	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
+	if (test1 > test2) {
+		sdram_start(0);
+		dramsize = test1;
+	} else {
+		dramsize = test2;
+	}
+
+	/* memory smaller than 1MB is impossible */
+	if (dramsize < (1 << 20)) {
+		dramsize = 0;
+	}
+
+	/* set SDRAM CS0 size according to the amount of RAM found */
+	if (dramsize > 0) {
+		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
+	} else {
+		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
+	}
+
+	/* let SDRAM CS1 start right after CS0 */
+	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
+
+	/* find RAM size using SDRAM CS1 only */
+	if (!dramsize)
+		sdram_start(0);
+	test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
+	if (!dramsize) {
+		sdram_start(1);
+		test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
+	}
+	if (test1 > test2) {
+		sdram_start(0);
+		dramsize2 = test1;
+	} else {
+		dramsize2 = test2;
+	}
+
+	/* memory smaller than 1MB is impossible */
+	if (dramsize2 < (1 << 20)) {
+		dramsize2 = 0;
+	}
+
+	/* set SDRAM CS1 size according to the amount of RAM found */
+	if (dramsize2 > 0) {
+		*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
+			| (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
+	} else {
+		*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
+	}
+
+#else /* CONFIG_SYS_RAMBOOT */
+
+	/* retrieve size of memory connected to SDRAM CS0 */
+	dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
+	if (dramsize >= 0x13) {
+		dramsize = (1 << (dramsize - 0x13)) << 20;
+	} else {
+		dramsize = 0;
+	}
+
+	/* retrieve size of memory connected to SDRAM CS1 */
+	dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
+	if (dramsize2 >= 0x13) {
+		dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
+	} else {
+		dramsize2 = 0;
+	}
+
+#endif /* CONFIG_SYS_RAMBOOT */
+
+	gd->ram_size = dramsize + dramsize2;
+
+	return 0;
+}
+
+int checkboard (void)
+{
+	puts ("Board: CANMB\n");
+	return 0;
+}
+
+int board_early_init_r (void)
+{
+	*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
+	*(vu_long *)MPC5XXX_BOOTCS_START =
+	*(vu_long *)MPC5XXX_CS0_START = START_REG(CONFIG_SYS_FLASH_BASE);
+	*(vu_long *)MPC5XXX_BOOTCS_STOP =
+	*(vu_long *)MPC5XXX_CS0_STOP = STOP_REG(CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE);
+	return 0;
+}
diff --git a/board/canmb/mt48lc16m32s2-75.h b/board/canmb/mt48lc16m32s2-75.h
new file mode 100644
index 0000000000..0133eaa2ca
--- /dev/null
+++ b/board/canmb/mt48lc16m32s2-75.h
@@ -0,0 +1,14 @@ 
+/*
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#define SDRAM_DDR	0		/* is SDR */
+
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE	0x00CD0000
+#define SDRAM_CONTROL	0x504F0000
+#define SDRAM_CONFIG1	0xD2322800
+#define SDRAM_CONFIG2	0x8AD70000
diff --git a/board/cm5200/Kconfig b/board/cm5200/Kconfig
new file mode 100644
index 0000000000..ccea5c96e4
--- /dev/null
+++ b/board/cm5200/Kconfig
@@ -0,0 +1,9 @@ 
+if TARGET_CM5200
+
+config SYS_BOARD
+	default "cm5200"
+
+config SYS_CONFIG_NAME
+	default "cm5200"
+
+endif
diff --git a/board/cm5200/MAINTAINERS b/board/cm5200/MAINTAINERS
new file mode 100644
index 0000000000..1e1df3f6dc
--- /dev/null
+++ b/board/cm5200/MAINTAINERS
@@ -0,0 +1,6 @@ 
+CM5200 BOARD
+#M:	-
+S:	Maintained
+F:	board/cm5200/
+F:	include/configs/cm5200.h
+F:	configs/cm5200_defconfig
diff --git a/board/cm5200/Makefile b/board/cm5200/Makefile
new file mode 100644
index 0000000000..76f8b9fc05
--- /dev/null
+++ b/board/cm5200/Makefile
@@ -0,0 +1,8 @@ 
+#
+# (C) Copyright 2003-2007
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	:= cm5200.o cmd_cm5200.o fwupdate.o
diff --git a/board/cm5200/cm5200.c b/board/cm5200/cm5200.c
new file mode 100644
index 0000000000..0c647bbd3d
--- /dev/null
+++ b/board/cm5200/cm5200.c
@@ -0,0 +1,355 @@ 
+/*
+ * (C) Copyright 2003-2007
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * (C) Copyright 2004-2005
+ * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
+ *
+ * Adapted to U-Boot 1.2 by:
+ *   Bartlomiej Sieka <tur@semihalf.com>:
+ *      - HW ID readout from EEPROM
+ *      - module detection
+ *   Grzegorz Bernacki <gjb@semihalf.com>:
+ *      - run-time SDRAM controller configuration
+ *      - LIBFDT support
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <i2c.h>
+#include <linux/ctype.h>
+
+#ifdef CONFIG_OF_LIBFDT
+#include <libfdt.h>
+#include <fdt_support.h>
+#endif /* CONFIG_OF_LIBFDT */
+
+
+#include "cm5200.h"
+#include "fwupdate.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static hw_id_t hw_id;
+
+
+#ifndef CONFIG_SYS_RAMBOOT
+/*
+ * Helper function to initialize SDRAM controller.
+ */
+static void sdram_start(int hi_addr, mem_conf_t *mem_conf)
+{
+	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
+
+	/* unlock mode register */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = mem_conf->control | 0x80000000 |
+						hi_addr_bit;
+
+	/* precharge all banks */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = mem_conf->control | 0x80000002 |
+						hi_addr_bit;
+
+	/* auto refresh */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = mem_conf->control | 0x80000004 |
+						hi_addr_bit;
+
+	/* auto refresh, second time */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = mem_conf->control | 0x80000004 |
+						hi_addr_bit;
+
+	/* set mode register */
+	*(vu_long *)MPC5XXX_SDRAM_MODE = mem_conf->mode;
+
+	/* normal operation */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = mem_conf->control | hi_addr_bit;
+}
+#endif /* CONFIG_SYS_RAMBOOT */
+
+
+/*
+ * Retrieve memory configuration for a given module. board_type is the index
+ * in hw_id_list[] corresponding to the module we are executing on; we return
+ * SDRAM controller settings approprate for this module.
+ */
+static mem_conf_t* get_mem_config(int board_type)
+{
+	switch(board_type){
+		case CM1_QA:
+			return memory_config[0];
+		case CM11_QA:
+		case CMU1_QA:
+			return memory_config[1];
+		default:
+			printf("ERROR: Unknown module, using a default SDRAM "
+				"configuration - things may not work!!!.\n");
+			return memory_config[0];
+	}
+}
+
+
+/*
+ * Initalize SDRAM - configure SDRAM controller, detect memory size.
+ */
+int dram_init(void)
+{
+	ulong dramsize = 0;
+#ifndef CONFIG_SYS_RAMBOOT
+	ulong test1, test2;
+	mem_conf_t *mem_conf;
+
+	mem_conf = get_mem_config(gd->board_type);
+
+	/* configure SDRAM start/end for detection */
+	*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */
+
+	/* setup config registers */
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = mem_conf->config1;
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = mem_conf->config2;
+
+	sdram_start(0, mem_conf);
+	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
+	sdram_start(1, mem_conf);
+	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
+	if (test1 > test2) {
+		sdram_start(0, mem_conf);
+		dramsize = test1;
+	} else
+		dramsize = test2;
+
+	/* memory smaller than 1MB is impossible */
+	if (dramsize < (1 << 20))
+		dramsize = 0;
+
+	/* set SDRAM CS0 size according to the amount of RAM found */
+	if (dramsize > 0) {
+		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 +
+			__builtin_ffs(dramsize >> 20) - 1;
+	} else
+		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
+#else /* CONFIG_SYS_RAMBOOT */
+	/* retrieve size of memory connected to SDRAM CS0 */
+	dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
+	if (dramsize >= 0x13)
+		dramsize = (1 << (dramsize - 0x13)) << 20;
+	else
+		dramsize = 0;
+#endif /* !CONFIG_SYS_RAMBOOT */
+
+	/*
+	 * On MPC5200B we need to set the special configuration delay in the
+	 * DDR controller.  Refer to chapter 8.7.5 SDelay--MBAR + 0x0190 of
+	 * the MPC5200B User's Manual.
+	 */
+	*(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
+	__asm__ volatile ("sync");
+
+	gd->ram_size = dramsize;
+
+	return 0;
+}
+
+
+/*
+ * Read module hardware identification data from the I2C EEPROM.
+ */
+static void read_hw_id(hw_id_t hw_id)
+{
+	printf("ERROR: can't read HW ID from EEPROM\n");
+}
+
+
+/*
+ * Identify module we are running on, set gd->board_type to the index in
+ * hw_id_list[] corresponding to the module identifed, or to
+ * CM5200_UNKNOWN_MODULE if we can't identify the module.
+ */
+static void identify_module(hw_id_t hw_id)
+{
+	int i, j, element;
+	char match;
+	gd->board_type = CM5200_UNKNOWN_MODULE;
+	for (i = 0; i < sizeof (hw_id_list) / sizeof (char **); ++i) {
+		match = 1;
+		for (j = 0; j < sizeof (hw_id_identify) / sizeof (int); ++j) {
+			element = hw_id_identify[j];
+			if (strncmp(hw_id_list[i][element],
+					&hw_id[element][0],
+					hw_id_format[element].length) != 0) {
+				match = 0;
+				break;
+			}
+		}
+		if (match) {
+			gd->board_type = i;
+			break;
+		}
+	}
+}
+
+
+/*
+ * Compose string with module name.
+ * buf is assumed to have enough space, and be null-terminated.
+ */
+static void compose_module_name(hw_id_t hw_id, char *buf)
+{
+	char tmp[MODULE_NAME_MAXLEN];
+	strncat(buf, &hw_id[PCB_NAME][0], hw_id_format[PCB_NAME].length);
+	strncat(buf, ".", 1);
+	strncat(buf, &hw_id[FORM][0], hw_id_format[FORM].length);
+	strncat(buf, &hw_id[VERSION][0], hw_id_format[VERSION].length);
+	strncat(buf, " (", 2);
+	strncat(buf, &hw_id[IDENTIFICATION_NUMBER][0],
+		hw_id_format[IDENTIFICATION_NUMBER].length);
+	sprintf(tmp, " / %u.%u)",
+		hw_id[MAJOR_SW_VERSION][0],
+		hw_id[MINOR_SW_VERSION][0]);
+	strcat(buf, tmp);
+}
+
+#if defined(CONFIG_SYS_I2C_SOFT)
+/*
+ * Compose string with hostname.
+ * buf is assumed to have enough space, and be null-terminated.
+ */
+static void compose_hostname(hw_id_t hw_id, char *buf)
+{
+	char *p;
+	strncat(buf, &hw_id[PCB_NAME][0], hw_id_format[PCB_NAME].length);
+	strncat(buf, "_", 1);
+	strncat(buf, &hw_id[FORM][0], hw_id_format[FORM].length);
+	strncat(buf, &hw_id[VERSION][0], hw_id_format[VERSION].length);
+	for (p = buf; *p; ++p)
+		*p = tolower(*p);
+
+}
+#endif
+
+#ifdef CONFIG_OF_BOARD_SETUP
+/*
+ * Update 'model' and 'memory' properties in the blob according to the module
+ * that we are running on.
+ */
+static void ft_blob_update(void *blob, bd_t *bd)
+{
+	int len, ret, nodeoffset = 0;
+	char module_name[MODULE_NAME_MAXLEN] = {0};
+
+	compose_module_name(hw_id, module_name);
+	len = strlen(module_name) + 1;
+
+	ret = fdt_setprop(blob, nodeoffset, "model", module_name, len);
+	if (ret < 0)
+	printf("ft_blob_update(): cannot set /model property err:%s\n",
+		fdt_strerror(ret));
+}
+#endif /* CONFIG_OF_BOARD_SETUP */
+
+
+/*
+ * Read HW ID from I2C EEPROM and detect the modue we are running on. Note
+ * that we need to use local variable for readout, because global data is not
+ * writable yet (and we'll have to redo the readout later on).
+ */
+int checkboard(void)
+{
+	hw_id_t hw_id_tmp;
+	char module_name_tmp[MODULE_NAME_MAXLEN] = "";
+
+	read_hw_id(hw_id_tmp);
+	identify_module(hw_id_tmp);	/* this sets gd->board_type */
+	compose_module_name(hw_id_tmp, module_name_tmp);
+
+	if (gd->board_type != CM5200_UNKNOWN_MODULE)
+		printf("Board: %s\n", module_name_tmp);
+	else
+		printf("Board: unrecognized cm5200 module (%s)\n",
+			module_name_tmp);
+
+	return 0;
+}
+
+
+int board_early_init_r(void)
+{
+	/*
+	 * Now, when we are in RAM, enable flash write access for detection
+	 * process. Note that CS_BOOT cannot be cleared when executing in
+	 * flash.
+	 */
+	*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
+
+	/* Now that we can write to global data, read HW ID again. */
+	read_hw_id(hw_id);
+	return 0;
+}
+
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+#if defined(CONFIG_SYS_I2C_SOFT)
+	uchar buf[6];
+	char str[18];
+	char hostname[MODULE_NAME_MAXLEN];
+
+	/* Read ethaddr from EEPROM */
+	if (i2c_read(CONFIG_SYS_I2C_EEPROM, CONFIG_MAC_OFFSET, 2, buf, 6) == 0) {
+		sprintf(str, "%02X:%02X:%02X:%02X:%02X:%02X",
+			buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]);
+		/* Check if MAC addr is owned by Schindler */
+		if (strstr(str, "00:06:C3") != str)
+			printf(LOG_PREFIX "Warning - Illegal MAC address (%s)"
+				" in EEPROM.\n", str);
+		else {
+			printf(LOG_PREFIX "Using MAC (%s) from I2C EEPROM\n",
+				str);
+			setenv("ethaddr", str);
+		}
+	} else {
+		printf(LOG_PREFIX "Warning - Unable to read MAC from I2C"
+			" device at address %02X:%04X\n", CONFIG_SYS_I2C_EEPROM,
+			CONFIG_MAC_OFFSET);
+	}
+	hostname[0] = 0x00;
+	/* set the hostname appropriate to the module we're running on */
+	compose_hostname(hw_id, hostname);
+	setenv("hostname", hostname);
+
+#endif /* defined(CONFIG_SYS_I2C_SOFT) */
+	if (!getenv("ethaddr"))
+		printf(LOG_PREFIX "MAC address not set, networking is not "
+					"operational\n");
+
+	return 0;
+}
+#endif /* CONFIG_MISC_INIT_R */
+
+
+#ifdef CONFIG_LAST_STAGE_INIT
+int last_stage_init(void)
+{
+#ifdef CONFIG_USB_STORAGE
+	cm5200_fwupdate();
+#endif /* CONFIG_USB_STORAGE */
+	return 0;
+}
+#endif /* CONFIG_LAST_STAGE_INIT */
+
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, bd_t *bd)
+{
+	ft_cpu_setup(blob, bd);
+	ft_blob_update(blob, bd);
+
+	return 0;
+}
+#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/cm5200/cm5200.h b/board/cm5200/cm5200.h
new file mode 100644
index 0000000000..c2573f3bf6
--- /dev/null
+++ b/board/cm5200/cm5200.h
@@ -0,0 +1,171 @@ 
+/*
+ * (C) Copyright 2007 DENX Software Engineering
+ *
+ * Author: Bartlomiej Sieka <tur@semihalf.com>
+ * Author: Grzegorz Bernacki <gjb@semihalf.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _CM5200_H
+#define _CM5200_H
+
+
+/*
+ * Definitions and declarations for the modules of the cm5200 platform. Mostly
+ * related to reading the hardware identification data (HW ID) from the I2C
+ * EEPROM, detection of the particular module we are executing on, and
+ * appropriate SDRAM controller initialization.
+ */
+
+
+#define CM5200_UNKNOWN_MODULE	0xffffffff
+
+enum {
+	DEVICE_NAME,		/* 0 */
+	GENERATION,		/* 1 */
+	PCB_NAME,		/* 2 */
+	FORM,			/* 3 */
+	VERSION,		/* 4 */
+	IDENTIFICATION_NUMBER,	/* 5 */
+	MAJOR_SW_VERSION,	/* 6 */
+	MINOR_SW_VERSION,	/* 7 */
+	/* add new alements above this line */
+	HW_ID_ELEM_COUNT	/* count */
+};
+
+/*
+ * Sect. 4.1 "CM1.Q/CMU1.Q Supervisory Microcontroller Interface Definition"
+ */
+
+#define DEVICE_NAME_OFFSET		0x02
+#define GENERATION_OFFSET		0x0b
+#define PCB_NAME_OFFSET			0x0c
+#define FORM_OFFSET			0x15
+#define VERSION_OFFSET			0x16
+#define IDENTIFICATION_NUMBER_OFFSET	0x19
+#define MAJOR_SW_VERSION_OFFSET		0x0480
+#define MINOR_SW_VERSION_OFFSET		0x0481
+
+
+#define DEVICE_NAME_LEN			0x09
+#define GENERATION_LEN			0x01
+#define PCB_NAME_LEN			0x09
+#define FORM_LEN			0x01
+#define VERSION_LEN			0x03
+#define IDENTIFICATION_NUMBER_LEN	0x09
+#define MAJOR_SW_VERSION_LEN		0x01
+#define MINOR_SW_VERSION_LEN		0x01
+
+#define HW_ID_ELEM_MAXLEN		0x09	/* MAX(XXX_LEN) */
+
+/* entire HW ID in EEPROM is 64 bytes, so longer module name is unlikely */
+#define MODULE_NAME_MAXLEN		64
+
+
+/* storage for HW ID read from EEPROM */
+typedef char hw_id_t[HW_ID_ELEM_COUNT][HW_ID_ELEM_MAXLEN];
+
+
+/* HW ID layout in EEPROM */
+static struct {
+	unsigned int offset;
+	unsigned int length;
+} hw_id_format[HW_ID_ELEM_COUNT] = {
+	{DEVICE_NAME_OFFSET,		DEVICE_NAME_LEN},
+	{GENERATION_OFFSET,		GENERATION_LEN},
+	{PCB_NAME_OFFSET,		PCB_NAME_LEN},
+	{FORM_OFFSET,			FORM_LEN},
+	{VERSION_OFFSET,		VERSION_LEN},
+	{IDENTIFICATION_NUMBER_OFFSET,	IDENTIFICATION_NUMBER_LEN},
+	{MAJOR_SW_VERSION_OFFSET,	MAJOR_SW_VERSION_LEN},
+	{MINOR_SW_VERSION_OFFSET,	MINOR_SW_VERSION_LEN},
+};
+
+
+/* HW ID data found in EEPROM on supported modules */
+static char *cm1_qa_hw_id[HW_ID_ELEM_COUNT] = {
+	"CM",		/* DEVICE_NAME */
+	"1",		/* GENERATION */
+	"CM1",		/* PCB_NAME */
+	"Q",		/* FORM */
+	"A",		/* VERSION */
+	"591881",	/* IDENTIFICATION_NUMBER */
+	"",		/* MAJOR_SW_VERSION */
+	"",		/* MINOR_SW_VERSION */
+};
+
+static char *cm11_qa_hw_id[HW_ID_ELEM_COUNT] = {
+	"CM",		/* DEVICE_NAME */
+	"1",		/* GENERATION */
+	"CM11",		/* PCB_NAME */
+	"Q",		/* FORM */
+	"A",		/* VERSION */
+	"594200",	/* IDENTIFICATION_NUMBER */
+	"",		/* MAJOR_SW_VERSION */
+	"",		/* MINOR_SW_VERSION */
+};
+
+static char *cmu1_qa_hw_id[HW_ID_ELEM_COUNT] = {
+	"CMU",		/* DEVICE_NAME */
+	"1",		/* GENERATION */
+	"CMU1",		/* PCB_NAME */
+	"Q",		/* FORM */
+	"A",		/* VERSION */
+	"594128",	/* IDENTIFICATION_NUMBER */
+	"",		/* MAJOR_SW_VERSION */
+	"",		/* MINOR_SW_VERSION */
+};
+
+
+/* list of known modules */
+static char **hw_id_list[] = {
+	cm1_qa_hw_id,
+	cm11_qa_hw_id,
+	cmu1_qa_hw_id,
+};
+
+/* indices to the above list - keep in sync */
+enum {
+	CM1_QA,
+	CM11_QA,
+	CMU1_QA,
+};
+
+
+/* identify modules based on these hw id elements */
+static int hw_id_identify[] = {
+	PCB_NAME,
+	FORM,
+	VERSION,
+};
+
+
+/* Registers' settings for SDRAM controller intialization */
+typedef struct {
+	ulong mode;
+	ulong control;
+	ulong config1;
+	ulong config2;
+} mem_conf_t;
+
+static mem_conf_t k4s561632E = {
+	0x00CD0000,      /* CASL 3, burst length 8 */
+	0x514F0000,
+	0xE2333900,
+	0x8EE70000
+};
+
+static mem_conf_t mt48lc32m16a2 = {
+	0x00CD0000,      /* CASL 3, burst length 8 */
+	0x514F0000,
+	0xD2322800,
+	0x8AD70000
+};
+
+static mem_conf_t* memory_config[] = {
+	&k4s561632E,
+	&mt48lc32m16a2
+};
+
+#endif /* _CM5200_H */
diff --git a/board/cm5200/cmd_cm5200.c b/board/cm5200/cmd_cm5200.c
new file mode 100644
index 0000000000..60097dc8c7
--- /dev/null
+++ b/board/cm5200/cmd_cm5200.c
@@ -0,0 +1,402 @@ 
+/*
+ * (C) Copyright 2007 Markus Kappeler <markus.kappeler@objectxp.com>
+ *
+ * Adapted for U-Boot 1.2 by Piotr Kruszynski <ppk@semihalf.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <i2c.h>
+#include <usb.h>
+
+#ifdef CONFIG_CMD_BSP
+
+static int do_usb_test(char * const argv[])
+{
+	int i;
+	static int usb_stor_curr_dev = -1; /* current device */
+
+	printf("Starting USB Test\n"
+		"Please insert USB Memmory Stick\n\n"
+		"Please press any key to start\n\n");
+	getc();
+
+	usb_stop();
+	printf("(Re)start USB...\n");
+	i = usb_init();
+#ifdef CONFIG_USB_STORAGE
+		/* try to recognize storage devices immediately */
+		if (i >= 0)
+			usb_stor_curr_dev = usb_stor_scan(1);
+#endif /* CONFIG_USB_STORAGE */
+	if (usb_stor_curr_dev >= 0)
+		printf("Found USB Storage Dev continue with Test...\n");
+	else {
+		printf("No USB Storage Device detected.. Stop Test\n");
+		return 1;
+	}
+
+	usb_stor_info();
+
+	printf("stopping USB..\n");
+	usb_stop();
+
+	return 0;
+}
+
+static int do_led_test(char * const argv[])
+{
+	int i = 0;
+	struct mpc5xxx_gpt_0_7 *gpt = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT;
+
+	printf("Starting LED Test\n"
+		"Please set Switch S500 all off\n\n"
+		"Please press any key to start\n\n");
+	getc();
+
+	/* configure timer 2-3 for simple GPIO output High */
+	gpt->gpt2.emsr |= 0x00000034;
+	gpt->gpt3.emsr |= 0x00000034;
+
+	(*(vu_long *)MPC5XXX_WU_GPIO_ENABLE) |= 0x80000000;
+	(*(vu_long *)MPC5XXX_WU_GPIO_DIR) |= 0x80000000;
+	printf("Please press any key to stop\n\n");
+	while (!tstc()) {
+		if (i == 1) {
+			(*(vu_long *)MPC5XXX_WU_GPIO_DATA_O) |= 0x80000000;
+			gpt->gpt2.emsr &= ~0x00000010;
+			gpt->gpt3.emsr &= ~0x00000010;
+		} else if (i == 2) {
+			(*(vu_long *)MPC5XXX_WU_GPIO_DATA_O) &= ~0x80000000;
+			gpt->gpt2.emsr &= ~0x00000010;
+			gpt->gpt3.emsr |= 0x00000010;
+		} else if (i >= 3) {
+			(*(vu_long *)MPC5XXX_WU_GPIO_DATA_O) &= ~0x80000000;
+			gpt->gpt3.emsr &= ~0x00000010;
+			gpt->gpt2.emsr |= 0x00000010;
+			i = 0;
+		}
+		i++;
+		udelay(200000);
+	}
+	getc();
+
+	(*(vu_long *)MPC5XXX_WU_GPIO_DATA_O) |= 0x80000000;
+	gpt->gpt2.emsr |= 0x00000010;
+	gpt->gpt3.emsr |= 0x00000010;
+
+	return 0;
+}
+
+static int do_rs232_test(char * const argv[])
+{
+	int error_status = 0;
+	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
+	struct mpc5xxx_psc *psc1 = (struct mpc5xxx_psc *)MPC5XXX_PSC1;
+
+	/* Configure PSC 2-3-6 as GPIO */
+	gpio->port_config &= 0xFF0FF80F;
+
+	switch (simple_strtoul(argv[2], NULL, 10)) {
+	case 1:
+		/* check RTS <-> CTS loop */
+		/* set rts to 0 */
+		printf("Uart 1 test: RX TX tested by using U-Boot\n"
+			"Please connect RTS with CTS on Uart1 plug\n\n"
+			"Press any key to start\n\n");
+		getc();
+
+		psc1->op1 |= 0x01;
+
+		/* wait some time before requesting status */
+		udelay(10);
+
+		/* check status at cts */
+		if ((psc1->ip & 0x01) != 0) {
+			error_status = 3;
+			printf("%s: failure at rs232_1, cts status is %d "
+				"(should be 0)\n",
+				__FUNCTION__, (psc1->ip & 0x01));
+		}
+
+		/* set rts to 1 */
+		psc1->op0 |= 0x01;
+
+		/* wait some time before requesting status */
+		udelay(10);
+
+		/* check status at cts */
+		if ((psc1->ip & 0x01) != 1) {
+			error_status = 3;
+			printf("%s: failure at rs232_1, cts status is %d "
+				"(should be 1)\n",
+				__FUNCTION__, (psc1->ip & 0x01));
+		}
+		break;
+	case 2:
+		/* set PSC2_0, PSC2_2 as output and PSC2_1, PSC2_3 as input */
+		printf("Uart 2 test: Please use RS232 Loopback plug on UART2\n"
+			"\nPress any key to start\n\n");
+		getc();
+
+		gpio->simple_gpioe &= ~(0x000000F0);
+		gpio->simple_gpioe |= 0x000000F0;
+		gpio->simple_ddr &= ~(0x000000F0);
+		gpio->simple_ddr |= 0x00000050;
+
+		/* check TXD <-> RXD loop */
+		/* set TXD to 1 */
+		gpio->simple_dvo |= (1 << 4);
+
+		/* wait some time before requesting status */
+		udelay(10);
+
+		if ((gpio->simple_ival & 0x00000020) != 0x00000020) {
+			error_status = 2;
+			printf("%s: failure at rs232_2, rxd status is %d "
+				"(should be 1)\n", __FUNCTION__,
+				(gpio->simple_ival & 0x00000020) >> 5);
+		}
+
+		/* set TXD to 0 */
+		gpio->simple_dvo &= ~(1 << 4);
+
+		/* wait some time before requesting status */
+		udelay(10);
+
+		if ((gpio->simple_ival & 0x00000020) != 0x00000000) {
+			error_status = 2;
+			printf("%s: failure at rs232_2, rxd status is %d "
+				"(should be 0)\n", __FUNCTION__,
+				(gpio->simple_ival & 0x00000020) >> 5);
+		}
+
+		/* check RTS <-> CTS loop */
+		/* set RTS to 1 */
+		gpio->simple_dvo |= (1 << 6);
+
+		/* wait some time before requesting status */
+		udelay(10);
+
+		if ((gpio->simple_ival & 0x00000080) != 0x00000080) {
+			error_status = 3;
+			printf("%s: failure at rs232_2, cts status is %d "
+				"(should be 1)\n", __FUNCTION__,
+				(gpio->simple_ival & 0x00000080) >> 7);
+		}
+
+		/* set RTS to 0 */
+		gpio->simple_dvo &= ~(1 << 6);
+
+		/* wait some time before requesting status */
+		udelay(10);
+
+		if ((gpio->simple_ival & 0x00000080) != 0x00000000) {
+			error_status = 3;
+			printf("%s: failure at rs232_2, cts status is %d "
+				"(should be 0)\n", __FUNCTION__,
+				(gpio->simple_ival & 0x00000080) >> 7);
+		}
+		break;
+	case 3:
+		/* set PSC3_0, PSC3_2 as output and PSC3_1, PSC3_3 as input */
+		printf("Uart 3 test: Please use RS232 Loopback plug on UART2\n"
+			"\nPress any key to start\n\n");
+		getc();
+
+		gpio->simple_gpioe &= ~(0x00000F00);
+		gpio->simple_gpioe |= 0x00000F00;
+
+		gpio->simple_ddr &= ~(0x00000F00);
+		gpio->simple_ddr |= 0x00000500;
+
+		/* check TXD <-> RXD loop */
+		/* set TXD to 1 */
+		gpio->simple_dvo |= (1 << 8);
+
+		/* wait some time before requesting status */
+		udelay(10);
+
+		if ((gpio->simple_ival & 0x00000200) != 0x00000200) {
+			error_status = 2;
+			printf("%s: failure at rs232_3, rxd status is %d "
+				"(should be 1)\n", __FUNCTION__,
+				(gpio->simple_ival & 0x00000200) >> 9);
+		}
+
+		/* set TXD to 0 */
+		gpio->simple_dvo &= ~(1 << 8);
+
+		/* wait some time before requesting status */
+		udelay(10);
+
+		if ((gpio->simple_ival & 0x00000200) != 0x00000000) {
+			error_status = 2;
+			printf("%s: failure at rs232_3, rxd status is %d "
+				"(should be 0)\n", __FUNCTION__,
+				(gpio->simple_ival & 0x00000200) >> 9);
+		}
+
+		/* check RTS <-> CTS loop */
+		/* set RTS to 1 */
+		gpio->simple_dvo |= (1 << 10);
+
+		/* wait some time before requesting status */
+		udelay(10);
+
+		if ((gpio->simple_ival & 0x00000800) != 0x00000800) {
+			error_status = 3;
+			printf("%s: failure at rs232_3, cts status is %d "
+				"(should be 1)\n", __FUNCTION__,
+				(gpio->simple_ival & 0x00000800) >> 11);
+		}
+
+		/* set RTS to 0 */
+		gpio->simple_dvo &= ~(1 << 10);
+
+		/* wait some time before requesting status */
+		udelay(10);
+
+		if ((gpio->simple_ival & 0x00000800) != 0x00000000) {
+			error_status = 3;
+			printf("%s: failure at rs232_3, cts status is %d "
+				"(should be 0)\n", __FUNCTION__,
+				(gpio->simple_ival & 0x00000800) >> 11);
+		}
+		break;
+	case 4:
+		/* set PSC6_2, PSC6_3 as output and PSC6_0, PSC6_1 as input */
+		printf("Uart 4 test: Please use RS232 Loopback plug on UART2\n"
+			"\nPress any key to start\n\n");
+		getc();
+
+		gpio->simple_gpioe &= ~(0xF0000000);
+		gpio->simple_gpioe |= 0x30000000;
+
+		gpio->simple_ddr &= ~(0xf0000000);
+		gpio->simple_ddr |= 0x30000000;
+
+		(*(vu_long *)MPC5XXX_WU_GPIO_ENABLE) |= 0x30000000;
+		(*(vu_long *)MPC5XXX_WU_GPIO_DIR) &= ~(0x30000000);
+
+		/* check TXD <-> RXD loop */
+		/* set TXD to 1 */
+		gpio->simple_dvo |= (1 << 28);
+
+		/* wait some time before requesting status */
+		udelay(10);
+
+		if (((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) & 0x10000000) !=
+				0x10000000) {
+			error_status = 2;
+			printf("%s: failure at rs232_4, rxd status is %lu "
+				"(should be 1)\n", __FUNCTION__,
+				((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) &
+					0x10000000) >> 28);
+		}
+
+		/* set TXD to 0 */
+		gpio->simple_dvo &= ~(1 << 28);
+
+		/* wait some time before requesting status */
+		udelay(10);
+
+		if (((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) & 0x10000000) !=
+				0x00000000) {
+			error_status = 2;
+			printf("%s: failure at rs232_4, rxd status is %lu "
+				"(should be 0)\n", __FUNCTION__,
+				((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) &
+					0x10000000) >> 28);
+		}
+
+		/* check RTS <-> CTS loop */
+		/* set RTS to 1 */
+		gpio->simple_dvo |= (1 << 29);
+
+		/* wait some time before requesting status */
+		udelay(10);
+
+		if (((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) & 0x20000000) !=
+				0x20000000) {
+			error_status = 3;
+			printf("%s: failure at rs232_4, cts status is %lu "
+				"(should be 1)\n", __FUNCTION__,
+				((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) &
+					0x20000000) >> 29);
+		}
+
+		/* set RTS to 0 */
+		gpio->simple_dvo &= ~(1 << 29);
+
+		/* wait some time before requesting status */
+		udelay(10);
+
+		if (((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) & 0x20000000) !=
+				0x00000000) {
+			error_status = 3;
+			printf("%s: failure at rs232_4, cts status is %lu "
+				"(should be 0)\n", __FUNCTION__,
+				((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) &
+					0x20000000) >> 29);
+		}
+		break;
+	default:
+		printf("%s: invalid rs232 number %s\n", __FUNCTION__, argv[2]);
+		error_status = 1;
+		break;
+	}
+	gpio->port_config |= (CONFIG_SYS_GPS_PORT_CONFIG & 0xFF0FF80F);
+
+	return error_status;
+}
+
+static int cmd_fkt(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	int rcode = -1;
+
+	switch (argc) {
+	case 2:
+		if (strncmp(argv[1], "led", 3) == 0)
+			rcode = do_led_test(argv);
+		else if (strncmp(argv[1], "usb", 3) == 0)
+			rcode = do_usb_test(argv);
+		break;
+	case 3:
+		if (strncmp(argv[1], "rs232", 3) == 0)
+			rcode = do_rs232_test(argv);
+		break;
+	}
+
+	switch (rcode) {
+	case -1:
+		printf("Usage:\n"
+			"fkt { i2c | led | usb }\n"
+			"fkt rs232 number\n");
+		rcode = 1;
+		break;
+	case 0:
+		printf("Test passed\n");
+		break;
+	default:
+		printf("Test failed with code: %d\n", rcode);
+	}
+
+	return rcode;
+}
+
+U_BOOT_CMD(
+	fkt,	4,	1,	cmd_fkt,
+	"Function test routines",
+	"i2c\n"
+	"     - Test I2C communication\n"
+	"fkt led\n"
+	"     - Test LEDs\n"
+	"fkt rs232 number\n"
+	"     - Test RS232 (loopback plug(s) for RS232 required)\n"
+	"fkt usb\n"
+	"     - Test USB communication"
+);
+#endif /* CONFIG_CMD_BSP */
diff --git a/board/cm5200/fwupdate.c b/board/cm5200/fwupdate.c
new file mode 100644
index 0000000000..4740c8394c
--- /dev/null
+++ b/board/cm5200/fwupdate.c
@@ -0,0 +1,181 @@ 
+/*
+ * (C) Copyright 2007 Schindler Lift Inc.
+ * (C) Copyright 2007 DENX Software Engineering
+ *
+ * Author: Michel Marti <mma@objectxp.com>
+ * Adapted for U-Boot 1.2 by Piotr Kruszynski <ppk@semihalf.com>:
+ *   - code clean-up
+ *   - bugfix for overwriting bootargs by user
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <fat.h>
+#include <malloc.h>
+#include <image.h>
+#include <usb.h>
+#include <fat.h>
+
+#include "fwupdate.h"
+
+static int load_rescue_image(ulong);
+
+void cm5200_fwupdate(void)
+{
+	cmd_tbl_t *bcmd;
+	char *rsargs;
+	char *tmp = NULL;
+	char ka[16];
+	char * const argv[3] = { "bootm", ka, NULL };
+
+	/* Check if rescue system is disabled... */
+	if (getenv("norescue")) {
+		printf(LOG_PREFIX "Rescue System disabled.\n");
+		return;
+	}
+
+	/* Check if we have a USB storage device and load image */
+	if (load_rescue_image(LOAD_ADDR))
+		return;
+
+	bcmd = find_cmd("bootm");
+	if (!bcmd)
+		return;
+
+	sprintf(ka, "%lx", (ulong)LOAD_ADDR);
+
+	/* prepare our bootargs */
+	rsargs = getenv("rs-args");
+	if (!rsargs)
+		rsargs = RS_BOOTARGS;
+	else {
+		tmp = malloc(strlen(rsargs+1));
+		if (!tmp) {
+			printf(LOG_PREFIX "Memory allocation failed\n");
+			return;
+		}
+		strcpy(tmp, rsargs);
+		rsargs = tmp;
+	}
+
+	setenv("bootargs", rsargs);
+
+	if (rsargs == tmp)
+		free(rsargs);
+
+	printf(LOG_PREFIX "Starting update system (bootargs=%s)...\n", rsargs);
+	do_bootm(bcmd, 0, 2, argv);
+}
+
+static int load_rescue_image(ulong addr)
+{
+	disk_partition_t info;
+	int devno;
+	int partno;
+	int i;
+	char fwdir[64];
+	char nxri[128];
+	char *tmp;
+	char dev[7];
+	char addr_str[16];
+	char * const argv[6] = { "fatload", "usb", dev, addr_str, nxri, NULL };
+	struct blk_desc *stor_dev = NULL;
+	cmd_tbl_t *bcmd;
+
+	/* Get name of firmware directory */
+	tmp = getenv("fw-dir");
+
+	/* Copy it into fwdir */
+	strncpy(fwdir, tmp ? tmp : FW_DIR, sizeof(fwdir));
+	fwdir[sizeof(fwdir) - 1] = 0; /* Terminate string */
+
+	printf(LOG_PREFIX "Checking for firmware image directory '%s' on USB"
+		" storage...\n", fwdir);
+	usb_stop();
+	if (usb_init() != 0)
+		return 1;
+
+	/* Check for storage device */
+	if (usb_stor_scan(1) != 0) {
+		usb_stop();
+		return 1;
+	}
+
+	/* Detect storage device */
+	for (devno = 0; devno < USB_MAX_STOR_DEV; devno++) {
+		stor_dev = blk_get_devnum_by_type(IF_TYPE_USB, devno);
+		if (stor_dev->type != DEV_TYPE_UNKNOWN)
+			break;
+	}
+	if (!stor_dev || stor_dev->type == DEV_TYPE_UNKNOWN) {
+		printf(LOG_PREFIX "No valid storage device found...\n");
+		usb_stop();
+		return 1;
+	}
+
+	/* Detect partition */
+	for (partno = -1, i = 0; i < 6; i++) {
+		if (part_get_info(stor_dev, i, &info) == 0) {
+			if (fat_register_device(stor_dev, i) == 0) {
+				/* Check if rescue image is present */
+				FW_DEBUG("Looking for firmware directory '%s'"
+					" on partition %d\n", fwdir, i);
+				if (!fat_exists(fwdir)) {
+					FW_DEBUG("No NX rescue image on "
+						"partition %d.\n", i);
+					partno = -2;
+				} else {
+					partno = i;
+					FW_DEBUG("Partition %d contains "
+						"firmware directory\n", partno);
+					break;
+				}
+			}
+		}
+	}
+
+	if (partno < 0) {
+		switch (partno) {
+		case -1:
+			printf(LOG_PREFIX "Error: No valid (FAT) partition "
+				"detected\n");
+			break;
+		case -2:
+			printf(LOG_PREFIX "Error: No NX rescue image on FAT "
+				"partition\n");
+			break;
+		default:
+			printf(LOG_PREFIX "Error: Failed with code %d\n",
+				partno);
+		}
+		usb_stop();
+		return 1;
+	}
+
+	/* Load the rescue image */
+	bcmd = find_cmd("fatload");
+	if (!bcmd) {
+		printf(LOG_PREFIX "Error - 'fatload' command not present.\n");
+		usb_stop();
+		return 1;
+	}
+
+	tmp = getenv("nx-rescue-image");
+	sprintf(nxri, "%s/%s", fwdir, tmp ? tmp : RESCUE_IMAGE);
+	sprintf(dev, "%d:%d", devno, partno);
+	sprintf(addr_str, "%lx", addr);
+
+	FW_DEBUG("fat_fsload device='%s', addr='%s', file: %s\n",
+		dev, addr_str, nxri);
+
+	if (do_fat_fsload(bcmd, 0, 5, argv) != 0) {
+		usb_stop();
+		return 1;
+	}
+
+	/* Stop USB */
+	usb_stop();
+	return 0;
+}
diff --git a/board/cm5200/fwupdate.h b/board/cm5200/fwupdate.h
new file mode 100644
index 0000000000..6ddf0bac35
--- /dev/null
+++ b/board/cm5200/fwupdate.h
@@ -0,0 +1,31 @@ 
+/*
+ * (C) Copyright 2007 Schindler Lift Inc.
+ *
+ * Author: Michel Marti <mma@objectxp.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __FW_UPDATE_H
+#define __FW_UPDATE_H
+
+/* Default prefix for output messages */
+#define LOG_PREFIX	"CM5200:"
+
+/* Extra debug macro */
+#ifdef CONFIG_FWUPDATE_DEBUG
+#define FW_DEBUG(fmt...) printf(LOG_PREFIX fmt)
+#else
+#define FW_DEBUG(fmt...)
+#endif
+
+/* Name of the directory holding firmware images */
+#define FW_DIR		"nx-fw"
+#define RESCUE_IMAGE	"nxrs.img"
+#define LOAD_ADDR	0x400000
+#define RS_BOOTARGS	"ramdisk_size=8192K"
+
+/* Main function for fwupdate */
+void cm5200_fwupdate(void);
+
+#endif /* __FW_UPDATE_H */
diff --git a/board/davedenx/aria/Kconfig b/board/davedenx/aria/Kconfig
new file mode 100644
index 0000000000..54a86b9e13
--- /dev/null
+++ b/board/davedenx/aria/Kconfig
@@ -0,0 +1,12 @@ 
+if TARGET_ARIA
+
+config SYS_BOARD
+	default "aria"
+
+config SYS_VENDOR
+	default "davedenx"
+
+config SYS_CONFIG_NAME
+	default "aria"
+
+endif
diff --git a/board/davedenx/aria/MAINTAINERS b/board/davedenx/aria/MAINTAINERS
new file mode 100644
index 0000000000..a6152c985a
--- /dev/null
+++ b/board/davedenx/aria/MAINTAINERS
@@ -0,0 +1,6 @@ 
+ARIA BOARD
+M:	Wolfgang Denk <wd@denx.de>
+S:	Maintained
+F:	board/davedenx/aria/
+F:	include/configs/aria.h
+F:	configs/aria_defconfig
diff --git a/board/davedenx/aria/Makefile b/board/davedenx/aria/Makefile
new file mode 100644
index 0000000000..dd38b7f389
--- /dev/null
+++ b/board/davedenx/aria/Makefile
@@ -0,0 +1,7 @@ 
+#
+# (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	:= aria.o
diff --git a/board/davedenx/aria/aria.c b/board/davedenx/aria/aria.c
new file mode 100644
index 0000000000..e389819e9d
--- /dev/null
+++ b/board/davedenx/aria/aria.c
@@ -0,0 +1,115 @@ 
+/*
+ * (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
+ * (C) Copyright 2009 Dave Srl www.dave.eu
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/bitops.h>
+#include <command.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+#include <asm/mpc512x.h>
+#include <fdt_support.h>
+#ifdef CONFIG_MISC_INIT_R
+#include <i2c.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+	gd->ram_size = fixed_sdram(NULL, NULL, 0);
+
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	u32 tmp;
+
+	tmp = in_be32((u32*)CONFIG_SYS_ARIA_FPGA_BASE);
+	printf("FPGA:  %u-%u.%u.%u\n",
+		(tmp & 0xFF000000) >> 24,
+		(tmp & 0x00FF0000) >> 16,
+		(tmp & 0x0000FF00) >>  8,
+		 tmp & 0x000000FF
+	);
+
+	return 0;
+}
+
+static  iopin_t ioregs_init[] = {
+	/*
+	 * FEC
+	 */
+
+	/* FEC on PSCx_x*/
+	{
+		offsetof(struct ioctrl512x, io_control_psc0_0), 5, 0,
+		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+	{
+		offsetof(struct ioctrl512x, io_control_psc1_0), 10, 0,
+		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+	{
+		offsetof(struct ioctrl512x, io_control_spdif_txclk), 3, 0,
+		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+
+	/*
+	 * DIU
+	 */
+	/* FUNC2=DIU CLK */
+	{
+		offsetof(struct ioctrl512x, io_control_psc6_0), 1, 0,
+		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
+	},
+	/* FUNC2=DIU_HSYNC */
+	{
+		offsetof(struct ioctrl512x, io_control_psc6_1), 1, 0,
+		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+	/* FUNC2=DIUVSYNC Sets Next 26 to DIU Pads */
+	{
+		offsetof(struct ioctrl512x, io_control_psc6_4), 26, 0,
+		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+	/*
+	 * On board SRAM
+	 */
+	/* FUNC2=/LPC CS6 */
+	{
+		offsetof(struct ioctrl512x, io_control_j1850_rx), 1, 0,
+		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(1) | IO_PIN_ST(1) | IO_PIN_DS(3)
+	},
+};
+
+int checkboard (void)
+{
+	puts("Board: ARIA\n");
+
+	/* initialize function mux & slew rate IO inter alia on IO Pins  */
+
+	iopin_initialize(ioregs_init, ARRAY_SIZE(ioregs_init));
+
+	return 0;
+}
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, bd_t *bd)
+{
+	ft_cpu_setup(blob, bd);
+
+	return 0;
+}
+#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/esd/mecp5123/Kconfig b/board/esd/mecp5123/Kconfig
new file mode 100644
index 0000000000..3f2a411196
--- /dev/null
+++ b/board/esd/mecp5123/Kconfig
@@ -0,0 +1,12 @@ 
+if TARGET_MECP5123
+
+config SYS_BOARD
+	default "mecp5123"
+
+config SYS_VENDOR
+	default "esd"
+
+config SYS_CONFIG_NAME
+	default "mecp5123"
+
+endif
diff --git a/board/esd/mecp5123/MAINTAINERS b/board/esd/mecp5123/MAINTAINERS
new file mode 100644
index 0000000000..ae5fcead90
--- /dev/null
+++ b/board/esd/mecp5123/MAINTAINERS
@@ -0,0 +1,6 @@ 
+MECP5123 BOARD
+M:	Reinhard Arlt <reinhard.arlt@esd-electronics.com>
+S:	Maintained
+F:	board/esd/mecp5123/
+F:	include/configs/mecp5123.h
+F:	configs/mecp5123_defconfig
diff --git a/board/esd/mecp5123/Makefile b/board/esd/mecp5123/Makefile
new file mode 100644
index 0000000000..f5ebb0144f
--- /dev/null
+++ b/board/esd/mecp5123/Makefile
@@ -0,0 +1,7 @@ 
+#
+# (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	:= mecp5123.o
diff --git a/board/esd/mecp5123/mecp5123.c b/board/esd/mecp5123/mecp5123.c
new file mode 100644
index 0000000000..78a6b66110
--- /dev/null
+++ b/board/esd/mecp5123/mecp5123.c
@@ -0,0 +1,200 @@ 
+/*
+ * (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
+ * (C) Copyright 2009 Dave Srl www.dave.eu
+ * (C) Copyright 2009 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/bitops.h>
+#include <command.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+#include <asm/mpc512x.h>
+#include <fdt_support.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int eeprom_write_enable(unsigned dev_addr, int state)
+{
+	return -ENOSYS;
+}
+
+int board_early_init_f(void)
+{
+	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+	int i;
+
+	/*
+	 * Initialize Local Window for boot access
+	 */
+	out_be32(&im->sysconf.lpbaw,
+		 CSAW_START(0xffb00000) | CSAW_STOP(0xffb00000, 0x00010000));
+	sync_law(&im->sysconf.lpbaw);
+
+	/*
+	 * Configure MSCAN clocks
+	 */
+	for (i=0; i<4; ++i) {
+		out_be32(&im->clk.msccr[i], 0x00300000);
+		out_be32(&im->clk.msccr[i], 0x00310000);
+	}
+
+	/*
+	 * Configure GPIO's
+	 */
+	clrbits_be32(&im->gpio.gpodr, 0x000000e0);
+	clrbits_be32(&im->gpio.gpdir, 0x00ef0000);
+	setbits_be32(&im->gpio.gpdir, 0x001000e0);
+	setbits_be32(&im->gpio.gpdat, 0x00100000);
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size(0, fixed_sdram(NULL, NULL, 0));
+
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+	u32 val;
+
+	/*
+	 * Optimize access to profibus chip (VPC3) on the local bus
+	 */
+
+	/*
+	 * Select 1:1 for LPC_DIV
+	 */
+	val = in_be32(&im->clk.scfr[0]) & ~SCFR1_LPC_DIV_MASK;
+	out_be32(&im->clk.scfr[0], val | (0x1 << SCFR1_LPC_DIV_SHIFT));
+
+	/*
+	 * Configure LPC Chips Select Deadcycle Control Register
+	 * CS0 - device can drive data 2 clock cycle(s) after CS deassertion
+	 * CS1 - device can drive data 1 clock cycle(s) after CS deassertion
+	 */
+	clrbits_be32(&im->lpc.cs_dccr, 0x000000ff);
+	setbits_be32(&im->lpc.cs_dccr, (0x00 << 4) | (0x01 << 0));
+
+	/*
+	 * Configure LPC Chips Select Holdcycle Control Register
+	 * CS0 - data is valid 2 clock cycle(s) after CS deassertion
+	 * CS1 - data is valid 1 clock cycle(s) after CS deassertion
+	 */
+	clrbits_be32(&im->lpc.cs_hccr, 0x000000ff);
+	setbits_be32(&im->lpc.cs_hccr, (0x00 << 4) | (0x01 << 0));
+
+	return 0;
+}
+
+static iopin_t ioregs_init[] = {
+	/* FUNC1=FEC_RX_DV Sets Next 3 to FEC pads */
+	{
+		offsetof(struct ioctrl512x, io_control_spdif_txclk), 3, 0,
+		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+	/* FUNC1=FEC_COL Sets Next 15 to FEC pads */
+	{
+		offsetof(struct ioctrl512x, io_control_psc0_0), 15, 0,
+		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+	/* FUNC1=SELECT LPC_CS1 */
+	{
+		offsetof(struct ioctrl512x, io_control_lpc_cs1), 1, 0,
+		IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+	/* FUNC3=SELECT PSC5_2 */
+	{
+		offsetof(struct ioctrl512x, io_control_psc5_2), 1, 0,
+		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+	/* FUNC3=SELECT PSC5_3 */
+	{
+		offsetof(struct ioctrl512x, io_control_psc5_3), 1, 0,
+		IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+	/* FUNC3=SELECT PSC7_3 */
+	{
+		offsetof(struct ioctrl512x, io_control_psc7_3), 1, 0,
+		IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+	/* FUNC3=SELECT PSC9_0 */
+	{
+		offsetof(struct ioctrl512x, io_control_psc9_0), 3, 0,
+		IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+	/* FUNC3=SELECT PSC10_0 */
+	{
+		offsetof(struct ioctrl512x, io_control_psc10_0), 3, 0,
+		IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+	/* FUNC3=SELECT PSC10_3 */
+	{
+		offsetof(struct ioctrl512x, io_control_psc10_3), 1, 0,
+		IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+	/* FUNC3=SELECT PSC11_0 */
+	{
+		offsetof(struct ioctrl512x, io_control_psc11_0), 4, 0,
+		IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+	/* FUNC0=SELECT IRQ0 */
+	{
+		offsetof(struct ioctrl512x, io_control_irq0), 4, 0,
+		IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	}
+};
+
+static iopin_t rev2_silicon_pci_ioregs_init[] = {
+	/* FUNC0=PCI Sets next 54 to PCI pads */
+	{
+		offsetof(struct ioctrl512x, io_control_pci_ad31), 54, 0,
+		IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_DS(0)
+	}
+};
+
+int checkboard(void)
+{
+	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+	u32 spridr;
+
+	puts("Board: MECP_5123\n");
+
+	/*
+	 * Initialize function mux & slew rate IO inter alia on IO
+	 * Pins
+	 */
+	iopin_initialize(ioregs_init, ARRAY_SIZE(ioregs_init));
+
+	spridr = in_be32(&im->sysconf.spridr);
+	if (SVR_MJREV(spridr) >= 2)
+		iopin_initialize(rev2_silicon_pci_ioregs_init, 1);
+
+	return 0;
+}
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, bd_t *bd)
+{
+	ft_cpu_setup(blob, bd);
+
+	return 0;
+}
+#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/freescale/mpc5121ads/Kconfig b/board/freescale/mpc5121ads/Kconfig
new file mode 100644
index 0000000000..f125f9e596
--- /dev/null
+++ b/board/freescale/mpc5121ads/Kconfig
@@ -0,0 +1,12 @@ 
+if TARGET_MPC5121ADS
+
+config SYS_BOARD
+	default "mpc5121ads"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_CONFIG_NAME
+	default "mpc5121ads"
+
+endif
diff --git a/board/freescale/mpc5121ads/MAINTAINERS b/board/freescale/mpc5121ads/MAINTAINERS
new file mode 100644
index 0000000000..d4aab8fb51
--- /dev/null
+++ b/board/freescale/mpc5121ads/MAINTAINERS
@@ -0,0 +1,7 @@ 
+MPC5121ADS BOARD
+#M:	-
+S:	Maintained
+F:	board/freescale/mpc5121ads/
+F:	include/configs/mpc5121ads.h
+F:	configs/mpc5121ads_defconfig
+F:	configs/mpc5121ads_rev2_defconfig
diff --git a/board/freescale/mpc5121ads/Makefile b/board/freescale/mpc5121ads/Makefile
new file mode 100644
index 0000000000..67cf55546b
--- /dev/null
+++ b/board/freescale/mpc5121ads/Makefile
@@ -0,0 +1,8 @@ 
+#
+# (C) Copyright 2007
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	:= mpc5121ads.o
diff --git a/board/freescale/mpc5121ads/README b/board/freescale/mpc5121ads/README
new file mode 100644
index 0000000000..741bc40382
--- /dev/null
+++ b/board/freescale/mpc5121ads/README
@@ -0,0 +1,7 @@ 
+To configure for the current (Rev 3.x) ADS5121
+	make mpc5121ads_config
+This will automatically include PCI, the Real Time CLock, add backup flash
+ability and set the correct frequency and memory configuration.
+
+To configure for the older Rev 2 ADS5121 type (this will not have PCI)
+	make mpc5121ads_rev2_config
diff --git a/board/freescale/mpc5121ads/mpc5121ads.c b/board/freescale/mpc5121ads/mpc5121ads.c
new file mode 100644
index 0000000000..d729056fd0
--- /dev/null
+++ b/board/freescale/mpc5121ads/mpc5121ads.c
@@ -0,0 +1,265 @@ 
+/*
+ * (C) Copyright 2007-2009 DENX Software Engineering
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/bitops.h>
+#include <command.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+#include <asm/mpc512x.h>
+#include <fdt_support.h>
+#ifdef CONFIG_MISC_INIT_R
+#include <i2c.h>
+#endif
+#include <net.h>
+
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void __mpc5121_nfc_select_chip(struct mtd_info *mtd, int chip);
+
+/* Active chip number set in board_nand_select_device() (mpc5121_nfc.c) */
+extern int mpc5121_nfc_chip;
+
+/* Control chips select signal on MPC5121ADS board */
+void mpc5121_nfc_select_chip(struct mtd_info *mtd, int chip)
+{
+	unsigned char *csreg = (u8 *)CONFIG_SYS_CPLD_BASE + 0x09;
+	u8 v;
+
+	v = in_8(csreg);
+	v |= 0x0F;
+
+	if (chip >= 0) {
+		__mpc5121_nfc_select_chip(mtd, 0);
+		v &= ~(1 << mpc5121_nfc_chip);
+	} else {
+		__mpc5121_nfc_select_chip(mtd, -1);
+	}
+
+	out_8(csreg, v);
+}
+
+int board_early_init_f(void)
+{
+	/*
+	 * Disable Boot NOR FLASH write protect - CPLD Reg 8 NOR FLASH Control
+	 *
+	 * Without this the flash identification routine fails, as it needs to issue
+	 * write commands in order to establish the device ID.
+	 */
+
+#ifdef CONFIG_MPC5121ADS_REV2
+	out_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08), 0xC1);
+#else
+	if (in_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08)) & 0x04) {
+		out_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08), 0xC1);
+	} else {
+		/* running from Backup flash */
+		out_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08), 0x32);
+	}
+#endif
+	return 0;
+}
+
+int is_micron(void){
+
+	ushort brd_rev = *(vu_short *)(CONFIG_SYS_CPLD_BASE + 0x00);
+	uchar macaddr[6];
+	u32 brddate, macchk, ismicron;
+
+	/*
+	 * MAC address has serial number with date of manufacture
+	 * Boards made before Nov-08 #1180 use Micron memory;
+	 * 001e59 is the STx vendor #
+	 * Default is Elpida since it works for both but is slightly slower
+	 */
+	ismicron = 0;
+	if (brd_rev >= 0x0400 && eth_getenv_enetaddr("ethaddr", macaddr)) {
+		brddate = (macaddr[3] << 16) + (macaddr[4] << 8) + macaddr[5];
+		macchk = (macaddr[0] << 16) + (macaddr[1] << 8) + macaddr[2];
+		debug("brddate = %d\n\t", brddate);
+
+		if (macchk == 0x001e59 && brddate <= 8111180)
+			ismicron = 1;
+	} else if (brd_rev < 0x400) {
+		ismicron = 1;
+	}
+	debug("Using %s Memory settings\n\t",
+		ismicron ? "Micron" : "Elpida");
+	return(ismicron);
+}
+
+int dram_init(void)
+{
+	u32 msize = 0;
+	/*
+	 * Elpida MDDRC and initialization settings are an alternative
+	 * to the Default Micron ones for all but the earliest Rev 4 boards
+	 */
+	ddr512x_config_t elpida_mddrc_config = {
+		.ddr_sys_config   = CONFIG_SYS_MDDRC_SYS_CFG_ELPIDA,
+		.ddr_time_config0 = CONFIG_SYS_MDDRC_TIME_CFG0,
+		.ddr_time_config1 = CONFIG_SYS_MDDRC_TIME_CFG1_ELPIDA,
+		.ddr_time_config2 = CONFIG_SYS_MDDRC_TIME_CFG2_ELPIDA,
+	};
+
+	u32 elpida_init_sequence[] = {
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_PCHG_ALL,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_RFSH,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_RFSH,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_EM2,
+		CONFIG_SYS_DDRCMD_EM3,
+		CONFIG_SYS_DDRCMD_EN_DLL,
+		CONFIG_SYS_ELPIDA_RES_DLL,
+		CONFIG_SYS_DDRCMD_PCHG_ALL,
+		CONFIG_SYS_DDRCMD_RFSH,
+		CONFIG_SYS_DDRCMD_RFSH,
+		CONFIG_SYS_DDRCMD_RFSH,
+		CONFIG_SYS_ELPIDA_INIT_DEV_OP,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_OCD_DEFAULT,
+		CONFIG_SYS_ELPIDA_OCD_EXIT,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_NOP
+	};
+
+	if (is_micron()) {
+		msize = fixed_sdram(NULL, NULL, 0);
+	} else {
+		msize = fixed_sdram(&elpida_mddrc_config,
+				elpida_init_sequence,
+				sizeof(elpida_init_sequence)/sizeof(u32));
+	}
+
+	gd->ram_size = msize;
+
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	return 0;
+}
+
+static  iopin_t ioregs_init[] = {
+	/* FUNC1=FEC_RX_DV Sets Next 3 to FEC pads */
+	{
+		offsetof(struct ioctrl512x, io_control_spdif_txclk), 3, 0,
+		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+	/* Set highest Slew on 9 PATA pins */
+	{
+		offsetof(struct ioctrl512x, io_control_pata_ce1), 9, 1,
+		IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+	/* FUNC1=FEC_COL Sets Next 15 to FEC pads */
+	{
+		offsetof(struct ioctrl512x, io_control_psc0_0), 15, 0,
+		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+	/* FUNC1=SPDIF_TXCLK */
+	{
+		offsetof(struct ioctrl512x, io_control_lpc_cs1), 1, 0,
+		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
+	},
+	/* FUNC2=SPDIF_TX and sets Next pin to SPDIF_RX */
+	{
+		offsetof(struct ioctrl512x, io_control_i2c1_scl), 2, 0,
+		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
+	},
+	/* FUNC2=DIU CLK */
+	{
+		offsetof(struct ioctrl512x, io_control_psc6_0), 1, 0,
+		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
+	},
+	/* FUNC2=DIU_HSYNC */
+	{
+		offsetof(struct ioctrl512x, io_control_psc6_1), 1, 0,
+		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+	/* FUNC2=DIUVSYNC Sets Next 26 to DIU Pads */
+	{
+		offsetof(struct ioctrl512x, io_control_psc6_4), 26, 0,
+		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	}
+};
+
+static  iopin_t rev2_silicon_pci_ioregs_init[] = {
+	/* FUNC0=PCI Sets next 54 to PCI pads */
+	{
+		offsetof(struct ioctrl512x, io_control_pci_ad31), 54, 0,
+		IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_DS(0)
+	}
+};
+
+int checkboard (void)
+{
+	ushort brd_rev = *(vu_short *) (CONFIG_SYS_CPLD_BASE + 0x00);
+	uchar cpld_rev = *(vu_char *) (CONFIG_SYS_CPLD_BASE + 0x02);
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+	u32 spridr = in_be32(&im->sysconf.spridr);
+
+	printf ("Board: MPC5121ADS rev. 0x%04x (CPLD rev. 0x%02x)\n",
+		brd_rev, cpld_rev);
+
+	/* initialize function mux & slew rate IO inter alia on IO Pins  */
+	iopin_initialize(ioregs_init, ARRAY_SIZE(ioregs_init));
+
+	if (SVR_MJREV (spridr) >= 2)
+		iopin_initialize(rev2_silicon_pci_ioregs_init, 1);
+
+	return 0;
+}
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, bd_t *bd)
+{
+	ft_cpu_setup(blob, bd);
+
+	return 0;
+}
+#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/ifm/ac14xx/Kconfig b/board/ifm/ac14xx/Kconfig
new file mode 100644
index 0000000000..97e80d5ddd
--- /dev/null
+++ b/board/ifm/ac14xx/Kconfig
@@ -0,0 +1,12 @@ 
+if TARGET_AC14XX
+
+config SYS_BOARD
+	default "ac14xx"
+
+config SYS_VENDOR
+	default "ifm"
+
+config SYS_CONFIG_NAME
+	default "ac14xx"
+
+endif
diff --git a/board/ifm/ac14xx/MAINTAINERS b/board/ifm/ac14xx/MAINTAINERS
new file mode 100644
index 0000000000..8fd74e516e
--- /dev/null
+++ b/board/ifm/ac14xx/MAINTAINERS
@@ -0,0 +1,6 @@ 
+AC14XX BOARD
+M:	Anatolij Gustschin <agust@denx.de>
+S:	Maintained
+F:	board/ifm/ac14xx/
+F:	include/configs/ac14xx.h
+F:	configs/ac14xx_defconfig
diff --git a/board/ifm/ac14xx/Makefile b/board/ifm/ac14xx/Makefile
new file mode 100644
index 0000000000..55def60417
--- /dev/null
+++ b/board/ifm/ac14xx/Makefile
@@ -0,0 +1,7 @@ 
+#
+# (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	:= ac14xx.o
diff --git a/board/ifm/ac14xx/ac14xx.c b/board/ifm/ac14xx/ac14xx.c
new file mode 100644
index 0000000000..cd79e804a0
--- /dev/null
+++ b/board/ifm/ac14xx/ac14xx.c
@@ -0,0 +1,569 @@ 
+/*
+ * (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
+ * (C) Copyright 2009 Dave Srl www.dave.eu
+ * (C) Copyright 2010 ifm ecomatic GmbH
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/bitops.h>
+#include <command.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+#include <asm/mpc512x.h>
+#include <fdt_support.h>
+#ifdef CONFIG_MISC_INIT_R
+#include <i2c.h>
+#endif
+
+static int mac_diag;
+static int gpio_diag;
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void gpio_configure(void)
+{
+	immap_t *im;
+	gpio512x_t *gpioregs;
+
+	im = (immap_t *) CONFIG_SYS_IMMR;
+	gpioregs = &im->gpio;
+	out_be32(&gpioregs->gpodr, 0x00290000); /* open drain */
+	out_be32(&gpioregs->gpdat, 0x80001040); /* data (when output) */
+
+	/*
+	 * out_be32(&gpioregs->gpdir, 0xC2293020);
+	 * workaround for a hardware effect: configure direction in pieces,
+	 * setting all outputs at once drops the reset line too low and
+	 * makes us lose the MII connection (breaks ethernet for us)
+	 */
+	out_be32(&gpioregs->gpdir, 0x02003060); /* direction */
+	setbits_be32(&gpioregs->gpdir, 0x00200000); /* += reset asi */
+	udelay(10);
+	setbits_be32(&gpioregs->gpdir, 0x00080000); /* += reset safety */
+	udelay(10);
+	setbits_be32(&gpioregs->gpdir, 0x00010000); /* += reset comm */
+	udelay(10);
+	setbits_be32(&gpioregs->gpdir, 0xC0000000); /* += backlight, KB sel */
+
+	/* to turn from red to yellow when U-Boot runs */
+	setbits_be32(&gpioregs->gpdat, 0x00002020);
+	out_be32(&gpioregs->gpimr, 0x00000000); /* interrupt mask */
+	out_be32(&gpioregs->gpicr1, 0x00000004); /* interrupt sense part 1 */
+	out_be32(&gpioregs->gpicr2, 0x00A80000); /* interrupt sense part 2 */
+	out_be32(&gpioregs->gpier, 0xFFFFFFFF); /* interrupt events, clear */
+}
+
+/* the physical location of the pins */
+#define GPIOKEY_ROW_BITMASK	0x40000000
+#define GPIOKEY_ROW_UPPER	0
+#define GPIOKEY_ROW_LOWER	1
+
+#define GPIOKEY_COL0_BITMASK	0x20000000
+#define GPIOKEY_COL1_BITMASK	0x10000000
+#define GPIOKEY_COL2_BITMASK	0x08000000
+
+/* the logical presentation of pressed keys */
+#define GPIOKEY_BIT_FNLEFT	(1 << 5)
+#define GPIOKEY_BIT_FNRIGHT	(1 << 4)
+#define GPIOKEY_BIT_DIRUP	(1 << 3)
+#define GPIOKEY_BIT_DIRLEFT	(1 << 2)
+#define GPIOKEY_BIT_DIRRIGHT	(1 << 1)
+#define GPIOKEY_BIT_DIRDOWN	(1 << 0)
+
+/* the hotkey combination which starts recovery */
+#define GPIOKEY_BITS_RECOVERY	(GPIOKEY_BIT_FNLEFT | GPIOKEY_BIT_DIRUP | \
+				 GPIOKEY_BIT_DIRDOWN)
+
+static void gpio_selectrow(gpio512x_t *gpioregs, u32 row)
+{
+
+	if (row)
+		setbits_be32(&gpioregs->gpdat, GPIOKEY_ROW_BITMASK);
+	else
+		clrbits_be32(&gpioregs->gpdat, GPIOKEY_ROW_BITMASK);
+	udelay(10);
+}
+
+static u32 gpio_querykbd(void)
+{
+	immap_t *im;
+	gpio512x_t *gpioregs;
+	u32 keybits;
+	u32 input;
+
+	im = (immap_t *)CONFIG_SYS_IMMR;
+	gpioregs = &im->gpio;
+	keybits = 0;
+
+	/* query upper row */
+	gpio_selectrow(gpioregs, GPIOKEY_ROW_UPPER);
+	input = in_be32(&gpioregs->gpdat);
+	if ((input & GPIOKEY_COL0_BITMASK) == 0)
+		keybits |= GPIOKEY_BIT_FNLEFT;
+	if ((input & GPIOKEY_COL1_BITMASK) == 0)
+		keybits |= GPIOKEY_BIT_DIRUP;
+	if ((input & GPIOKEY_COL2_BITMASK) == 0)
+		keybits |= GPIOKEY_BIT_FNRIGHT;
+
+	/* query lower row */
+	gpio_selectrow(gpioregs, GPIOKEY_ROW_LOWER);
+	input = in_be32(&gpioregs->gpdat);
+	if ((input & GPIOKEY_COL0_BITMASK) == 0)
+		keybits |= GPIOKEY_BIT_DIRLEFT;
+	if ((input & GPIOKEY_COL1_BITMASK) == 0)
+		keybits |= GPIOKEY_BIT_DIRRIGHT;
+	if ((input & GPIOKEY_COL2_BITMASK) == 0)
+		keybits |= GPIOKEY_BIT_DIRDOWN;
+
+	/* return bit pattern for keys */
+	return keybits;
+}
+
+/* excerpt from the recovery's hw_info.h */
+
+struct __attribute__ ((__packed__)) eeprom_layout {
+	char	magic[3];	/** 'ifm' */
+	u8	len[2];		/** content length without magic/len fields */
+	u8	version[3];	/** structure version */
+	u8	type;		/** type of PCB */
+	u8	reserved[0x37];	/** padding up to offset 0x40 */
+	u8	macaddress[6];	/** ethernet MAC (for the mainboard) @0x40 */
+};
+
+#define HW_COMP_MAINCPU 2
+
+static struct eeprom_layout eeprom_content;
+static int eeprom_is_valid;
+static int eeprom_version;
+
+#define get_eeprom_field_int(name) ({ \
+	int value; \
+	int idx; \
+	value = 0; \
+	for (idx = 0; idx < sizeof(name); idx++) { \
+		value <<= 8; \
+		value |= name[idx]; \
+	} \
+	value; \
+})
+
+static int read_eeprom(void)
+{
+	return -ENOSYS;
+}
+
+int mac_read_from_eeprom(void)
+{
+	const u8 *mac;
+	const char *mac_txt;
+
+	if (read_eeprom()) {
+		printf("I2C EEPROM read failed.\n");
+		return -1;
+	}
+
+	if (!eeprom_is_valid) {
+		printf("I2C EEPROM content not valid\n");
+		return -1;
+	}
+
+	mac = NULL;
+	switch (eeprom_version) {
+	case 1:
+	case 2:
+		mac = (const u8 *)&eeprom_content.macaddress;
+		break;
+	}
+
+	if (mac && is_valid_ethaddr(mac)) {
+		eth_setenv_enetaddr("ethaddr", mac);
+		if (mac_diag) {
+			mac_txt = getenv("ethaddr");
+			if (mac_txt)
+				printf("DIAG: MAC value [%s]\n", mac_txt);
+			else
+				printf("DIAG: failed to setup MAC env\n");
+		}
+	}
+
+	return 0;
+}
+
+/*
+ * BEWARE!
+ * this board uses DDR1(!) Micron SDRAM, *NOT* the DDR2
+ * which the ADS, Aria or PDM360NG boards are using
+ * (the steps outlined here refer to the Micron datasheet)
+ */
+u32 sdram_init_seq[] = {
+	/* item 6, at least one NOP after CKE went high */
+	CONFIG_SYS_DDRCMD_NOP,
+	CONFIG_SYS_DDRCMD_NOP,
+	CONFIG_SYS_DDRCMD_NOP,
+	CONFIG_SYS_DDRCMD_NOP,
+	CONFIG_SYS_DDRCMD_NOP,
+	CONFIG_SYS_DDRCMD_NOP,
+	CONFIG_SYS_DDRCMD_NOP,
+	CONFIG_SYS_DDRCMD_NOP,
+	CONFIG_SYS_DDRCMD_NOP,
+	CONFIG_SYS_DDRCMD_NOP,
+	/* item 7, precharge all; item 8, tRP (20ns) */
+	CONFIG_SYS_DDRCMD_PCHG_ALL,
+	CONFIG_SYS_DDRCMD_NOP,
+	/* item 9, extended mode register; item 10, tMRD 10ns) */
+	CONFIG_SYS_MICRON_EMODE | CONFIG_SYS_MICRON_EMODE_PARAM,
+	CONFIG_SYS_DDRCMD_NOP,
+	/*
+	 * item 11, (base) mode register _with_ reset DLL;
+	 * item 12, tMRD (10ns)
+	 */
+	CONFIG_SYS_MICRON_BMODE | CONFIG_SYS_MICRON_BMODE_RSTDLL |
+	CONFIG_SYS_MICRON_BMODE_PARAM,
+	CONFIG_SYS_DDRCMD_NOP,
+	/* item 13, precharge all; item 14, tRP (20ns) */
+	CONFIG_SYS_DDRCMD_PCHG_ALL,
+	CONFIG_SYS_DDRCMD_NOP,
+	/*
+	 * item 15, auto refresh (i.e. refresh with CKE held high);
+	 * item 16, tRFC (70ns)
+	 */
+	CONFIG_SYS_DDRCMD_RFSH,
+	CONFIG_SYS_DDRCMD_NOP,
+	CONFIG_SYS_DDRCMD_NOP,
+	CONFIG_SYS_DDRCMD_NOP,
+	CONFIG_SYS_DDRCMD_NOP,
+	CONFIG_SYS_DDRCMD_NOP,
+	CONFIG_SYS_DDRCMD_NOP,
+	CONFIG_SYS_DDRCMD_NOP,
+	CONFIG_SYS_DDRCMD_NOP,
+	/*
+	 * item 17, auto refresh (i.e. refresh with CKE held high);
+	 * item 18, tRFC (70ns)
+	 */
+	CONFIG_SYS_DDRCMD_RFSH,
+	CONFIG_SYS_DDRCMD_NOP,
+	CONFIG_SYS_DDRCMD_NOP,
+	CONFIG_SYS_DDRCMD_NOP,
+	CONFIG_SYS_DDRCMD_NOP,
+	CONFIG_SYS_DDRCMD_NOP,
+	CONFIG_SYS_DDRCMD_NOP,
+	CONFIG_SYS_DDRCMD_NOP,
+	CONFIG_SYS_DDRCMD_NOP,
+	/* item 19, optional, unassert DLL reset; item 20, tMRD (20ns) */
+	CONFIG_SYS_MICRON_BMODE | CONFIG_SYS_MICRON_BMODE_PARAM,
+	CONFIG_SYS_DDRCMD_NOP,
+	/*
+	 * item 21, "actually done", but make sure 200 DRAM clock cycles
+	 * have passed after DLL reset before READ requests are issued
+	 * (200 cycles at 160MHz -> 1.25 usec)
+	 */
+	/* EMPTY, optional, we don't do it */
+};
+
+int dram_init(void)
+{
+	gd->ram_size = fixed_sdram(NULL, sdram_init_seq,
+				   ARRAY_SIZE(sdram_init_seq));
+
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	u32 keys;
+	char *s;
+	int want_recovery;
+
+	/* setup GPIO directions and initial values */
+	gpio_configure();
+
+	/*
+	 * enforce the start of the recovery system when
+	 * - the appropriate keys were pressed
+	 * - "some" external software told us to
+	 * - a previous installation was aborted or has failed
+	 */
+	want_recovery = 0;
+	keys = gpio_querykbd();
+	if (gpio_diag)
+		printf("GPIO keyboard status [0x%02X]\n", keys);
+	if ((keys & GPIOKEY_BITS_RECOVERY) == GPIOKEY_BITS_RECOVERY) {
+		printf("detected recovery request (keyboard)\n");
+		want_recovery = 1;
+	}
+	s = getenv("want_recovery");
+	if ((s != NULL) && (*s != '\0')) {
+		printf("detected recovery request (environment)\n");
+		want_recovery = 1;
+	}
+	s = getenv("install_in_progress");
+	if ((s != NULL) && (*s != '\0')) {
+		printf("previous installation has not completed\n");
+		want_recovery = 1;
+	}
+	s = getenv("install_failed");
+	if ((s != NULL) && (*s != '\0')) {
+		printf("previous installation has failed\n");
+		want_recovery = 1;
+	}
+	if (want_recovery) {
+		printf("enforced start of the recovery system\n");
+		setenv("bootcmd", "run recovery");
+	}
+
+	/*
+	 * boot the recovery system without waiting; boot the
+	 * production system without waiting by default, only
+	 * insert a pause (to provide a chance to get a prompt)
+	 * when GPIO keys were pressed during power on
+	 */
+	if (want_recovery)
+		setenv("bootdelay", "0");
+	else if (!keys)
+		setenv("bootdelay", "0");
+	else
+		setenv("bootdelay", "2");
+
+	/* get the ethernet MAC from I2C EEPROM */
+	mac_read_from_eeprom();
+
+	return 0;
+}
+
+/* setup specific IO pad configuration */
+static  iopin_t ioregs_init[] = {
+	{	/* LPC CS3 */
+		offsetof(struct ioctrl512x, io_control_nfc_ce0), 1,
+		IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
+		IO_PIN_FMUX(1) | IO_PIN_DS(2),
+	},
+	{	/* LPC CS1 */
+		offsetof(struct ioctrl512x, io_control_lpc_cs1), 1,
+		IO_PIN_OVER_DRVSTR,
+		IO_PIN_DS(2),
+	},
+	{	/* LPC CS2 */
+		offsetof(struct ioctrl512x, io_control_lpc_cs2), 1,
+		IO_PIN_OVER_DRVSTR,
+		IO_PIN_DS(2),
+	},
+	{	/* LPC CS4, CS5 */
+		offsetof(struct ioctrl512x, io_control_pata_ce1), 2,
+		IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
+		IO_PIN_FMUX(1) | IO_PIN_DS(2),
+	},
+	{	/* SDHC CLK, CMD, D0, D1, D2, D3 */
+		offsetof(struct ioctrl512x, io_control_pata_ior), 6,
+		IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
+		IO_PIN_FMUX(1) | IO_PIN_DS(2),
+	},
+	{	/* GPIO keyboard */
+		offsetof(struct ioctrl512x, io_control_pci_ad30), 4,
+		IO_PIN_OVER_FMUX,
+		IO_PIN_FMUX(3),
+	},
+	{	/* GPIO DN1 PF, LCD power, DN2 PF */
+		offsetof(struct ioctrl512x, io_control_pci_ad26), 3,
+		IO_PIN_OVER_FMUX,
+		IO_PIN_FMUX(3),
+	},
+	{	/* GPIO reset AS-i */
+		offsetof(struct ioctrl512x, io_control_pci_ad21), 1,
+		IO_PIN_OVER_FMUX,
+		IO_PIN_FMUX(3),
+	},
+	{	/* GPIO reset safety */
+		offsetof(struct ioctrl512x, io_control_pci_ad19), 1,
+		IO_PIN_OVER_FMUX,
+		IO_PIN_FMUX(3),
+	},
+	{	/* GPIO reset netX */
+		offsetof(struct ioctrl512x, io_control_pci_ad16), 1,
+		IO_PIN_OVER_FMUX,
+		IO_PIN_FMUX(3),
+	},
+	{	/* GPIO ma2 en */
+		offsetof(struct ioctrl512x, io_control_pci_ad15), 1,
+		IO_PIN_OVER_FMUX,
+		IO_PIN_FMUX(3),
+	},
+	{	/* GPIO SD CD, SD WP */
+		offsetof(struct ioctrl512x, io_control_pci_ad08), 2,
+		IO_PIN_OVER_FMUX,
+		IO_PIN_FMUX(3),
+	},
+	{	/* FEC RX DV */
+		offsetof(struct ioctrl512x, io_control_pci_ad06), 1,
+		IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
+		IO_PIN_FMUX(2) | IO_PIN_DS(2),
+	},
+	{	/* GPIO AS-i prog, AS-i done, LCD backlight */
+		offsetof(struct ioctrl512x, io_control_pci_ad05), 3,
+		IO_PIN_OVER_FMUX,
+		IO_PIN_FMUX(3),
+	},
+	{	/* GPIO AS-i wdg */
+		offsetof(struct ioctrl512x, io_control_pci_req2), 1,
+		IO_PIN_OVER_FMUX,
+		IO_PIN_FMUX(3),
+	},
+	{	/* GPIO safety wdg */
+		offsetof(struct ioctrl512x, io_control_pci_req1), 1,
+		IO_PIN_OVER_FMUX,
+		IO_PIN_FMUX(3),
+	},
+	{	/* GPIO netX wdg */
+		offsetof(struct ioctrl512x, io_control_pci_req0), 1,
+		IO_PIN_OVER_FMUX,
+		IO_PIN_FMUX(3),
+	},
+	{	/* GPIO IRQ powerfail */
+		offsetof(struct ioctrl512x, io_control_pci_inta), 1,
+		IO_PIN_OVER_FMUX,
+		IO_PIN_FMUX(3),
+	},
+	{	/* GPIO AS-i PWRD */
+		offsetof(struct ioctrl512x, io_control_pci_frame), 1,
+		IO_PIN_OVER_FMUX,
+		IO_PIN_FMUX(3),
+	},
+	{	/* GPIO LED0, LED1 */
+		offsetof(struct ioctrl512x, io_control_pci_idsel), 2,
+		IO_PIN_OVER_FMUX,
+		IO_PIN_FMUX(3),
+	},
+	{	/* GPIO IRQ AS-i 1, IRQ AS-i 2, IRQ safety */
+		offsetof(struct ioctrl512x, io_control_pci_irdy), 3,
+		IO_PIN_OVER_FMUX,
+		IO_PIN_FMUX(3),
+	},
+	{	/* DIU clk */
+		offsetof(struct ioctrl512x, io_control_spdif_txclk), 1,
+		IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
+		IO_PIN_FMUX(2) | IO_PIN_DS(2),
+	},
+	{	/* FEC TX ER, CRS */
+		offsetof(struct ioctrl512x, io_control_spdif_tx), 2,
+		IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
+		IO_PIN_FMUX(1) | IO_PIN_DS(2),
+	},
+	{	/* GPIO/GPT */ /* to *NOT* have the EXT IRQ0 float */
+		offsetof(struct ioctrl512x, io_control_irq0), 1,
+		IO_PIN_OVER_FMUX,
+		IO_PIN_FMUX(3),
+	},
+	{	/*
+		 * FEC col, tx en, tx clk, txd 0-3, mdc, rx er,
+		 * rdx 3-0, mdio, rx clk
+		 */
+		offsetof(struct ioctrl512x, io_control_psc0_0), 15,
+		IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
+		IO_PIN_FMUX(1) | IO_PIN_DS(2),
+	},
+	/* optional: make sure PSC3 remains the serial console */
+	{	/* LPC CS6 */
+		offsetof(struct ioctrl512x, io_control_psc3_4), 1,
+		IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
+		IO_PIN_FMUX(1) | IO_PIN_DS(2),
+	},
+	/* make sure PSC4 remains available for SPI,
+	    *BUT* PSC4_1 is a GPIO kind of SS! */
+	{	/* enforce drive strength on the SPI pin */
+		offsetof(struct ioctrl512x, io_control_psc4_0), 5,
+		IO_PIN_OVER_DRVSTR,
+		IO_PIN_DS(2),
+	},
+	{
+		offsetof(struct ioctrl512x, io_control_psc4_1), 1,
+		IO_PIN_OVER_FMUX,
+		IO_PIN_FMUX(3),
+	},
+	/* optional: make sure PSC5 remains available for SPI */
+	{	/* enforce drive strength on the SPI pin */
+		offsetof(struct ioctrl512x, io_control_psc5_0), 5,
+		IO_PIN_OVER_DRVSTR,
+		IO_PIN_DS(1),
+	},
+	{	/* LPC TSIZ1 */
+		offsetof(struct ioctrl512x, io_control_psc6_0), 1,
+		IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
+		IO_PIN_FMUX(1) | IO_PIN_DS(2),
+	},
+	{	/* DIU hsync */
+		offsetof(struct ioctrl512x, io_control_psc6_1), 1,
+		IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
+		IO_PIN_FMUX(2) | IO_PIN_DS(1),
+	},
+	{	/* DIU vsync */
+		offsetof(struct ioctrl512x, io_control_psc6_4), 1,
+		IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
+		IO_PIN_FMUX(2) | IO_PIN_DS(1),
+	},
+	{	/* PSC7, part of DIU RGB */
+		offsetof(struct ioctrl512x, io_control_psc7_0), 2,
+		IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
+		IO_PIN_FMUX(2) | IO_PIN_DS(1),
+	},
+	{	/* PSC7, safety UART */
+		offsetof(struct ioctrl512x, io_control_psc7_2), 2,
+		IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
+		IO_PIN_FMUX(0) | IO_PIN_DS(1),
+	},
+	{	/* DIU (part of) RGB[] */
+		offsetof(struct ioctrl512x, io_control_psc8_3), 16,
+		IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
+		IO_PIN_FMUX(2) | IO_PIN_DS(1),
+	},
+	{	/* DIU data enable */
+		offsetof(struct ioctrl512x, io_control_psc11_4), 1,
+		IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
+		IO_PIN_FMUX(2) | IO_PIN_DS(1),
+	},
+	/* reduce LPB drive strength for improved EMI */
+	{	/* LPC OE, LPC RW */
+		offsetof(struct ioctrl512x, io_control_lpc_oe), 2,
+		IO_PIN_OVER_DRVSTR,
+		IO_PIN_DS(2),
+	},
+	{	/* LPC AX03 through LPC AD00 */
+		offsetof(struct ioctrl512x, io_control_lpc_ax03), 36,
+		IO_PIN_OVER_DRVSTR,
+		IO_PIN_DS(2),
+	},
+	{	/* LPC CS5 */
+		offsetof(struct ioctrl512x, io_control_pata_ce2), 1,
+		IO_PIN_OVER_DRVSTR,
+		IO_PIN_DS(2),
+	},
+	{	/* SDHC CLK */
+		offsetof(struct ioctrl512x, io_control_nfc_wp), 1,
+		IO_PIN_OVER_DRVSTR,
+		IO_PIN_DS(2),
+	},
+	{	/* SDHC DATA */
+		offsetof(struct ioctrl512x, io_control_nfc_ale), 4,
+		IO_PIN_OVER_DRVSTR,
+		IO_PIN_DS(2),
+	},
+};
+
+int checkboard(void)
+{
+	puts("Board: ifm AC14xx\n");
+
+	/* initialize function mux & slew rate IO inter alia on IO Pins  */
+	iopin_initialize_bits(ioregs_init, ARRAY_SIZE(ioregs_init));
+
+	return 0;
+}
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, bd_t *bd)
+{
+	ft_cpu_setup(blob, bd);
+
+	return 0;
+}
+#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/ifm/o2dnt2/Kconfig b/board/ifm/o2dnt2/Kconfig
new file mode 100644
index 0000000000..e9d32ddc54
--- /dev/null
+++ b/board/ifm/o2dnt2/Kconfig
@@ -0,0 +1,77 @@ 
+if TARGET_O2D
+
+config SYS_BOARD
+	default "o2dnt2"
+
+config SYS_VENDOR
+	default "ifm"
+
+config SYS_CONFIG_NAME
+	default "o2d"
+
+endif
+
+if TARGET_O2D300
+
+config SYS_BOARD
+	default "o2dnt2"
+
+config SYS_VENDOR
+	default "ifm"
+
+config SYS_CONFIG_NAME
+	default "o2d300"
+
+endif
+
+if TARGET_O2DNT2
+
+config SYS_BOARD
+	default "o2dnt2"
+
+config SYS_VENDOR
+	default "ifm"
+
+config SYS_CONFIG_NAME
+	default "o2dnt2"
+
+endif
+
+if TARGET_O2I
+
+config SYS_BOARD
+	default "o2dnt2"
+
+config SYS_VENDOR
+	default "ifm"
+
+config SYS_CONFIG_NAME
+	default "o2i"
+
+endif
+
+if TARGET_O2MNT
+
+config SYS_BOARD
+	default "o2dnt2"
+
+config SYS_VENDOR
+	default "ifm"
+
+config SYS_CONFIG_NAME
+	default "o2mnt"
+
+endif
+
+if TARGET_O3DNT
+
+config SYS_BOARD
+	default "o2dnt2"
+
+config SYS_VENDOR
+	default "ifm"
+
+config SYS_CONFIG_NAME
+	default "o3dnt"
+
+endif
diff --git a/board/ifm/o2dnt2/MAINTAINERS b/board/ifm/o2dnt2/MAINTAINERS
new file mode 100644
index 0000000000..002f89e729
--- /dev/null
+++ b/board/ifm/o2dnt2/MAINTAINERS
@@ -0,0 +1,20 @@ 
+O2DNT2 BOARD
+M:	Anatolij Gustschin <agust@denx.de>
+S:	Maintained
+F:	board/ifm/o2dnt2/
+F:	include/configs/o2d.h
+F:	configs/O2D_defconfig
+F:	include/configs/o2d300.h
+F:	configs/O2D300_defconfig
+F:	include/configs/o2dnt2.h
+F:	configs/O2DNT2_defconfig
+F:	configs/O2DNT2_RAMBOOT_defconfig
+F:	include/configs/o2i.h
+F:	configs/O2I_defconfig
+F:	include/configs/o2mnt.h
+F:	configs/O2MNT_defconfig
+F:	configs/O2MNT_O2M110_defconfig
+F:	configs/O2MNT_O2M112_defconfig
+F:	configs/O2MNT_O2M113_defconfig
+F:	include/configs/o3dnt.h
+F:	configs/O3DNT_defconfig
diff --git a/board/ifm/o2dnt2/Makefile b/board/ifm/o2dnt2/Makefile
new file mode 100644
index 0000000000..64d6ba8c55
--- /dev/null
+++ b/board/ifm/o2dnt2/Makefile
@@ -0,0 +1,8 @@ 
+#
+# (C) Copyright 2005-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	:= o2dnt2.o
diff --git a/board/ifm/o2dnt2/o2dnt2.c b/board/ifm/o2dnt2/o2dnt2.c
new file mode 100644
index 0000000000..7770806bd2
--- /dev/null
+++ b/board/ifm/o2dnt2/o2dnt2.c
@@ -0,0 +1,388 @@ 
+/*
+ * Partially derived from board code for digsyMTC,
+ * (C) Copyright 2009
+ * Grzegorz Bernacki, Semihalf, gjb@semihalf.com
+ *
+ * (C) Copyright 2012
+ * DENX Software Engineering, Anatolij Gustschin <agust@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <net.h>
+#include <pci.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define SDRAM_MODE	0x00CD0000
+#define SDRAM_CONTROL	0x504F0000
+#define SDRAM_CONFIG1	0xD2322800
+#define SDRAM_CONFIG2	0x8AD70000
+
+enum ifm_sensor_type {
+	O2DNT		= 0x00,	/* !< O2DNT 32MB */
+	O2DNT2		= 0x01,	/* !< O2DNT2 64MB */
+	O3DNT		= 0x02,	/* !< O3DNT 32MB */
+	O3DNT_MIN	= 0x40,	/* !< O3DNT Minerva 32MB */
+	UNKNOWN		= 0xff,	/* !< Unknow sensor */
+};
+
+static enum ifm_sensor_type gt_ifm_sensor_type;
+
+#ifndef CONFIG_SYS_RAMBOOT
+static void sdram_start(int hi_addr)
+{
+	struct mpc5xxx_sdram *sdram = (struct mpc5xxx_sdram *)MPC5XXX_SDRAM;
+	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
+	long control = SDRAM_CONTROL | hi_addr_bit;
+
+	/* unlock mode register */
+	out_be32(&sdram->ctrl, control | 0x80000000);
+
+	/* precharge all banks */
+	out_be32(&sdram->ctrl, control | 0x80000002);
+
+	/* auto refresh */
+	out_be32(&sdram->ctrl, control | 0x80000004);
+
+	/* set mode register */
+	out_be32(&sdram->mode, SDRAM_MODE);
+
+	/* normal operation */
+	out_be32(&sdram->ctrl, control);
+}
+#endif
+
+/*
+ * ATTENTION: Although partially referenced dram_init does NOT make real use
+ *            use of CONFIG_SYS_SDRAM_BASE. The code does not work if
+ *            CONFIG_SYS_SDRAM_BASE is something else than 0x00000000.
+ */
+int dram_init(void)
+{
+	struct mpc5xxx_mmap_ctl *mmap_ctl =
+		(struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR;
+	struct mpc5xxx_sdram *sdram = (struct mpc5xxx_sdram *)MPC5XXX_SDRAM;
+	ulong dramsize = 0;
+	ulong dramsize2 = 0;
+	uint svr, pvr;
+
+	if (gt_ifm_sensor_type == O2DNT2) {
+		/* activate SDRAM CS1 */
+		setbits_be32((void *)MPC5XXX_GPS_PORT_CONFIG, 0x80000000);
+	}
+
+#ifndef CONFIG_SYS_RAMBOOT
+	ulong test1, test2;
+
+	/* setup SDRAM chip selects */
+	out_be32(&mmap_ctl->sdram0, 0x0000001E); /* 2 GB at 0x0 */
+	out_be32(&mmap_ctl->sdram1, 0x00000000); /* disabled */
+
+	/* setup config registers */
+	out_be32(&sdram->config1, SDRAM_CONFIG1);
+	out_be32(&sdram->config2, SDRAM_CONFIG2);
+
+	/* find RAM size using SDRAM CS0 only */
+	sdram_start(0);
+	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x08000000);
+	sdram_start(1);
+	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x08000000);
+	if (test1 > test2) {
+		sdram_start(0);
+		dramsize = test1;
+	} else {
+		dramsize = test2;
+	}
+
+	/* memory smaller than 1MB is impossible */
+	if (dramsize < (1 << 20))
+		dramsize = 0;
+
+	/* set SDRAM CS0 size according to the amount of RAM found */
+	if (dramsize > 0) {
+		out_be32(&mmap_ctl->sdram0,
+			 (0x13 + __builtin_ffs(dramsize >> 20) - 1));
+	} else {
+		out_be32(&mmap_ctl->sdram0, 0); /* disabled */
+	}
+
+	/* let SDRAM CS1 start right after CS0 */
+	out_be32(&mmap_ctl->sdram1, dramsize + 0x0000001E); /* 2G */
+
+	/* find RAM size using SDRAM CS1 only */
+	if (!dramsize)
+		sdram_start(0);
+
+	test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize),
+					0x80000000);
+	if (!dramsize) {
+		sdram_start(1);
+		test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize),
+					0x80000000);
+	}
+
+	if (test1 > test2) {
+		sdram_start(0);
+		dramsize2 = test1;
+	} else {
+		dramsize2 = test2;
+	}
+
+	/* memory smaller than 1MB is impossible */
+	if (dramsize2 < (1 << 20))
+		dramsize2 = 0;
+
+	/* set SDRAM CS1 size according to the amount of RAM found */
+	if (dramsize2 > 0) {
+		out_be32(&mmap_ctl->sdram1, (dramsize |
+			 (0x13 + __builtin_ffs(dramsize2 >> 20) - 1)));
+	} else {
+		out_be32(&mmap_ctl->sdram1, dramsize); /* disabled */
+	}
+
+#else /* CONFIG_SYS_RAMBOOT */
+	/* retrieve size of memory connected to SDRAM CS0 */
+	dramsize = in_be32(&mmap_ctl->sdram0) & 0xFF;
+	if (dramsize >= 0x13)
+		dramsize = (1 << (dramsize - 0x13)) << 20;
+	else
+		dramsize = 0;
+
+	/* retrieve size of memory connected to SDRAM CS1 */
+	dramsize2 = in_be32(&mmap_ctl->sdram1) & 0xFF;
+	if (dramsize2 >= 0x13)
+		dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
+	else
+		dramsize2 = 0;
+
+#endif /* CONFIG_SYS_RAMBOOT */
+
+	/*
+	 * On MPC5200B we need to set the special configuration delay in the
+	 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
+	 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
+	 *
+	 * "The SDelay should be written to a value of 0x00000004. It is
+	 * required to account for changes caused by normal wafer processing
+	 * parameters."
+	 */
+	svr = get_svr();
+	pvr = get_pvr();
+	if ((SVR_MJREV(svr) >= 2) &&
+	    (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4))
+		out_be32(&sdram->sdelay, 0x04);
+
+	gd->ram_size = dramsize + dramsize2;
+
+	return 0;
+}
+
+
+#define GPT_GPIO_IN	0x4
+
+int checkboard(void)
+{
+	struct mpc5xxx_gpt *gpt = (struct mpc5xxx_gpt *)MPC5XXX_GPT;
+	unsigned char board_config = 0;
+	int i;
+
+	/* switch gpt0 - gpt7 to input */
+	for (i = 0; i < 7; i++)
+		out_be32(&gpt[i].emsr, GPT_GPIO_IN);
+
+	/* get configuration byte on timer-port */
+	for (i = 0; i < 7; i++)
+		board_config |= (in_be32(&gpt[i].sr) & 0x100) >> (8 - i);
+
+	puts("Board: ");
+
+	switch (board_config) {
+	case 0:
+		puts("O2DNT\n");
+		gt_ifm_sensor_type = O2DNT;
+		break;
+	case 1:
+		puts("O3DNT\n");
+		gt_ifm_sensor_type = O3DNT;
+		break;
+	case 2:
+		puts("O2DNT2\n");
+		gt_ifm_sensor_type = O2DNT2;
+		break;
+	case 64:
+		puts("O3DNT Minerva\n");
+		gt_ifm_sensor_type = O3DNT_MIN;
+		break;
+	default:
+		puts("Unknown\n");
+		gt_ifm_sensor_type = UNKNOWN;
+		break;
+	}
+
+	return 0;
+}
+
+int board_early_init_r(void)
+{
+	struct mpc5xxx_lpb *lpb_regs = (struct mpc5xxx_lpb *)MPC5XXX_LPB;
+
+	/*
+	 * Now, when we are in RAM, enable flash write access for detection
+	 * process. Note that CS_BOOT cannot be cleared when executing in flash.
+	 */
+	clrbits_be32(&lpb_regs->cs0_cfg, 1); /* clear RO */
+	/* disable CS_BOOT */
+	clrbits_be32((void *)MPC5XXX_ADDECR, (1 << 25));
+	/* enable CS0 */
+	setbits_be32((void *)MPC5XXX_ADDECR, (1 << 16));
+
+	return 0;
+}
+
+#define MIIM_LXT971_LED_CFG_REG		0x14
+#define LXT971_LED_CFG_LINK_STATUS	0x4000
+#define LXT971_LED_CFG_RX_TX_ACTIVITY	0x0700
+#define LXT971_LED_CFG_LINK_ACTIVITY	0x00D0
+#define LXT971_LED_CFG_PULSE_STRETCH	0x0002
+/*
+ * Additional PHY intialization after reset in mpc5xxx_fec_init_phy()
+ */
+void reset_phy(void)
+{
+	/*
+	 * Set LED configuration bits.
+	 * It can't be done in misc_init_r() since FEC is not
+	 * initialized at this time. Therefore we do it here.
+	 */
+	miiphy_write("FEC", CONFIG_PHY_ADDR, MIIM_LXT971_LED_CFG_REG,
+			LXT971_LED_CFG_LINK_STATUS |
+			LXT971_LED_CFG_RX_TX_ACTIVITY |
+			LXT971_LED_CFG_LINK_ACTIVITY |
+			LXT971_LED_CFG_PULSE_STRETCH);
+}
+
+#if defined(CONFIG_POST)
+/*
+ * Reads GPIO pin PSC6_3. A keypress is reported, if PSC6_3 is low. If PSC6_3
+ * is left open, no keypress is detected.
+ */
+int post_hotkeys_pressed(void)
+{
+	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *) MPC5XXX_GPIO;
+
+	/*
+	 * Configure PSC6_1 and PSC6_3 as GPIO. PSC6 then couldn't be used in
+	 * CODEC or UART mode. Consumer IrDA should still be possible.
+	 */
+	clrbits_be32(&gpio->port_config, 0x07000000);
+	setbits_be32(&gpio->port_config, 0x03000000);
+
+	/* Enable GPIO for GPIO_IRDA_1 (IR_USB_CLK pin) = PSC6_3 */
+	setbits_be32(&gpio->simple_gpioe, 0x20000000);
+
+	/* Configure GPIO_IRDA_1 as input */
+	clrbits_be32(&gpio->simple_ddr, 0x20000000);
+
+	return (in_be32(&gpio->simple_ival) & 0x20000000) ? 0 : 1;
+}
+#endif
+
+#ifdef CONFIG_PCI
+static struct pci_controller hose;
+
+void pci_init_board(void)
+{
+	pci_mpc5xxx_init(&hose);
+}
+#endif
+
+#ifdef CONFIG_OF_BOARD_SETUP
+#if defined(CONFIG_SYS_UPDATE_FLASH_SIZE)
+static void ft_adapt_flash_base(void *blob)
+{
+	flash_info_t	*dev = &flash_info[0];
+	int off;
+	struct fdt_property *prop;
+	int len;
+	u32 *reg, *reg2;
+
+	off = fdt_node_offset_by_compatible(blob, -1, "fsl,mpc5200b-lpb");
+	if (off < 0) {
+		printf("Could not find fsl,mpc5200b-lpb node.\n");
+		return;
+	}
+
+	/* found compatible property */
+	prop = fdt_get_property_w(blob, off, "ranges", &len);
+	if (prop) {
+		reg = reg2 = (u32 *)&prop->data[0];
+
+		reg[2] = dev->start[0];
+		reg[3] = dev->size;
+		fdt_setprop(blob, off, "ranges", reg2, len);
+	} else
+		printf("Could not find ranges\n");
+}
+
+extern ulong flash_get_size(phys_addr_t base, int banknum);
+
+/* Update the flash baseaddr settings */
+int update_flash_size(int flash_size)
+{
+	struct mpc5xxx_mmap_ctl *mm =
+		(struct mpc5xxx_mmap_ctl *) CONFIG_SYS_MBAR;
+	flash_info_t *dev;
+	int i;
+	int size = 0;
+	unsigned long base = 0x0;
+	u32 *cs_reg = (u32 *)&mm->cs0_start;
+
+	for (i = 0; i < 2; i++) {
+		dev = &flash_info[i];
+
+		if (dev->size) {
+			/* calculate new base addr for this chipselect */
+			base -= dev->size;
+			out_be32(cs_reg, START_REG(base));
+			cs_reg++;
+			out_be32(cs_reg, STOP_REG(base, dev->size));
+			cs_reg++;
+			/* recalculate the sectoraddr in the cfi driver */
+			size += flash_get_size(base, i);
+		}
+	}
+	flash_protect_default();
+	gd->bd->bi_flashstart = base;
+	return 0;
+}
+#endif /* defined(CONFIG_SYS_UPDATE_FLASH_SIZE) */
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+	int phy_addr = CONFIG_PHY_ADDR;
+	char eth_path[] = "/soc5200@f0000000/mdio@3000/ethernet-phy@0";
+
+	ft_cpu_setup(blob, bd);
+
+#if defined(CONFIG_SYS_UPDATE_FLASH_SIZE)
+#ifdef CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
+	/* Update reg property in all nor flash nodes too */
+	fdt_fixup_nor_flash_size(blob);
+#endif
+	ft_adapt_flash_base(blob);
+#endif
+	/* fix up the phy address */
+	do_fixup_by_path(blob, eth_path, "reg", &phy_addr, sizeof(int), 0);
+
+	return 0;
+}
+#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/inka4x0/Kconfig b/board/inka4x0/Kconfig
new file mode 100644
index 0000000000..94a41f01a5
--- /dev/null
+++ b/board/inka4x0/Kconfig
@@ -0,0 +1,9 @@ 
+if TARGET_INKA4X0
+
+config SYS_BOARD
+	default "inka4x0"
+
+config SYS_CONFIG_NAME
+	default "inka4x0"
+
+endif
diff --git a/board/inka4x0/MAINTAINERS b/board/inka4x0/MAINTAINERS
new file mode 100644
index 0000000000..e8cec73a1a
--- /dev/null
+++ b/board/inka4x0/MAINTAINERS
@@ -0,0 +1,6 @@ 
+INKA4X0 BOARD
+M:	Anatolij Gustschin <agust@denx.de>
+S:	Maintained
+F:	board/inka4x0/
+F:	include/configs/inka4x0.h
+F:	configs/inka4x0_defconfig
diff --git a/board/inka4x0/Makefile b/board/inka4x0/Makefile
new file mode 100644
index 0000000000..c9a3540799
--- /dev/null
+++ b/board/inka4x0/Makefile
@@ -0,0 +1,8 @@ 
+#
+# (C) Copyright 2003-2009
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	:= inka4x0.o inkadiag.o
diff --git a/board/inka4x0/inka4x0.c b/board/inka4x0/inka4x0.c
new file mode 100644
index 0000000000..88cae59e8f
--- /dev/null
+++ b/board/inka4x0/inka4x0.c
@@ -0,0 +1,254 @@ 
+/*
+ * (C) Copyright 2008-2009
+ * Andreas Pfefferle, DENX Software Engineering, ap@denx.de.
+ *
+ * (C) Copyright 2009
+ * Detlev Zundel, DENX Software Engineering, dzu@denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * (C) Copyright 2004
+ * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
+ *
+ * (C) Copyright 2003-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/io.h>
+#include <common.h>
+#include <mpc5xxx.h>
+#include <pci.h>
+
+#if defined(CONFIG_DDR_MT46V16M16)
+#include "mt46v16m16-75.h"
+#elif defined(CONFIG_SDR_MT48LC16M16A2)
+#include "mt48lc16m16a2-75.h"
+#elif defined(CONFIG_DDR_MT46V32M16)
+#include "mt46v32m16.h"
+#elif defined(CONFIG_DDR_HYB25D512160BF)
+#include "hyb25d512160bf.h"
+#elif defined(CONFIG_DDR_K4H511638C)
+#include "k4h511638c.h"
+#else
+#error "INKA4x0 SDRAM: invalid chip type specified!"
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifndef CONFIG_SYS_RAMBOOT
+static void sdram_start (int hi_addr)
+{
+	volatile struct mpc5xxx_sdram *sdram =
+		(struct mpc5xxx_sdram *)MPC5XXX_SDRAM;
+	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
+
+	/* unlock mode register */
+	out_be32(&sdram->ctrl, SDRAM_CONTROL | 0x80000000 | hi_addr_bit);
+
+	/* precharge all banks */
+	out_be32(&sdram->ctrl, SDRAM_CONTROL | 0x80000002 | hi_addr_bit);
+
+#if SDRAM_DDR
+	/* set mode register: extended mode */
+	out_be32(&sdram->mode, SDRAM_EMODE);
+
+	/* set mode register: reset DLL */
+	out_be32(&sdram->mode, SDRAM_MODE | 0x04000000);
+#endif
+
+	/* precharge all banks */
+	out_be32(&sdram->ctrl, SDRAM_CONTROL | 0x80000002 | hi_addr_bit);
+
+	/* auto refresh */
+	out_be32(&sdram->ctrl, SDRAM_CONTROL | 0x80000004 | hi_addr_bit);
+
+	/* set mode register */
+	out_be32(&sdram->mode, SDRAM_MODE);
+
+	/* normal operation */
+	out_be32(&sdram->ctrl, SDRAM_CONTROL | hi_addr_bit);
+}
+#endif
+
+/*
+ * ATTENTION: Although partially referenced dram_init does NOT make real use
+ *	      use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
+ *	      is something else than 0x00000000.
+ */
+
+int dram_init(void)
+{
+	volatile struct mpc5xxx_mmap_ctl *mm =
+		(struct mpc5xxx_mmap_ctl *) CONFIG_SYS_MBAR;
+	volatile struct mpc5xxx_cdm     *cdm =
+		(struct mpc5xxx_cdm *)      MPC5XXX_CDM;
+	volatile struct mpc5xxx_sdram *sdram =
+		(struct mpc5xxx_sdram *)    MPC5XXX_SDRAM;
+	ulong dramsize = 0;
+#ifndef CONFIG_SYS_RAMBOOT
+	long test1, test2;
+
+	/* setup SDRAM chip selects */
+	out_be32(&mm->sdram0, 0x0000001c);	/* 512MB at 0x0 */
+	out_be32(&mm->sdram1, 0x40000000);	/* disabled */
+
+	/* setup config registers */
+	out_be32(&sdram->config1, SDRAM_CONFIG1);
+	out_be32(&sdram->config2, SDRAM_CONFIG2);
+
+#if SDRAM_DDR
+	/* set tap delay */
+	out_be32(&cdm->porcfg, SDRAM_TAPDELAY);
+#endif
+
+	/* find RAM size using SDRAM CS0 only */
+	sdram_start(0);
+	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
+	sdram_start(1);
+	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
+	if (test1 > test2) {
+		sdram_start(0);
+		dramsize = test1;
+	} else {
+		dramsize = test2;
+	}
+
+	/* memory smaller than 1MB is impossible */
+	if (dramsize < (1 << 20)) {
+		dramsize = 0;
+	}
+
+	/* set SDRAM CS0 size according to the amount of RAM found */
+	if (dramsize > 0) {
+		out_be32(&mm->sdram0, 0x13 +
+			 __builtin_ffs(dramsize >> 20) - 1);
+	} else {
+		out_be32(&mm->sdram0, 0); /* disabled */
+	}
+
+	out_be32(&mm->sdram1, dramsize); /* disabled */
+#else /* CONFIG_SYS_RAMBOOT */
+
+	/* retrieve size of memory connected to SDRAM CS0 */
+	dramsize = in_be32(&mm->sdram0) & 0xFF;
+	if (dramsize >= 0x13) {
+		dramsize = (1 << (dramsize - 0x13)) << 20;
+	} else {
+		dramsize = 0;
+	}
+#endif /* CONFIG_SYS_RAMBOOT */
+
+	gd->ram_size = dramsize;
+
+	return 0;
+}
+
+int checkboard (void)
+{
+	puts ("Board: INKA 4X0\n");
+	return 0;
+}
+
+void flash_preinit(void)
+{
+	volatile struct mpc5xxx_lpb *lpb = (struct mpc5xxx_lpb *)MPC5XXX_LPB;
+
+	/*
+	 * Now, when we are in RAM, enable flash write
+	 * access for detection process.
+	 * Note that CS_BOOT (CS0) cannot be cleared when
+	 * executing in flash.
+	 */
+	clrbits_be32(&lpb->cs0_cfg, 0x1); /* clear RO */
+}
+
+int misc_init_f (void)
+{
+	volatile struct mpc5xxx_gpio	*gpio    =
+		(struct mpc5xxx_gpio *)   MPC5XXX_GPIO;
+	volatile struct mpc5xxx_wu_gpio	*wu_gpio =
+		(struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
+	volatile struct mpc5xxx_gpt	*gpt;
+	char tmp[10];
+	int i, br;
+
+	i = getenv_f("brightness", tmp, sizeof(tmp));
+	br = (i > 0)
+		? (int) simple_strtoul (tmp, NULL, 10)
+		: CONFIG_SYS_BRIGHTNESS;
+	if (br > 255)
+		br = 255;
+
+	/* Initialize GPIO output pins.
+	 */
+	/* Configure GPT as GPIO output (and set them as they control low-active LEDs */
+	for (i = 0; i <= 5; i++) {
+		gpt = (struct mpc5xxx_gpt *)(MPC5XXX_GPT + (i * 0x10));
+		out_be32(&gpt->emsr, 0x34);
+	}
+
+	/* Configure GPT7 as PWM timer, 1kHz, no ints. */
+	gpt = (struct mpc5xxx_gpt *)(MPC5XXX_GPT + (7 * 0x10));
+	out_be32(&gpt->emsr,  0);		/* Disable */
+	out_be32(&gpt->cir,   0x020000fe);
+	out_be32(&gpt->pwmcr, (br << 16));
+	out_be32(&gpt->emsr,  0x3);		/* Enable PWM mode and start */
+
+	/* Configure PSC3_6,7 as GPIO output */
+	setbits_be32(&gpio->simple_gpioe, MPC5XXX_GPIO_SIMPLE_PSC3_6 |
+					  MPC5XXX_GPIO_SIMPLE_PSC3_7);
+	setbits_be32(&gpio->simple_ddr,   MPC5XXX_GPIO_SIMPLE_PSC3_6 |
+					  MPC5XXX_GPIO_SIMPLE_PSC3_7);
+
+	/* Configure PSC3_9 and GPIO_WKUP6,7 as GPIO output */
+	setbits_8(&wu_gpio->enable,  MPC5XXX_GPIO_WKUP_6 |
+				     MPC5XXX_GPIO_WKUP_7 |
+				     MPC5XXX_GPIO_WKUP_PSC3_9);
+	setbits_8(&wu_gpio->ddr,     MPC5XXX_GPIO_WKUP_6 |
+				     MPC5XXX_GPIO_WKUP_7 |
+				     MPC5XXX_GPIO_WKUP_PSC3_9);
+
+	/* Set LR mirror bit because it is low-active */
+	setbits_8(&wu_gpio->dvo,     MPC5XXX_GPIO_WKUP_7);
+
+	/* Reset Coral-P graphics controller */
+	setbits_8(&wu_gpio->dvo,     MPC5XXX_GPIO_WKUP_PSC3_9);
+
+	/* Enable display backlight */
+	clrbits_8(&gpio->sint_inten, MPC5XXX_GPIO_SINT_PSC3_8);
+	setbits_8(&gpio->sint_gpioe, MPC5XXX_GPIO_SINT_PSC3_8);
+	setbits_8(&gpio->sint_ddr,   MPC5XXX_GPIO_SINT_PSC3_8);
+	setbits_8(&gpio->sint_dvo,   MPC5XXX_GPIO_SINT_PSC3_8);
+
+	/*
+	 * Configure three wire serial interface to RTC (PSC1_4,
+	 * PSC2_4, PSC3_4, PSC3_5)
+	 */
+	setbits_8(&wu_gpio->enable,  MPC5XXX_GPIO_WKUP_PSC1_4 |
+				     MPC5XXX_GPIO_WKUP_PSC2_4);
+	setbits_8(&wu_gpio->ddr,     MPC5XXX_GPIO_WKUP_PSC1_4 |
+				     MPC5XXX_GPIO_WKUP_PSC2_4);
+	clrbits_8(&wu_gpio->dvo,     MPC5XXX_GPIO_WKUP_PSC1_4);
+	clrbits_8(&gpio->sint_inten, MPC5XXX_GPIO_SINT_PSC3_4 |
+				     MPC5XXX_GPIO_SINT_PSC3_5);
+	setbits_8(&gpio->sint_gpioe, MPC5XXX_GPIO_SINT_PSC3_4 |
+				     MPC5XXX_GPIO_SINT_PSC3_5);
+	setbits_8(&gpio->sint_ddr,   MPC5XXX_GPIO_SINT_PSC3_5);
+	clrbits_8(&gpio->sint_dvo,   MPC5XXX_GPIO_SINT_PSC3_5);
+
+	return 0;
+}
+
+#ifdef	CONFIG_PCI
+static struct pci_controller hose;
+
+extern void pci_mpc5xxx_init(struct pci_controller *);
+
+void pci_init_board(void)
+{
+	pci_mpc5xxx_init(&hose);
+}
+#endif
diff --git a/board/inka4x0/inkadiag.c b/board/inka4x0/inkadiag.c
new file mode 100644
index 0000000000..4c43205129
--- /dev/null
+++ b/board/inka4x0/inkadiag.c
@@ -0,0 +1,465 @@ 
+/*
+ * (C) Copyright 2008, 2009 Andreas Pfefferle,
+ *     DENX Software Engineering, ap@denx.de.
+ * (C) Copyright 2009 Detlev Zundel,
+ *     DENX Software Engineering, dzu@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/io.h>
+#include <common.h>
+#include <config.h>
+#include <console.h>
+#include <mpc5xxx.h>
+#include <pci.h>
+
+#include <command.h>
+
+/* This is needed for the includes in ns16550.h */
+#define CONFIG_SYS_NS16550_REG_SIZE 1
+#include <ns16550.h>
+
+#define GPIO_BASE		((u_char *)CONFIG_SYS_CS3_START)
+
+#define DIGIN_TOUCHSCR_MASK	0x00003000	/* Inputs 12-13 */
+#define DIGIN_KEYB_MASK		0x00010000	/* Input 16 */
+
+#define DIGIN_DRAWER_SW1	0x00400000	/* Input 22 */
+#define DIGIN_DRAWER_SW2	0x00800000	/* Input 23 */
+
+#define DIGIO_LED0		0x00000001	/* Output 0 */
+#define DIGIO_LED1		0x00000002	/* Output 1 */
+#define DIGIO_LED2		0x00000004	/* Output 2 */
+#define DIGIO_LED3		0x00000008	/* Output 3 */
+#define DIGIO_LED4		0x00000010	/* Output 4 */
+#define DIGIO_LED5		0x00000020	/* Output 5 */
+
+#define DIGIO_DRAWER1		0x00000100	/* Output 8 */
+#define DIGIO_DRAWER2		0x00000200	/* Output 9 */
+
+#define SERIAL_PORT_BASE	((u_char *)CONFIG_SYS_CS2_START)
+
+#define PSC_OP1_RTS	0x01
+#define PSC_OP0_RTS	0x01
+
+/*
+ * Table with supported baudrates (defined in inka4x0.h)
+ */
+static const unsigned long baudrate_table[] = CONFIG_SYS_BAUDRATE_TABLE;
+#define	N_BAUDRATES (sizeof(baudrate_table) / sizeof(baudrate_table[0]))
+
+static unsigned int inka_digin_get_input(void)
+{
+	return in_8(GPIO_BASE + 0) << 0 | in_8(GPIO_BASE + 1) << 8 |
+		in_8(GPIO_BASE + 2) << 16 | in_8(GPIO_BASE + 3) << 24;
+}
+
+#define LED_HIGH(NUM)							\
+	do {								\
+		setbits_be32((unsigned *)MPC5XXX_GPT##NUM##_ENABLE, 0x10); \
+	} while (0)
+
+#define LED_LOW(NUM)							\
+	do {								\
+		clrbits_be32((unsigned *)MPC5XXX_GPT##NUM##_ENABLE, 0x10); \
+	} while (0)
+
+#define CHECK_LED(NUM) \
+    do { \
+	    if (state & (1 << NUM)) {		\
+		    LED_HIGH(NUM);		\
+	    } else {				\
+		    LED_LOW(NUM);		\
+	    }					\
+    } while (0)
+
+static void inka_digio_set_output(unsigned int state, int which)
+{
+	volatile struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
+
+	if (which == 0) {
+		/* other */
+		CHECK_LED(0);
+		CHECK_LED(1);
+		CHECK_LED(2);
+		CHECK_LED(3);
+		CHECK_LED(4);
+		CHECK_LED(5);
+	} else {
+		if (which == 1) {
+			/* drawer1 */
+			if (state) {
+				clrbits_be32(&gpio->simple_dvo, 0x1000);
+				udelay(1);
+				setbits_be32(&gpio->simple_dvo, 0x1000);
+			} else {
+				setbits_be32(&gpio->simple_dvo, 0x1000);
+				udelay(1);
+				clrbits_be32(&gpio->simple_dvo, 0x1000);
+			}
+		}
+		if (which == 2) {
+			/* drawer 2 */
+			if (state) {
+				clrbits_be32(&gpio->simple_dvo, 0x2000);
+				udelay(1);
+				setbits_be32(&gpio->simple_dvo, 0x2000);
+			} else {
+				setbits_be32(&gpio->simple_dvo, 0x2000);
+				udelay(1);
+				clrbits_be32(&gpio->simple_dvo, 0x2000);
+			}
+		}
+	}
+	udelay(1);
+}
+
+static int do_inkadiag_io(cmd_tbl_t *cmdtp, int flag, int argc,
+			  char * const argv[]) {
+	unsigned int state, val;
+
+	switch (argc) {
+	case 3:
+		/* Write a value */
+		val = simple_strtol(argv[2], NULL, 16);
+
+		if (strcmp(argv[1], "drawer1") == 0) {
+			inka_digio_set_output(val, 1);
+		} else if (strcmp(argv[1], "drawer2") == 0) {
+			inka_digio_set_output(val, 2);
+		} else if (strcmp(argv[1], "other") == 0)
+			inka_digio_set_output(val, 0);
+		else {
+			printf("Invalid argument: %s\n", argv[1]);
+			return -1;
+		}
+		/* fall through */
+	case 2:
+		/* Read a value */
+		state = inka_digin_get_input();
+
+		if (strcmp(argv[1], "drawer1") == 0) {
+			val = (state & DIGIN_DRAWER_SW1) >> (ffs(DIGIN_DRAWER_SW1) - 1);
+		} else if (strcmp(argv[1], "drawer2") == 0) {
+			val = (state & DIGIN_DRAWER_SW2) >> (ffs(DIGIN_DRAWER_SW2) - 1);
+		} else if (strcmp(argv[1], "other") == 0) {
+			val = ((state & DIGIN_KEYB_MASK) >> (ffs(DIGIN_KEYB_MASK) - 1))
+				| (state & DIGIN_TOUCHSCR_MASK) >> (ffs(DIGIN_TOUCHSCR_MASK) - 2);
+		} else {
+			printf("Invalid argument: %s\n", argv[1]);
+			return -1;
+		}
+		printf("exit code: 0x%X\n", val);
+		return 0;
+	default:
+		return cmd_usage(cmdtp);
+	}
+
+	return -1;
+}
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int ser_init(volatile struct mpc5xxx_psc *psc, int baudrate)
+{
+	unsigned long baseclk;
+	int div;
+
+	/* reset PSC */
+	out_8(&psc->command, PSC_SEL_MODE_REG_1);
+
+	/* select clock sources */
+
+	out_be16(&psc->psc_clock_select, 0);
+	baseclk = (gd->arch.ipb_clk + 16) / 32;
+
+	/* switch to UART mode */
+	out_be32(&psc->sicr, 0);
+
+	/* configure parity, bit length and so on */
+
+	out_8(&psc->mode, PSC_MODE_8_BITS | PSC_MODE_PARNONE);
+	out_8(&psc->mode, PSC_MODE_ONE_STOP);
+
+	/* set up UART divisor */
+	div = (baseclk + (baudrate / 2)) / baudrate;
+	out_8(&psc->ctur, (div >> 8) & 0xff);
+	out_8(&psc->ctlr, div & 0xff);
+
+	/* disable all interrupts */
+	out_be16(&psc->psc_imr, 0);
+
+	/* reset and enable Rx/Tx */
+	out_8(&psc->command, PSC_RST_RX);
+	out_8(&psc->command, PSC_RST_TX);
+	out_8(&psc->command, PSC_RX_ENABLE | PSC_TX_ENABLE);
+
+	return 0;
+}
+
+static void ser_putc(volatile struct mpc5xxx_psc *psc, const char c)
+{
+	/* Wait 1 second for last character to go. */
+	int i = 0;
+
+	while (!(psc->psc_status & PSC_SR_TXEMP) && (i++ < 1000000/10))
+		udelay(10);
+	psc->psc_buffer_8 = c;
+
+}
+
+static int ser_getc(volatile struct mpc5xxx_psc *psc)
+{
+	/* Wait for a character to arrive. */
+	int i = 0;
+
+	while (!(in_be16(&psc->psc_status) & PSC_SR_RXRDY) && (i++ < 1000000/10))
+		udelay(10);
+
+	return in_8(&psc->psc_buffer_8);
+}
+
+static int do_inkadiag_serial(cmd_tbl_t *cmdtp, int flag, int argc,
+			      char * const argv[]) {
+	volatile struct NS16550 *uart;
+	volatile struct mpc5xxx_psc *psc;
+	unsigned int num, mode;
+	int combrd, baudrate, i, j, len;
+	int address;
+
+	if (argc < 5)
+		return cmd_usage(cmdtp);
+
+	argc--;
+	argv++;
+
+	num = simple_strtol(argv[0], NULL, 0);
+	if (num < 0 || num > 11) {
+		printf("invalid argument for num: %d\n", num);
+		return -1;
+	}
+
+	mode = simple_strtol(argv[1], NULL, 0);
+
+	combrd = 0;
+	baudrate = simple_strtoul(argv[2], NULL, 10);
+	for (i=0; i<N_BAUDRATES; ++i) {
+		if (baudrate == baudrate_table[i])
+			break;
+	}
+	if (i == N_BAUDRATES) {
+		printf("## Baudrate %d bps not supported\n",
+		       baudrate);
+		return 1;
+	}
+	combrd = 115200 / baudrate;
+
+	uart = (struct NS16550 *)(SERIAL_PORT_BASE + (num << 3));
+
+	printf("Testing uart %d.\n\n", num);
+
+	if ((num >= 0) && (num <= 7)) {
+		if (mode & 1) {
+			/* turn on 'loopback' mode */
+			out_8(&uart->mcr, UART_MCR_LOOP);
+		} else {
+			/*
+			 * establish the UART's operational parameters
+			 * set DLAB=1, so rbr accesses DLL
+			 */
+			out_8(&uart->lcr, UART_LCR_DLAB);
+			/* set baudrate */
+			out_8(&uart->rbr, combrd);
+			/* set data-format: 8-N-1 */
+			out_8(&uart->lcr, UART_LCR_WLS_8);
+		}
+
+		if (mode & 2) {
+			/* set request to send */
+			out_8(&uart->mcr, UART_MCR_RTS);
+			udelay(10);
+			/* check clear to send */
+			if ((in_8(&uart->msr) & UART_MSR_CTS) == 0x00)
+				return -1;
+		}
+		if (mode & 4) {
+			/* set data terminal ready */
+			out_8(&uart->mcr, UART_MCR_DTR);
+			udelay(10);
+			/* check data set ready and carrier detect */
+			if ((in_8(&uart->msr) & (UART_MSR_DSR | UART_MSR_DCD))
+			    != (UART_MSR_DSR | UART_MSR_DCD))
+				return -1;
+		}
+
+		/* write each message-character, read it back, and display it */
+		for (i = 0, len = strlen(argv[3]); i < len; ++i) {
+			j = 0;
+			while ((in_8(&uart->lsr) & UART_LSR_THRE) ==	0x00) {
+				if (j++ > CONFIG_SYS_HZ)
+					break;
+				udelay(10);
+			}
+			out_8(&uart->rbr, argv[3][i]);
+			j = 0;
+			while ((in_8(&uart->lsr) & UART_LSR_DR) == 0x00) {
+				if (j++ > CONFIG_SYS_HZ)
+					break;
+				udelay(10);
+			}
+			printf("%c", in_8(&uart->rbr));
+		}
+		printf("\n\n");
+		out_8(&uart->mcr, 0x00);
+	} else {
+		address = 0;
+
+		switch (num) {
+		case 8:
+			address = MPC5XXX_PSC6;
+			break;
+		case 9:
+			address = MPC5XXX_PSC3;
+			break;
+		case 10:
+			address = MPC5XXX_PSC2;
+			break;
+		case 11:
+			address = MPC5XXX_PSC1;
+			break;
+		}
+		psc = (struct mpc5xxx_psc *)address;
+		ser_init(psc, simple_strtol(argv[2], NULL, 0));
+		if (mode & 2) {
+			/* set request to send */
+			out_8(&psc->op0, PSC_OP0_RTS);
+			udelay(10);
+			/* check clear to send */
+			if ((in_8(&psc->ip) & PSC_IPCR_CTS) == 0)
+				return -1;
+		}
+		len = strlen(argv[3]);
+		for (i = 0; i < len; ++i) {
+			ser_putc(psc, argv[3][i]);
+			printf("%c", ser_getc(psc));
+		}
+		printf("\n\n");
+	}
+	return 0;
+}
+
+#define BUZZER_GPT	(MPC5XXX_GPT + 0x60)	/* GPT6 */
+static void buzzer_turn_on(unsigned int freq)
+{
+	volatile struct mpc5xxx_gpt *gpt = (struct mpc5xxx_gpt *)(BUZZER_GPT);
+
+	const u32 prescale = gd->arch.ipb_clk / freq / 128;
+	const u32 count = 128;
+	const u32 width = 64;
+
+	gpt->cir = (prescale << 16) | count;
+	gpt->pwmcr = width << 16;
+	gpt->emsr = 3;		/* Timer enabled for PWM */
+}
+
+static void buzzer_turn_off(void)
+{
+	volatile struct mpc5xxx_gpt *gpt = (struct mpc5xxx_gpt *)(BUZZER_GPT);
+
+	gpt->emsr = 0;
+}
+
+static int do_inkadiag_buzzer(cmd_tbl_t *cmdtp, int flag, int argc,
+			      char * const argv[]) {
+
+	unsigned int period, freq;
+	int prev, i;
+
+	if (argc != 3)
+		return cmd_usage(cmdtp);
+
+	argc--;
+	argv++;
+
+	period = simple_strtol(argv[0], NULL, 0);
+	if (!period)
+		printf("Zero period is senseless\n");
+	argc--;
+	argv++;
+
+	freq = simple_strtol(argv[0], NULL, 0);
+	/* avoid zero prescale in buzzer_turn_on() */
+	if (freq > gd->arch.ipb_clk / 128) {
+		printf("%dHz exceeds maximum (%ldHz)\n", freq,
+		       gd->arch.ipb_clk / 128);
+	} else if (!freq)
+		printf("Zero frequency is senseless\n");
+	else
+		buzzer_turn_on(freq);
+
+	clear_ctrlc();
+	prev = disable_ctrlc(0);
+
+	printf("Buzzing for %d ms. Type ^C to abort!\n\n", period);
+
+	i = 0;
+	while (!ctrlc() && (i++ < CONFIG_SYS_HZ))
+		udelay(period);
+
+	clear_ctrlc();
+	disable_ctrlc(prev);
+
+	buzzer_turn_off();
+
+	return 0;
+}
+
+static int do_inkadiag_help(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
+
+cmd_tbl_t cmd_inkadiag_sub[] = {
+	U_BOOT_CMD_MKENT(io, 1, 1, do_inkadiag_io, "read digital input",
+	 "<drawer1|drawer2|other> [value] - get or set specified signal"),
+	U_BOOT_CMD_MKENT(serial, 4, 1, do_inkadiag_serial, "test serial port",
+	 "<num> <mode> <baudrate> <msg>  - test uart num [0..11] in mode\n"
+	 "and baudrate with msg"),
+	U_BOOT_CMD_MKENT(buzzer, 2, 1, do_inkadiag_buzzer, "activate buzzer",
+	 "<period> <freq> - turn buzzer on for period ms with freq hz"),
+	U_BOOT_CMD_MKENT(help, 4, 1, do_inkadiag_help, "get help",
+	 "[command] - get help for command"),
+};
+
+static int do_inkadiag_help(cmd_tbl_t *cmdtp, int flag,
+			    int argc, char * const argv[]) {
+	extern int _do_help (cmd_tbl_t *cmd_start, int cmd_items,
+			     cmd_tbl_t *cmdtp, int flag,
+			     int argc, char * const argv[]);
+	/* do_help prints command name - we prepend inkadiag to our subcommands! */
+#ifdef CONFIG_SYS_LONGHELP
+	puts ("inkadiag ");
+#endif
+	return _do_help(&cmd_inkadiag_sub[0],
+		ARRAY_SIZE(cmd_inkadiag_sub), cmdtp, flag, argc, argv);
+}
+
+static int do_inkadiag(cmd_tbl_t *cmdtp, int flag, int argc,
+		       char * const argv[]) {
+	cmd_tbl_t *c;
+
+	c = find_cmd_tbl(argv[1], &cmd_inkadiag_sub[0], ARRAY_SIZE(cmd_inkadiag_sub));
+
+	if (c) {
+		argc--;
+		argv++;
+		return c->cmd(c, flag, argc, argv);
+	} else {
+		/* Unrecognized command */
+		return cmd_usage(cmdtp);
+	}
+}
+
+U_BOOT_CMD(inkadiag, 6, 1, do_inkadiag,
+	   "inkadiag - inka diagnosis\n",
+	   "[inkadiag what ...]\n"
+	   "    - perform a diagnosis on inka hardware\n"
+	   "'inkadiag' performs hardware tests.");
diff --git a/board/inka4x0/k4h511638c.h b/board/inka4x0/k4h511638c.h
new file mode 100644
index 0000000000..054ddafd59
--- /dev/null
+++ b/board/inka4x0/k4h511638c.h
@@ -0,0 +1,16 @@ 
+/*
+ * Copyright (C) 2007 Semihalf
+ * Written by Marian Balakowicz <m8@semihalf.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#define SDRAM_DDR	1		/* is DDR */
+
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE	0x018D0000
+#define SDRAM_EMODE	0x40090000
+#define SDRAM_CONTROL	0x714F0F00
+#define SDRAM_CONFIG1	0x73722930
+#define SDRAM_CONFIG2	0x46770000
+#define SDRAM_TAPDELAY	0x10000000
diff --git a/board/inka4x0/mt46v16m16-75.h b/board/inka4x0/mt46v16m16-75.h
new file mode 100644
index 0000000000..23fc6f06be
--- /dev/null
+++ b/board/inka4x0/mt46v16m16-75.h
@@ -0,0 +1,16 @@ 
+/*
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#define SDRAM_DDR	1		/* is DDR */
+
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE	0x018D0000
+#define SDRAM_EMODE	0x40090000
+#define SDRAM_CONTROL	0x714F0F00
+#define SDRAM_CONFIG1	0x73722930
+#define SDRAM_CONFIG2	0x47770000
+#define SDRAM_TAPDELAY	0x10000000
diff --git a/board/inka4x0/mt46v32m16-75.h b/board/inka4x0/mt46v32m16-75.h
new file mode 100644
index 0000000000..f16f450d01
--- /dev/null
+++ b/board/inka4x0/mt46v32m16-75.h
@@ -0,0 +1,16 @@ 
+/*
+ * Copyright (C) 2007 Semihalf
+ * Written by Marian Balakowicz <m8@semihalf.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#define SDRAM_DDR	1		/* is DDR */
+
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE	0x018D0000
+#define SDRAM_EMODE	0x40090000
+#define SDRAM_CONTROL	0x714F0F00
+#define SDRAM_CONFIG1	0x73711930
+#define SDRAM_CONFIG2	0x46770000
+#define SDRAM_TAPDELAY	0x10000000
diff --git a/board/inka4x0/mt48lc16m16a2-75.h b/board/inka4x0/mt48lc16m16a2-75.h
new file mode 100644
index 0000000000..0133eaa2ca
--- /dev/null
+++ b/board/inka4x0/mt48lc16m16a2-75.h
@@ -0,0 +1,14 @@ 
+/*
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#define SDRAM_DDR	0		/* is SDR */
+
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE	0x00CD0000
+#define SDRAM_CONTROL	0x504F0000
+#define SDRAM_CONFIG1	0xD2322800
+#define SDRAM_CONFIG2	0x8AD70000
diff --git a/board/intercontrol/digsy_mtc/Kconfig b/board/intercontrol/digsy_mtc/Kconfig
new file mode 100644
index 0000000000..1cf2275d81
--- /dev/null
+++ b/board/intercontrol/digsy_mtc/Kconfig
@@ -0,0 +1,12 @@ 
+if TARGET_DIGSY_MTC
+
+config SYS_BOARD
+	default "digsy_mtc"
+
+config SYS_VENDOR
+	default "intercontrol"
+
+config SYS_CONFIG_NAME
+	default "digsy_mtc"
+
+endif
diff --git a/board/intercontrol/digsy_mtc/MAINTAINERS b/board/intercontrol/digsy_mtc/MAINTAINERS
new file mode 100644
index 0000000000..c83ebcdab9
--- /dev/null
+++ b/board/intercontrol/digsy_mtc/MAINTAINERS
@@ -0,0 +1,9 @@ 
+DIGSY_MTC BOARD
+M:	Werner Pfister <Pfister_Werner@intercontrol.de>
+S:	Maintained
+F:	board/intercontrol/digsy_mtc/
+F:	include/configs/digsy_mtc.h
+F:	configs/digsy_mtc_defconfig
+F:	configs/digsy_mtc_RAMBOOT_defconfig
+F:	configs/digsy_mtc_rev5_defconfig
+F:	configs/digsy_mtc_rev5_RAMBOOT_defconfig
diff --git a/board/intercontrol/digsy_mtc/Makefile b/board/intercontrol/digsy_mtc/Makefile
new file mode 100644
index 0000000000..4d13eadf5b
--- /dev/null
+++ b/board/intercontrol/digsy_mtc/Makefile
@@ -0,0 +1,8 @@ 
+#
+# Author: Grzegorz Bernacki, Semihalf, gjb@semihalf.com
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	:= digsy_mtc.o
+obj-$(CONFIG_VIDEO) += cmd_disp.o
diff --git a/board/intercontrol/digsy_mtc/cmd_disp.c b/board/intercontrol/digsy_mtc/cmd_disp.c
new file mode 100644
index 0000000000..2ffa8bfe40
--- /dev/null
+++ b/board/intercontrol/digsy_mtc/cmd_disp.c
@@ -0,0 +1,41 @@ 
+/*
+ * (C) Copyright 2011 DENX Software Engineering,
+ * Anatolij Gustschin <agust@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <mpc5xxx.h>
+#include <asm/io.h>
+
+#define GPIO_USB1_0	0x00010000
+
+static int cmd_disp(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
+
+	if (argc < 2) {
+		printf("%s\n",
+		       in_be32(&gpio->simple_dvo) & GPIO_USB1_0 ? "on" : "off");
+		return 0;
+	}
+
+	if (!strncmp(argv[1], "on", 2)) {
+		setbits_be32(&gpio->simple_dvo, GPIO_USB1_0);
+	} else if (!strncmp(argv[1], "off", 3)) {
+		clrbits_be32(&gpio->simple_dvo, GPIO_USB1_0);
+	} else {
+		cmd_usage(cmdtp);
+		return 1;
+	}
+	return 0;
+}
+
+U_BOOT_CMD(disp, 2, 1, cmd_disp,
+		"disp [on/off] - switch display on/off",
+		"\n    - print display on/off status\n"
+		"on\n    - turn on\n"
+		"off\n    - turn off\n"
+);
diff --git a/board/intercontrol/digsy_mtc/digsy_mtc.c b/board/intercontrol/digsy_mtc/digsy_mtc.c
new file mode 100644
index 0000000000..6c33eeb022
--- /dev/null
+++ b/board/intercontrol/digsy_mtc/digsy_mtc.c
@@ -0,0 +1,477 @@ 
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * (C) Copyright 2005-2009
+ * Modified for InterControl digsyMTC MPC5200 board by
+ * Frank Bodammer, GCD Hard- & Software GmbH,
+ *                 frank.bodammer@gcd-solutions.de
+ *
+ * (C) Copyright 2009
+ * Grzegorz Bernacki, Semihalf, gjb@semihalf.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <net.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include "eeprom.h"
+#if defined(CONFIG_DIGSY_REV5)
+#include "is45s16800a2.h"
+#include <mtd/cfi_flash.h>
+#include <flash.h>
+#else
+#include "is42s16800a-7t.h"
+#endif
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <i2c.h>
+#include <mb862xx.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern int usb_cpu_init(void);
+
+#if defined(CONFIG_DIGSY_REV5)
+/*
+ * The M29W128GH needs a special reset command function,
+ * details see the doc/README.cfi file
+ */
+void flash_cmd_reset(flash_info_t *info)
+{
+	flash_write_cmd(info, 0, 0, AMD_CMD_RESET);
+}
+#endif
+
+#ifndef CONFIG_SYS_RAMBOOT
+static void sdram_start(int hi_addr)
+{
+	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
+	long control = SDRAM_CONTROL | hi_addr_bit;
+
+	/* unlock mode register */
+	out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000000);
+
+	/* precharge all banks */
+	out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000002);
+
+	/* auto refresh */
+	out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000004);
+
+	/* set mode register */
+	out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_MODE);
+
+	/* normal operation */
+	out_be32((void *)MPC5XXX_SDRAM_CTRL, control);
+}
+#endif
+
+/*
+ * ATTENTION: Although partially referenced dram_init does NOT make real use
+ *            use of CONFIG_SYS_SDRAM_BASE. The code does not work if
+ *            CONFIG_SYS_SDRAM_BASE is something other than 0x00000000.
+ */
+
+int dram_init(void)
+{
+	ulong dramsize = 0;
+	ulong dramsize2 = 0;
+	uint svr, pvr;
+#ifndef CONFIG_SYS_RAMBOOT
+	ulong test1, test2;
+
+	/* setup SDRAM chip selects */
+	out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0x0000001C); /* 512MB at 0x0 */
+	out_be32((void *)MPC5XXX_SDRAM_CS1CFG, 0x80000000); /* disabled */
+
+	/* setup config registers */
+	out_be32((void *)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1);
+	out_be32((void *)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2);
+
+	/* find RAM size using SDRAM CS0 only */
+	sdram_start(0);
+	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x08000000);
+	sdram_start(1);
+	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x08000000);
+	if (test1 > test2) {
+		sdram_start(0);
+		dramsize = test1;
+	} else {
+		dramsize = test2;
+	}
+
+	/* memory smaller than 1MB is impossible */
+	if (dramsize < (1 << 20))
+		dramsize = 0;
+
+	/* set SDRAM CS0 size according to the amount of RAM found */
+	if (dramsize > 0) {
+		out_be32((void *)MPC5XXX_SDRAM_CS0CFG,
+			(0x13 + __builtin_ffs(dramsize >> 20) - 1));
+	} else {
+		out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0); /* disabled */
+	}
+
+	/* let SDRAM CS1 start right after CS0 */
+	out_be32((void *)MPC5XXX_SDRAM_CS1CFG, dramsize + 0x0000001C);
+
+	/* find RAM size using SDRAM CS1 only */
+	test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize),
+			0x08000000);
+		dramsize2 = test1;
+
+	/* memory smaller than 1MB is impossible */
+	if (dramsize2 < (1 << 20))
+		dramsize2 = 0;
+
+	/* set SDRAM CS1 size according to the amount of RAM found */
+	if (dramsize2 > 0) {
+		out_be32((void *)MPC5XXX_SDRAM_CS1CFG, (dramsize |
+			(0x13 + __builtin_ffs(dramsize2 >> 20) - 1)));
+	} else {
+		out_be32((void *)MPC5XXX_SDRAM_CS1CFG, dramsize); /* disabled */
+	}
+
+#else /* CONFIG_SYS_RAMBOOT */
+
+	/* retrieve size of memory connected to SDRAM CS0 */
+	dramsize = in_be32((void *)MPC5XXX_SDRAM_CS0CFG) & 0xFF;
+	if (dramsize >= 0x13)
+		dramsize = (1 << (dramsize - 0x13)) << 20;
+	else
+		dramsize = 0;
+
+	/* retrieve size of memory connected to SDRAM CS1 */
+	dramsize2 = in_be32((void *)MPC5XXX_SDRAM_CS1CFG) & 0xFF;
+	if (dramsize2 >= 0x13)
+		dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
+	else
+		dramsize2 = 0;
+
+#endif /* CONFIG_SYS_RAMBOOT */
+
+	/*
+	 * On MPC5200B we need to set the special configuration delay in the
+	 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
+	 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
+	 *
+	 * "The SDelay should be written to a value of 0x00000004. It is
+	 * required to account for changes caused by normal wafer processing
+	 * parameters."
+	 */
+	svr = get_svr();
+	pvr = get_pvr();
+	if ((SVR_MJREV(svr) >= 2) &&
+	    (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4))
+		out_be32((void *)MPC5XXX_SDRAM_SDELAY, 0x04);
+
+	gd->ram_size = dramsize + dramsize2;
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	char buf[64];
+	int i = getenv_f("serial#", buf, sizeof(buf));
+
+	puts ("Board: InterControl digsyMTC");
+#if defined(CONFIG_DIGSY_REV5)
+	puts (" rev5");
+#endif
+	if (i > 0) {
+		puts(", ");
+		puts(buf);
+	}
+	putc('\n');
+
+	return 0;
+}
+
+#if defined(CONFIG_VIDEO)
+
+#define GPIO_USB1_0		0x00010000	/* Power-On pin */
+#define GPIO_USB1_9		0x08		/* PX_~EN pin */
+
+#define GPIO_EE_DO		0x10		/* PSC6_0 (DO) pin */
+#define GPIO_EE_CTS		0x20		/* PSC6_1 (CTS) pin */
+#define GPIO_EE_DI		0x10000000	/* PSC6_2 (DI) pin */
+#define GPIO_EE_CLK		0x20000000	/* PSC6_3 (CLK) pin */
+
+#define GPT_GPIO_ON		0x00000034	/* GPT as simple GPIO, high */
+
+static void exbo_hw_init(void)
+{
+	struct mpc5xxx_gpt *gpt = (struct mpc5xxx_gpt *)MPC5XXX_GPT;
+	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
+	struct mpc5xxx_wu_gpio *wu_gpio =
+				(struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
+
+	/* configure IrDA pins (PSC6 port) as gpios */
+	gpio->port_config &= 0xFF8FFFFF;
+
+	/* Init for USB1_0, EE_CLK and EE_DI - Low */
+	setbits_be32(&gpio->simple_ddr,
+			GPIO_USB1_0 | GPIO_EE_CLK | GPIO_EE_DI);
+	clrbits_be32(&gpio->simple_ode,
+			GPIO_USB1_0 | GPIO_EE_CLK | GPIO_EE_DI);
+	clrbits_be32(&gpio->simple_dvo,
+			GPIO_USB1_0 | GPIO_EE_CLK | GPIO_EE_DI);
+	setbits_be32(&gpio->simple_gpioe,
+			GPIO_USB1_0 | GPIO_EE_CLK | GPIO_EE_DI);
+
+	/* Init for EE_DO, EE_CTS - Input */
+	clrbits_8(&wu_gpio->ddr, GPIO_EE_DO | GPIO_EE_CTS);
+	setbits_8(&wu_gpio->enable, GPIO_EE_DO | GPIO_EE_CTS);
+
+	/* Init for PX_~EN (USB1_9) - High */
+	clrbits_8(&gpio->sint_ode, GPIO_USB1_9);
+	setbits_8(&gpio->sint_ddr, GPIO_USB1_9);
+	clrbits_8(&gpio->sint_inten, GPIO_USB1_9);
+	setbits_8(&gpio->sint_dvo, GPIO_USB1_9);
+	setbits_8(&gpio->sint_gpioe, GPIO_USB1_9);
+
+	/* Init for ~OE Switch (GPIO3) - Timer_0 GPIO High */
+	out_be32(&gpt[0].emsr, GPT_GPIO_ON);
+	/* Init for S Switch (GPIO4) - Timer_1 GPIO High */
+	out_be32(&gpt[1].emsr, GPT_GPIO_ON);
+
+	/* Power-On camera supply */
+	setbits_be32(&gpio->simple_dvo, GPIO_USB1_0);
+}
+#else
+static inline void exbo_hw_init(void) {}
+#endif /* CONFIG_VIDEO */
+
+int board_early_init_r(void)
+{
+	/*
+	 * Now, when we are in RAM, enable flash write access for detection
+	 * process.  Note that CS_BOOT cannot be cleared when executing in
+	 * flash.
+	 */
+	/* disable CS_BOOT */
+	clrbits_be32((void *)MPC5XXX_ADDECR, (1 << 25));
+	/* enable CS1 */
+	setbits_be32((void *)MPC5XXX_ADDECR, (1 << 17));
+	/* enable CS0 */
+	setbits_be32((void *)MPC5XXX_ADDECR, (1 << 16));
+
+#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT)
+	/* Low level USB init, required for proper kernel operation */
+	usb_cpu_init();
+#endif
+
+	return (0);
+}
+
+void board_get_enetaddr (uchar * enet)
+{
+	ushort read = 0;
+	ushort addr_of_eth_addr = 0;
+	ushort len_sys = 0;
+	ushort len_sys_cfg = 0;
+
+	/* check identification word */
+	eeprom_read(EEPROM_ADDR, EEPROM_ADDR_IDENT, (uchar *)&read, 2);
+	if (read != EEPROM_IDENT)
+		return;
+
+	/* calculate offset of config area */
+	eeprom_read(EEPROM_ADDR, EEPROM_ADDR_LEN_SYS, (uchar *)&len_sys, 2);
+	eeprom_read(EEPROM_ADDR, EEPROM_ADDR_LEN_SYSCFG,
+		(uchar *)&len_sys_cfg, 2);
+	addr_of_eth_addr = (len_sys + len_sys_cfg + EEPROM_ADDR_ETHADDR) << 1;
+	if (addr_of_eth_addr >= EEPROM_LEN)
+		return;
+
+	eeprom_read(EEPROM_ADDR, addr_of_eth_addr, enet, 6);
+}
+
+int misc_init_r(void)
+{
+	pci_dev_t devbusfn;
+	uchar enetaddr[6];
+
+	/* check if graphic extension board is present */
+	devbusfn = pci_find_device(PCI_VENDOR_ID_FUJITSU,
+				   PCI_DEVICE_ID_CORAL_PA, 0);
+	if (devbusfn != -1)
+		exbo_hw_init();
+
+	if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
+		board_get_enetaddr(enetaddr);
+		eth_setenv_enetaddr("ethaddr", enetaddr);
+	}
+
+	return 0;
+}
+
+#ifdef CONFIG_PCI
+static struct pci_controller hose;
+
+extern void pci_mpc5xxx_init(struct pci_controller *);
+
+void pci_init_board(void)
+{
+	pci_mpc5xxx_init(&hose);
+}
+#endif
+
+#ifdef CONFIG_IDE
+
+#ifdef CONFIG_IDE_RESET
+
+void init_ide_reset(void)
+{
+	debug ("init_ide_reset\n");
+
+	/* set gpio output value to 1 */
+	setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, (1 << 25));
+	/* open drain output */
+	setbits_be32((void *)MPC5XXX_WU_GPIO_ODE, (1 << 25));
+	/* direction output */
+	setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, (1 << 25));
+	/* enable gpio */
+	setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, (1 << 25));
+
+}
+
+void ide_set_reset(int idereset)
+{
+	debug ("ide_reset(%d)\n", idereset);
+
+	/* set gpio output value to 0 */
+	clrbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, (1 << 25));
+	/* open drain output */
+	setbits_be32((void *)MPC5XXX_WU_GPIO_ODE, (1 << 25));
+	/* direction output */
+	setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, (1 << 25));
+	/* enable gpio */
+	setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, (1 << 25));
+
+	udelay(10000);
+
+	/* set gpio output value to 1 */
+	setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, (1 << 25));
+	/* open drain output */
+	setbits_be32((void *)MPC5XXX_WU_GPIO_ODE, (1 << 25));
+	/* direction output */
+	setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, (1 << 25));
+	/* enable gpio */
+	setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, (1 << 25));
+}
+#endif /* CONFIG_IDE_RESET */
+#endif /* CONFIG_IDE */
+
+#ifdef CONFIG_OF_BOARD_SETUP
+static void ft_delete_node(void *fdt, const char *compat)
+{
+	int off = -1;
+	int ret;
+
+	off = fdt_node_offset_by_compatible(fdt, -1, compat);
+	if (off < 0) {
+		printf("Could not find %s node.\n", compat);
+		return;
+	}
+
+	ret = fdt_del_node(fdt, off);
+	if (ret < 0)
+		printf("Could not delete %s node.\n", compat);
+}
+#if defined(CONFIG_SYS_UPDATE_FLASH_SIZE)
+static void ft_adapt_flash_base(void *blob)
+{
+	flash_info_t	*dev = &flash_info[0];
+	int off;
+	struct fdt_property *prop;
+	int len;
+	u32 *reg, *reg2;
+
+	off = fdt_node_offset_by_compatible(blob, -1, "fsl,mpc5200b-lpb");
+	if (off < 0) {
+		printf("Could not find fsl,mpc5200b-lpb node.\n");
+		return;
+	}
+
+	/* found compatible property */
+	prop = fdt_get_property_w(blob, off, "ranges", &len);
+	if (prop) {
+		reg = reg2 = (u32 *)&prop->data[0];
+
+		reg[2] = dev->start[0];
+		reg[3] = dev->size;
+		fdt_setprop(blob, off, "ranges", reg2, len);
+	} else
+		printf("Could not find ranges\n");
+}
+
+extern ulong flash_get_size (phys_addr_t base, int banknum);
+
+/* Update the Flash Baseaddr settings */
+int update_flash_size (int flash_size)
+{
+	volatile struct mpc5xxx_mmap_ctl *mm =
+		(struct mpc5xxx_mmap_ctl *) CONFIG_SYS_MBAR;
+	flash_info_t	*dev;
+	int	i;
+	int size = 0;
+	unsigned long base = 0x0;
+	u32 *cs_reg = (u32 *)&mm->cs0_start;
+
+	for (i = 0; i < 2; i++) {
+		dev = &flash_info[i];
+
+		if (dev->size) {
+			/* calculate new base addr for this chipselect */
+			base -= dev->size;
+			out_be32(cs_reg, START_REG(base));
+			cs_reg++;
+			out_be32(cs_reg, STOP_REG(base, dev->size));
+			cs_reg++;
+			/* recalculate the sectoraddr in the cfi driver */
+			size += flash_get_size(base, i);
+		}
+	}
+	flash_protect_default();
+	gd->bd->bi_flashstart = base;
+	return 0;
+}
+#endif /* defined(CONFIG_SYS_UPDATE_FLASH_SIZE) */
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+	int phy_addr = CONFIG_PHY_ADDR;
+	char eth_path[] = "/soc5200@f0000000/mdio@3000/ethernet-phy@0";
+
+	ft_cpu_setup(blob, bd);
+	/*
+	 * There are 2 RTC nodes in the DTS, so remove
+	 * the unneeded node here.
+	 */
+#if defined(CONFIG_DIGSY_REV5)
+	ft_delete_node(blob, "dallas,ds1339");
+#else
+	ft_delete_node(blob, "mc,rv3029c2");
+#endif
+#if defined(CONFIG_SYS_UPDATE_FLASH_SIZE)
+#ifdef CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
+	/* Update reg property in all nor flash nodes too */
+	fdt_fixup_nor_flash_size(blob);
+#endif
+	ft_adapt_flash_base(blob);
+#endif
+	/* fix up the phy address */
+	do_fixup_by_path(blob, eth_path, "reg", &phy_addr, sizeof(int), 0);
+
+	return 0;
+}
+#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/intercontrol/digsy_mtc/eeprom.h b/board/intercontrol/digsy_mtc/eeprom.h
new file mode 100644
index 0000000000..17bd034072
--- /dev/null
+++ b/board/intercontrol/digsy_mtc/eeprom.h
@@ -0,0 +1,18 @@ 
+/*
+ * (C) Copyright 2009 Semihalf.
+ * Written by: Grzegorz Bernacki <gjb@semihalf.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef CMD_EEPROM_H
+#define CMD_EEPROM_H
+
+#define EEPROM_ADDR		CONFIG_SYS_I2C_EEPROM_ADDR
+#define EEPROM_LEN		1024	/* eeprom length */
+#define EEPROM_IDENT		2408	/* identification word */
+#define EEPROM_ADDR_IDENT	0	/* identification word offset */
+#define EEPROM_ADDR_LEN_SYS	2	/* system area lenght offset */
+#define EEPROM_ADDR_LEN_SYSCFG	4	/* system config area length offset */
+#define EEPROM_ADDR_ETHADDR	23	/* ethernet address offset */
+
+#endif
diff --git a/board/intercontrol/digsy_mtc/is42s16800a-7t.h b/board/intercontrol/digsy_mtc/is42s16800a-7t.h
new file mode 100644
index 0000000000..c555d2d623
--- /dev/null
+++ b/board/intercontrol/digsy_mtc/is42s16800a-7t.h
@@ -0,0 +1,11 @@ 
+/*
+ * (C) Copyright 2004-2009
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#define SDRAM_MODE	0x00CD0000
+#define SDRAM_CONTROL	0x505F0000
+#define SDRAM_CONFIG1	0xD2322900
+#define SDRAM_CONFIG2	0x8AD70000
diff --git a/board/intercontrol/digsy_mtc/is45s16800a2.h b/board/intercontrol/digsy_mtc/is45s16800a2.h
new file mode 100644
index 0000000000..c42ba38e34
--- /dev/null
+++ b/board/intercontrol/digsy_mtc/is45s16800a2.h
@@ -0,0 +1,15 @@ 
+/*
+ * (C) Copyright 2010
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * based on:
+ * (C) Copyright 2004-2009
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#define SDRAM_MODE	0x00CD0000
+#define SDRAM_CONTROL	0x50470000
+#define SDRAM_CONFIG1	0xD2322900
+#define SDRAM_CONFIG2	0x8AD70000
diff --git a/board/ipek01/Kconfig b/board/ipek01/Kconfig
new file mode 100644
index 0000000000..34e094d79d
--- /dev/null
+++ b/board/ipek01/Kconfig
@@ -0,0 +1,9 @@ 
+if TARGET_IPEK01
+
+config SYS_BOARD
+	default "ipek01"
+
+config SYS_CONFIG_NAME
+	default "ipek01"
+
+endif
diff --git a/board/ipek01/MAINTAINERS b/board/ipek01/MAINTAINERS
new file mode 100644
index 0000000000..906d39ef80
--- /dev/null
+++ b/board/ipek01/MAINTAINERS
@@ -0,0 +1,6 @@ 
+IPEK01 BOARD
+M:	Anatolij Gustschin <agust@denx.de>
+S:	Maintained
+F:	board/ipek01/
+F:	include/configs/ipek01.h
+F:	configs/ipek01_defconfig
diff --git a/board/ipek01/Makefile b/board/ipek01/Makefile
new file mode 100644
index 0000000000..a786ab2118
--- /dev/null
+++ b/board/ipek01/Makefile
@@ -0,0 +1,8 @@ 
+#
+# (C) Copyright 2003-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	:= ipek01.o
diff --git a/board/ipek01/ipek01.c b/board/ipek01/ipek01.c
new file mode 100644
index 0000000000..133db8c6bd
--- /dev/null
+++ b/board/ipek01/ipek01.c
@@ -0,0 +1,270 @@ 
+/*
+ * (C) Copyright 2003-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * (C) Copyright 2006
+ * MicroSys GmbH
+ *
+ * (C) Copyright 2009
+ * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <pci.h>
+#include <netdev.h>
+#include <miiphy.h>
+#include <libfdt.h>
+#include <mb862xx.h>
+#include <video_fb.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+
+#ifdef CONFIG_OF_LIBFDT
+#include <fdt_support.h>
+#endif /* CONFIG_OF_LIBFDT */
+
+/* mt46v16m16-75 */
+#ifdef CONFIG_MPC5200_DDR
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE	0x018D0000
+#define SDRAM_EMODE	0x40090000
+#define SDRAM_CONTROL	0x714f0f00
+#define SDRAM_CONFIG1	0x73722930
+#define SDRAM_CONFIG2	0x47770000
+#define SDRAM_TAPDELAY	0x10000000
+#else
+#error SDRAM is not supported on this board
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void sdram_start (int hi_addr)
+{
+	struct mpc5xxx_sdram *sdram = (struct mpc5xxx_sdram *)MPC5XXX_SDRAM;
+	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
+
+	/* unlock mode register */
+	out_be32 (&sdram->ctrl, SDRAM_CONTROL | 0x80000000 | hi_addr_bit);
+
+	/* precharge all banks */
+	out_be32 (&sdram->ctrl, SDRAM_CONTROL | 0x80000002 | hi_addr_bit);
+
+	/* set mode register: extended mode */
+	out_be32 (&sdram->mode, SDRAM_EMODE);
+
+	/* set mode register: reset DLL */
+	out_be32 (&sdram->mode, SDRAM_MODE | 0x04000000);
+
+	/* precharge all banks */
+	out_be32 (&sdram->ctrl, SDRAM_CONTROL | 0x80000002 | hi_addr_bit);
+
+	/* auto refresh */
+	out_be32 (&sdram->ctrl, SDRAM_CONTROL | 0x80000004 | hi_addr_bit);
+
+	/* set mode register */
+	out_be32 (&sdram->mode, SDRAM_MODE);
+
+	/* normal operation */
+	out_be32 (&sdram->ctrl, SDRAM_CONTROL | hi_addr_bit);
+}
+
+/*
+ * ATTENTION: Although partially referenced dram_init does NOT make real
+ *	      use of CONFIG_SYS_SDRAM_BASE. The code does not work if
+ *	      CONFIG_SYS_SDRAM_BASE is something else than 0x00000000.
+ */
+
+int dram_init(void)
+{
+	struct mpc5xxx_mmap_ctl *mmap_ctl =
+		(struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR;
+	struct mpc5xxx_sdram *sdram = (struct mpc5xxx_sdram *)MPC5XXX_SDRAM;
+	struct mpc5xxx_cdm *cdm = (struct mpc5xxx_cdm *)MPC5XXX_CDM;
+	ulong dramsize = 0;
+	ulong dramsize2 = 0;
+	ulong test1, test2;
+
+	/* setup SDRAM chip selects */
+	out_be32 (&mmap_ctl->sdram0, 0x0000001e);	/* 2G at 0x0 */
+	out_be32 (&mmap_ctl->sdram1, 0x00000000);	/* disabled */
+
+	/* setup config registers */
+	out_be32 (&sdram->config1, SDRAM_CONFIG1);
+	out_be32 (&sdram->config2, SDRAM_CONFIG2);
+
+	/* set tap delay */
+	out_be32 (&cdm->porcfg, SDRAM_TAPDELAY);
+
+	/* find RAM size using SDRAM CS0 only */
+	sdram_start (0);
+	test1 = get_ram_size ((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
+	sdram_start (1);
+	test2 = get_ram_size ((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
+	if (test1 > test2) {
+		sdram_start (0);
+		dramsize = test1;
+	} else {
+		dramsize = test2;
+	}
+
+	/* memory smaller than 1MB is impossible */
+	if (dramsize < (1 << 20))
+		dramsize = 0;
+
+	/* set SDRAM CS0 size according to the amount of RAM found */
+	if (dramsize > 0)
+		out_be32 (&mmap_ctl->sdram0,
+			  0x13 + __builtin_ffs (dramsize >> 20) - 1);
+	else
+		out_be32 (&mmap_ctl->sdram1, 0);	/* disabled */
+
+	/*
+	 * On MPC5200B we need to set the special configuration delay in the
+	 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
+	 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
+	 *
+	 * "The SDelay should be written to a value of 0x00000004. It is
+	 * required to account for changes caused by normal wafer processing
+	 * parameters."
+	 */
+	out_be32 (&sdram->sdelay, 0x04);
+
+	gd->ram_size = dramsize + dramsize2;
+
+	return 0;
+}
+
+int checkboard (void)
+{
+	puts ("Board: IPEK01 \n");
+	return 0;
+}
+
+void flash_preinit (void)
+{
+	struct mpc5xxx_lpb *lpb = (struct mpc5xxx_lpb *)MPC5XXX_LPB;
+
+	/*
+	 * Now, when we are in RAM, enable flash write
+	 * access for detection process.
+	 * Note that CS_BOOT cannot be cleared when
+	 * executing in flash.
+	 */
+	clrbits_be32 (&lpb->cs0_cfg, 0x1);	/* clear RO */
+}
+
+void flash_afterinit (ulong start, ulong size)
+{
+	struct mpc5xxx_mmap_ctl *mmap_ctl =
+		(struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR;
+
+#if defined(CONFIG_BOOT_ROM)
+	/* adjust mapping */
+	out_be32 (&mmap_ctl->cs1_start, START_REG (start));
+	out_be32 (&mmap_ctl->cs1_stop, STOP_REG (start, size));
+#else
+	/* adjust mapping */
+	out_be32 (&mmap_ctl->boot_start, START_REG (start));
+	out_be32 (&mmap_ctl->cs0_start, START_REG (start));
+	out_be32 (&mmap_ctl->boot_stop, STOP_REG (start, size));
+	out_be32 (&mmap_ctl->cs0_stop, STOP_REG (start, size));
+#endif
+}
+
+extern flash_info_t flash_info[];	/* info for FLASH chips */
+
+int misc_init_r (void)
+{
+	/* adjust flash start */
+	gd->bd->bi_flashstart = flash_info[0].start[0];
+	return (0);
+}
+
+#ifdef	CONFIG_PCI
+static struct pci_controller hose;
+
+extern void pci_mpc5xxx_init (struct pci_controller *);
+
+void pci_init_board (void)
+{
+	pci_mpc5xxx_init (&hose);
+}
+#endif
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, bd_t *bd)
+{
+	ft_cpu_setup (blob, bd);
+	fdt_fixup_memory (blob, (u64) bd->bi_memstart, (u64) bd->bi_memsize);
+
+	return 0;
+}
+#endif /* CONFIG_OF_BOARD_SETUP */
+
+int board_eth_init(bd_t *bis)
+{
+	cpu_eth_init(bis); /* Built in FEC comes first */
+	return pci_eth_init(bis);
+}
+
+#ifdef CONFIG_VIDEO
+extern GraphicDevice mb862xx;
+
+static const gdc_regs init_regs[] = {
+	{0x0100, 0x00000900},
+	{0x0020, 0x80190257},
+	{0x0024, 0x00000000},
+	{0x0028, 0x00000000},
+	{0x002c, 0x00000000},
+	{0x0110, 0x00000000},
+	{0x0114, 0x00000000},
+	{0x0118, 0x02570320},
+	{0x0004, 0x041f0000},
+	{0x0008, 0x031f031f},
+	{0x000c, 0x067f0347},
+	{0x0010, 0x02780000},
+	{0x0014, 0x0257025c},
+	{0x0018, 0x00000000},
+	{0x001c, 0x02570320},
+	{0x0100, 0x80010900},
+	{0x0, 0x0}
+};
+
+const gdc_regs *board_get_regs (void)
+{
+	return init_regs;
+}
+
+/* Returns Lime base address */
+unsigned int board_video_init (void)
+{
+	if (mb862xx_probe (CONFIG_SYS_LIME_BASE) != MB862XX_TYPE_LIME)
+		return 0;
+
+	mb862xx.winSizeX = 800;
+	mb862xx.winSizeY = 600;
+	mb862xx.gdfIndex = GDF_15BIT_555RGB;
+	mb862xx.gdfBytesPP = 2;
+
+	return CONFIG_SYS_LIME_BASE;
+}
+
+#if defined(CONFIG_CONSOLE_EXTRA_INFO)
+/*
+ * Return text to be printed besides the logo.
+ */
+void video_get_info_str (int line_number, char *info)
+{
+	if (line_number == 1)
+		strcpy (info, " Board: IPEK01");
+	else
+		info[0] = '\0';
+}
+#endif
+#endif /* CONFIG_VIDEO */
diff --git a/board/jupiter/Kconfig b/board/jupiter/Kconfig
new file mode 100644
index 0000000000..d71acbbc4d
--- /dev/null
+++ b/board/jupiter/Kconfig
@@ -0,0 +1,9 @@ 
+if TARGET_JUPITER
+
+config SYS_BOARD
+	default "jupiter"
+
+config SYS_CONFIG_NAME
+	default "jupiter"
+
+endif
diff --git a/board/jupiter/MAINTAINERS b/board/jupiter/MAINTAINERS
new file mode 100644
index 0000000000..5a79a616cc
--- /dev/null
+++ b/board/jupiter/MAINTAINERS
@@ -0,0 +1,6 @@ 
+JUPITER BOARD
+M:	Heiko Schocher <hs@denx.de>
+S:	Maintained
+F:	board/jupiter/
+F:	include/configs/jupiter.h
+F:	configs/jupiter_defconfig
diff --git a/board/jupiter/Makefile b/board/jupiter/Makefile
new file mode 100644
index 0000000000..4d3ef9ed7a
--- /dev/null
+++ b/board/jupiter/Makefile
@@ -0,0 +1,8 @@ 
+#
+# (C) Copyright 2003-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	:= jupiter.o
diff --git a/board/jupiter/jupiter.c b/board/jupiter/jupiter.c
new file mode 100644
index 0000000000..52d2766e9a
--- /dev/null
+++ b/board/jupiter/jupiter.c
@@ -0,0 +1,296 @@ 
+/*
+ * (C) Copyright 2007
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <libfdt.h>
+
+#define SDRAM_DDR	0
+#if 1
+/* Settings Icecube */
+#define SDRAM_MODE	0x00CD0000
+#define SDRAM_CONTROL	0x504F0000
+#define SDRAM_CONFIG1	0xD2322800
+#define SDRAM_CONFIG2	0x8AD70000
+#else
+/*Settings Jupiter UB 1.0.0 */
+#define SDRAM_MODE	0x008D0000
+#define SDRAM_CONTROL	0xD04F0000
+#define SDRAM_CONFIG1	0xf7277f00
+#define SDRAM_CONFIG2	0x88b70004
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifndef CONFIG_SYS_RAMBOOT
+static void sdram_start (int hi_addr)
+{
+	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
+
+	/* unlock mode register */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* precharge all banks */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+#if SDRAM_DDR
+	/* set mode register: extended mode */
+	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
+	__asm__ volatile ("sync");
+
+	/* set mode register: reset DLL */
+	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
+	__asm__ volatile ("sync");
+#endif
+
+	/* precharge all banks */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* auto refresh */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* set mode register */
+	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
+	__asm__ volatile ("sync");
+
+	/* normal operation */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
+	__asm__ volatile ("sync");
+}
+#endif
+
+/*
+ * ATTENTION: Although partially referenced dram_init does NOT make real use
+ *            use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
+ *            is something else than 0x00000000.
+ */
+
+int dram_init(void)
+{
+	ulong dramsize = 0;
+	ulong dramsize2 = 0;
+	uint svr, pvr;
+
+#ifndef CONFIG_SYS_RAMBOOT
+	ulong test1, test2;
+
+	/* setup SDRAM chip selects */
+	*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
+	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
+	__asm__ volatile ("sync");
+
+	/* setup config registers */
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
+	__asm__ volatile ("sync");
+
+#if SDRAM_DDR
+	/* set tap delay */
+	*(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
+	__asm__ volatile ("sync");
+#endif
+
+	/* find RAM size using SDRAM CS0 only */
+	sdram_start(0);
+	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
+	sdram_start(1);
+	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
+	if (test1 > test2) {
+		sdram_start(0);
+		dramsize = test1;
+	} else {
+		dramsize = test2;
+	}
+
+	/* memory smaller than 1MB is impossible */
+	if (dramsize < (1 << 20)) {
+		dramsize = 0;
+	}
+
+	/* set SDRAM CS0 size according to the amount of RAM found */
+	if (dramsize > 0) {
+		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
+	} else {
+		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
+	}
+
+	/* let SDRAM CS1 start right after CS0 */
+	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
+
+	/* find RAM size using SDRAM CS1 only */
+	if (!dramsize)
+		sdram_start(0);
+	test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
+	if (!dramsize) {
+		sdram_start(1);
+		test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
+	}
+	if (test1 > test2) {
+		sdram_start(0);
+		dramsize2 = test1;
+	} else {
+		dramsize2 = test2;
+	}
+
+	/* memory smaller than 1MB is impossible */
+	if (dramsize2 < (1 << 20)) {
+		dramsize2 = 0;
+	}
+
+	/* set SDRAM CS1 size according to the amount of RAM found */
+	if (dramsize2 > 0) {
+		*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
+			| (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
+	} else {
+		*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
+	}
+
+#else /* CONFIG_SYS_RAMBOOT */
+
+	/* retrieve size of memory connected to SDRAM CS0 */
+	dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
+	if (dramsize >= 0x13) {
+		dramsize = (1 << (dramsize - 0x13)) << 20;
+	} else {
+		dramsize = 0;
+	}
+
+	/* retrieve size of memory connected to SDRAM CS1 */
+	dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
+	if (dramsize2 >= 0x13) {
+		dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
+	} else {
+		dramsize2 = 0;
+	}
+
+#endif /* CONFIG_SYS_RAMBOOT */
+
+	/*
+	 * On MPC5200B we need to set the special configuration delay in the
+	 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
+	 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
+	 *
+	 * "The SDelay should be written to a value of 0x00000004. It is
+	 * required to account for changes caused by normal wafer processing
+	 * parameters."
+	 */
+	svr = get_svr();
+	pvr = get_pvr();
+	if ((SVR_MJREV(svr) >= 2) &&
+	    (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
+
+		*(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
+		__asm__ volatile ("sync");
+	}
+
+	gd->ram_size = dramsize + dramsize2;
+
+	return 0;
+}
+
+int checkboard (void)
+{
+	puts ("Board: Sauter (Jupiter)\n");
+	return 0;
+}
+
+void flash_preinit(void)
+{
+	/*
+	 * Now, when we are in RAM, enable flash write
+	 * access for detection process.
+	 * Note that CS_BOOT cannot be cleared when
+	 * executing in flash.
+	 */
+	*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
+}
+
+int board_early_init_r (void)
+{
+	flash_preinit ();
+	return 0;
+}
+
+void flash_afterinit(ulong size)
+{
+	if (size == 0x1000000) { /* adjust mapping */
+		*(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START =
+			START_REG(CONFIG_SYS_BOOTCS_START | size);
+		*(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP =
+			STOP_REG(CONFIG_SYS_BOOTCS_START | size, size);
+	}
+	*(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */
+	*(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */
+}
+
+int update_flash_size (int flash_size)
+{
+	flash_afterinit (flash_size);
+	return 0;
+}
+
+int board_early_init_f (void)
+{
+	*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
+	return 0;
+}
+
+#ifdef	CONFIG_PCI
+static struct pci_controller hose;
+
+extern void pci_mpc5xxx_init(struct pci_controller *);
+
+void pci_init_board(void)
+{
+	pci_mpc5xxx_init(&hose);
+}
+#endif
+
+#if defined(CONFIG_IDE) && defined(CONFIG_IDE_RESET)
+
+void init_ide_reset (void)
+{
+	debug ("init_ide_reset\n");
+
+	/* Configure PSC1_4 as GPIO output for ATA reset */
+	*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
+	*(vu_long *) MPC5XXX_WU_GPIO_DIR    |= GPIO_PSC1_4;
+	/* Deassert reset */
+	*(vu_long *) MPC5XXX_WU_GPIO_DATA_O   |= GPIO_PSC1_4;
+}
+
+void ide_set_reset (int idereset)
+{
+	debug ("ide_reset(%d)\n", idereset);
+
+	if (idereset) {
+		*(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
+		/* Make a delay. MPC5200 spec says 25 usec min */
+		udelay(500000);
+	} else {
+		*(vu_long *) MPC5XXX_WU_GPIO_DATA_O |=  GPIO_PSC1_4;
+	}
+}
+#endif
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, bd_t *bd)
+{
+	ft_cpu_setup(blob, bd);
+
+	return 0;
+}
+#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/motionpro/Kconfig b/board/motionpro/Kconfig
new file mode 100644
index 0000000000..f624f6c95f
--- /dev/null
+++ b/board/motionpro/Kconfig
@@ -0,0 +1,9 @@ 
+if TARGET_MOTIONPRO
+
+config SYS_BOARD
+	default "motionpro"
+
+config SYS_CONFIG_NAME
+	default "motionpro"
+
+endif
diff --git a/board/motionpro/MAINTAINERS b/board/motionpro/MAINTAINERS
new file mode 100644
index 0000000000..2f8b5cb580
--- /dev/null
+++ b/board/motionpro/MAINTAINERS
@@ -0,0 +1,6 @@ 
+MOTIONPRO BOARD
+#M:	-
+S:	Maintained
+F:	board/motionpro/
+F:	include/configs/motionpro.h
+F:	configs/motionpro_defconfig
diff --git a/board/motionpro/Makefile b/board/motionpro/Makefile
new file mode 100644
index 0000000000..898a384c39
--- /dev/null
+++ b/board/motionpro/Makefile
@@ -0,0 +1,8 @@ 
+#
+# (C) Copyright 2003-2007
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	:= motionpro.o
diff --git a/board/motionpro/motionpro.c b/board/motionpro/motionpro.c
new file mode 100644
index 0000000000..7883a179e8
--- /dev/null
+++ b/board/motionpro/motionpro.c
@@ -0,0 +1,243 @@ 
+/*
+ * (C) Copyright 2003-2007
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * modified for Promess PRO - by Andy Joseph, andy@promessdev.com
+ * modified for Promess PRO-Motion - by Robert McCullough, rob@promessdev.com
+ * modified by Chris M. Tumas 6/20/06 Change CAS latency to 2 from 3
+ * Also changed the refresh for 100MHz operation
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <miiphy.h>
+#include <libfdt.h>
+
+#if defined(CONFIG_LED_STATUS)
+#include <status_led.h>
+#endif /* CONFIG_LED_STATUS */
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Kollmorgen DPR initialization data */
+struct init_elem {
+	unsigned long addr;
+	unsigned len;
+	char *data;
+	} init_seq[] = {
+		{0x500003F2, 2, "\x86\x00"},		/* HW parameter */
+		{0x500003F0, 2, "\x00\x00"},
+		{0x500003EC, 4, "\x00\x80\xc1\x52"},	/* Magic word */
+	};
+
+/*
+ * Initialize Kollmorgen DPR
+ */
+static void kollmorgen_init(void)
+{
+	unsigned i, j;
+	vu_char *p;
+
+	for (i = 0; i < sizeof(init_seq) / sizeof(struct init_elem); ++i) {
+		p = (vu_char *)init_seq[i].addr;
+		for (j = 0; j < init_seq[i].len; ++j)
+			*(p + j) = *(init_seq[i].data + j);
+	}
+
+	printf("DPR:   Kollmorgen DPR initialized\n");
+}
+
+
+/*
+ * Early board initalization.
+ */
+int board_early_init_r(void)
+{
+	/* Now, when we are in RAM, disable Boot Chipselect and enable CS0 */
+	*(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25);
+	*(vu_long *)MPC5XXX_ADDECR |= (1 << 16);
+
+	/* Initialize Kollmorgen DPR */
+	kollmorgen_init();
+
+	return 0;
+}
+
+
+/*
+ * Additional PHY intialization. After being reset in mpc5xxx_fec_init_phy(),
+ * PHY goes into FX mode.  To take it out of the FX mode and switch into
+ * desired TX operation, one needs to clear the FX_SEL bit of Mode Control
+ * Register.
+ */
+void reset_phy(void)
+{
+	unsigned short mode_control;
+
+	miiphy_read("FEC", CONFIG_PHY_ADDR, 0x15, &mode_control);
+	miiphy_write("FEC", CONFIG_PHY_ADDR, 0x15,
+			mode_control & 0xfffe);
+	return;
+}
+
+#ifndef CONFIG_SYS_RAMBOOT
+/*
+ * Helper function to initialize SDRAM controller.
+ */
+static void sdram_start(int hi_addr)
+{
+	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
+
+	/* unlock mode register */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 |
+						hi_addr_bit;
+
+	/* precharge all banks */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
+						hi_addr_bit;
+
+	/* auto refresh */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 |
+						hi_addr_bit;
+
+	/* auto refresh, second time */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 |
+						hi_addr_bit;
+
+	/* set mode register */
+	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
+
+	/* normal operation */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
+}
+#endif /* !CONFIG_SYS_RAMBOOT */
+
+
+/*
+ * Initalize SDRAM - configure SDRAM controller, detect memory size.
+ */
+int dram_init(void)
+{
+	ulong dramsize = 0;
+#ifndef CONFIG_SYS_RAMBOOT
+	ulong test1, test2;
+
+	/* According to AN3221 (MPC5200B SDRAM Initialization and
+	 * Configuration), the SDelay register must be written a value of
+	 * 0x00000004 as the first step of the SDRAM contorller configuration.
+	 */
+	*(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
+
+	/* configure SDRAM start/end for detection */
+	*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */
+	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000; /* disabled */
+
+	/* setup config registers */
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
+
+	sdram_start(0);
+	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
+	sdram_start(1);
+	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
+	if (test1 > test2) {
+		sdram_start(0);
+		dramsize = test1;
+	} else {
+		dramsize = test2;
+	}
+
+	/* memory smaller than 1MB is impossible */
+	if (dramsize < (1 << 20))
+		dramsize = 0;
+
+	/* set SDRAM CS0 size according to the amount of RAM found */
+	if (dramsize > 0) {
+		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 +
+			__builtin_ffs(dramsize >> 20) - 1;
+	} else {
+		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
+	}
+
+	/* let SDRAM CS1 start right after CS0 and disable it */
+	*(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize;
+
+#else /* !CONFIG_SYS_RAMBOOT */
+	/* retrieve size of memory connected to SDRAM CS0 */
+	dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
+	if (dramsize >= 0x13)
+		dramsize = (1 << (dramsize - 0x13)) << 20;
+	else
+		dramsize = 0;
+#endif /* CONFIG_SYS_RAMBOOT */
+
+	/* return total ram size */
+	gd->ram_size = dramsize;
+
+	return 0;
+}
+
+
+int checkboard(void)
+{
+	uchar rev = *(vu_char *)CPLD_REV_REGISTER;
+	printf("Board: Promess Motion-PRO board (CPLD rev. 0x%02x)\n", rev);
+	return 0;
+}
+
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, bd_t *bd)
+{
+	ft_cpu_setup(blob, bd);
+
+	return 0;
+}
+#endif /* CONFIG_OF_BOARD_SETUP */
+
+
+#if defined(CONFIG_LED_STATUS)
+vu_long *regcode_to_regaddr(led_id_t regcode)
+{
+	/* GPT Enable and Mode Select Register address */
+	vu_long *reg_translate[] = {
+					(vu_long *)MPC5XXX_GPT6_ENABLE,
+					(vu_long *)MPC5XXX_GPT7_ENABLE,
+				   };
+
+	if (ARRAY_SIZE(reg_translate) <= regcode)
+		return NULL;
+	return reg_translate[regcode];
+}
+
+void __led_init(led_id_t regcode, int state)
+{
+	vu_long *regaddr = regcode_to_regaddr(regcode);
+
+	*regaddr |= ENABLE_GPIO_OUT;
+
+	if (state == CONFIG_LED_STATUS_ON)
+		*((vu_long *) regaddr) |= LED_ON;
+	else
+		*((vu_long *) regaddr) &= ~LED_ON;
+}
+
+void __led_set(led_id_t regcode, int state)
+{
+	vu_long *regaddr = regcode_to_regaddr(regcode);
+
+	if (state == CONFIG_LED_STATUS_ON)
+		*regaddr |= LED_ON;
+	else
+		*regaddr &= ~LED_ON;
+}
+
+void __led_toggle(led_id_t regcode)
+{
+	vu_long *regaddr = regcode_to_regaddr(regcode);
+
+	*regaddr ^= LED_ON;
+}
+#endif /* CONFIG_LED_STATUS */
diff --git a/board/munices/Kconfig b/board/munices/Kconfig
new file mode 100644
index 0000000000..019aaae3e9
--- /dev/null
+++ b/board/munices/Kconfig
@@ -0,0 +1,9 @@ 
+if TARGET_MUNICES
+
+config SYS_BOARD
+	default "munices"
+
+config SYS_CONFIG_NAME
+	default "munices"
+
+endif
diff --git a/board/munices/MAINTAINERS b/board/munices/MAINTAINERS
new file mode 100644
index 0000000000..50d3e7ebda
--- /dev/null
+++ b/board/munices/MAINTAINERS
@@ -0,0 +1,6 @@ 
+MUNICES BOARD
+#M:	-
+S:	Maintained
+F:	board/munices/
+F:	include/configs/munices.h
+F:	configs/munices_defconfig
diff --git a/board/munices/Makefile b/board/munices/Makefile
new file mode 100644
index 0000000000..d16e2a1fa2
--- /dev/null
+++ b/board/munices/Makefile
@@ -0,0 +1,8 @@ 
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	:= munices.o
diff --git a/board/munices/mt48lc16m16a2-75.h b/board/munices/mt48lc16m16a2-75.h
new file mode 100644
index 0000000000..0133eaa2ca
--- /dev/null
+++ b/board/munices/mt48lc16m16a2-75.h
@@ -0,0 +1,14 @@ 
+/*
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#define SDRAM_DDR	0		/* is SDR */
+
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE	0x00CD0000
+#define SDRAM_CONTROL	0x504F0000
+#define SDRAM_CONFIG1	0xD2322800
+#define SDRAM_CONFIG2	0x8AD70000
diff --git a/board/munices/munices.c b/board/munices/munices.c
new file mode 100644
index 0000000000..468eb3723e
--- /dev/null
+++ b/board/munices/munices.c
@@ -0,0 +1,159 @@ 
+/*
+ * (C) Copyright 2007
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <pci.h>
+
+#include "mt48lc16m16a2-75.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifndef CONFIG_SYS_RAMBOOT
+static void sdram_start (int hi_addr)
+{
+	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
+
+	/* unlock mode register */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* precharge all banks */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+#if SDRAM_DDR
+	/* set mode register: extended mode */
+	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
+	__asm__ volatile ("sync");
+
+	/* set mode register: reset DLL */
+	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
+	__asm__ volatile ("sync");
+#endif
+
+	/* precharge all banks */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* auto refresh */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* set mode register */
+	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
+	__asm__ volatile ("sync");
+
+	/* normal operation */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
+	__asm__ volatile ("sync");
+}
+#endif
+
+/*
+ * ATTENTION: Although partially referenced dram_init does NOT make real use
+ *            use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
+ *            is something else than 0x00000000.
+ */
+
+int dram_init(void)
+{
+	ulong dramsize = 0;
+	ulong dramsize2 = 0;
+#ifndef CONFIG_SYS_RAMBOOT
+	ulong test1, test2;
+
+	/* setup SDRAM chip selects */
+	*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001b;/* 256MB at 0x0 */
+	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x10000000;/* disabled */
+	__asm__ volatile ("sync");
+
+	/* setup config registers */
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
+	__asm__ volatile ("sync");
+
+#if SDRAM_DDR && SDRAM_TAPDELAY
+	/* set tap delay */
+	*(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
+	__asm__ volatile ("sync");
+#endif
+
+	/* find RAM size using SDRAM CS0 only */
+	sdram_start(0);
+	test1 = (ulong )get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x10000000);
+	sdram_start(1);
+	test2 = (ulong )get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x10000000);
+	if (test1 > test2) {
+		sdram_start(0);
+		dramsize = test1;
+	} else {
+		dramsize = test2;
+	}
+
+	/* memory smaller than 1MB is impossible */
+	if (dramsize < (1 << 20)) {
+		dramsize = 0;
+	}
+
+	/* set SDRAM CS0 size according to the amount of RAM found */
+	if (dramsize > 0) {
+		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
+	} else {
+		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
+	}
+
+#else /* CONFIG_SYS_RAMBOOT */
+
+	/* retrieve size of memory connected to SDRAM CS0 */
+	dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
+	if (dramsize >= 0x13) {
+		dramsize = (1 << (dramsize - 0x13)) << 20;
+	} else {
+		dramsize = 0;
+	}
+
+	/* retrieve size of memory connected to SDRAM CS1 */
+	dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
+	if (dramsize2 >= 0x13) {
+		dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
+	} else {
+		dramsize2 = 0;
+	}
+
+#endif /* CONFIG_SYS_RAMBOOT */
+
+	gd->ram_size = dramsize + dramsize2;
+
+	return 0;
+}
+
+int checkboard (void)
+{
+	puts ("Board: MUNICes\n");
+	return 0;
+}
+
+#ifdef	CONFIG_PCI
+static struct pci_controller hose;
+
+extern void pci_mpc5xxx_init(struct pci_controller *);
+
+void pci_init_board(void)
+{
+	pci_mpc5xxx_init(&hose);
+}
+#endif
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, bd_t *bd)
+{
+	ft_cpu_setup(blob, bd);
+
+	return 0;
+}
+#endif /* CONFIG_OF_BOARD_SETUP */
diff --git a/board/pdm360ng/Kconfig b/board/pdm360ng/Kconfig
new file mode 100644
index 0000000000..33173a0a2a
--- /dev/null
+++ b/board/pdm360ng/Kconfig
@@ -0,0 +1,9 @@ 
+if TARGET_PDM360NG
+
+config SYS_BOARD
+	default "pdm360ng"
+
+config SYS_CONFIG_NAME
+	default "pdm360ng"
+
+endif
diff --git a/board/pdm360ng/MAINTAINERS b/board/pdm360ng/MAINTAINERS
new file mode 100644
index 0000000000..5c99f59e8f
--- /dev/null
+++ b/board/pdm360ng/MAINTAINERS
@@ -0,0 +1,6 @@ 
+PDM360NG BOARD
+M:	Michael Weiss <michael.weiss@ifm.com>
+S:	Maintained
+F:	board/pdm360ng/
+F:	include/configs/pdm360ng.h
+F:	configs/pdm360ng_defconfig
diff --git a/board/pdm360ng/Makefile b/board/pdm360ng/Makefile
new file mode 100644
index 0000000000..99201a41f6
--- /dev/null
+++ b/board/pdm360ng/Makefile
@@ -0,0 +1,8 @@ 
+#
+# (C) Copyright 2007
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	:= pdm360ng.o
diff --git a/board/pdm360ng/pdm360ng.c b/board/pdm360ng/pdm360ng.c
new file mode 100644
index 0000000000..371bcd9e6b
--- /dev/null
+++ b/board/pdm360ng/pdm360ng.c
@@ -0,0 +1,581 @@ 
+/*
+ * (C) Copyright 2009, 2010 Wolfgang Denk <wd@denx.de>
+ *
+ * (C) Copyright 2009-2010
+ * Michael WeiƟ, ifm ecomatic gmbh, michael.weiss@ifm.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/bitops.h>
+#include <command.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+#include <asm/mpc512x.h>
+#include <fdt_support.h>
+#include <flash.h>
+#ifdef CONFIG_MISC_INIT_R
+#include <i2c.h>
+#endif
+#include <serial.h>
+#include <jffs2/load_kernel.h>
+#include <mtd_node.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern flash_info_t flash_info[];
+ulong flash_get_size (phys_addr_t base, int banknum);
+
+sdram_conf_t mddrc_config[] = {
+	{
+		(512 << 20),	/* 512 MB RAM configuration */
+		{
+			CONFIG_SYS_MDDRC_SYS_CFG,
+			CONFIG_SYS_MDDRC_TIME_CFG0,
+			CONFIG_SYS_MDDRC_TIME_CFG1,
+			CONFIG_SYS_MDDRC_TIME_CFG2
+		}
+	},
+	{
+		(128 << 20),	/* 128 MB RAM configuration */
+		{
+			CONFIG_SYS_MDDRC_SYS_CFG_ALT1,
+			CONFIG_SYS_MDDRC_TIME_CFG0_ALT1,
+			CONFIG_SYS_MDDRC_TIME_CFG1_ALT1,
+			CONFIG_SYS_MDDRC_TIME_CFG2_ALT1
+		}
+	},
+};
+
+int dram_init(void)
+{
+	int i;
+	u32 msize = 0;
+	u32 pdm360ng_init_seq[] = {
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_PCHG_ALL,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_RFSH,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_RFSH,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_MICRON_INIT_DEV_OP,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_EM2,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_PCHG_ALL,
+		CONFIG_SYS_DDRCMD_EM2,
+		CONFIG_SYS_DDRCMD_EM3,
+		CONFIG_SYS_DDRCMD_EN_DLL,
+		CONFIG_SYS_DDRCMD_RES_DLL,
+		CONFIG_SYS_DDRCMD_PCHG_ALL,
+		CONFIG_SYS_DDRCMD_RFSH,
+		CONFIG_SYS_DDRCMD_RFSH,
+		CONFIG_SYS_MICRON_INIT_DEV_OP,
+		CONFIG_SYS_DDRCMD_OCD_DEFAULT,
+		CONFIG_SYS_DDRCMD_OCD_EXIT,
+		CONFIG_SYS_DDRCMD_PCHG_ALL,
+		CONFIG_SYS_DDRCMD_NOP
+	};
+
+	for (i = 0; i < ARRAY_SIZE(mddrc_config); i++) {
+		msize = fixed_sdram(&mddrc_config[i].cfg, pdm360ng_init_seq,
+				    ARRAY_SIZE(pdm360ng_init_seq));
+		if (msize == mddrc_config[i].size)
+			break;
+	}
+
+	gd->ram_size = msize;
+
+	return 0;
+}
+
+static int set_lcd_brightness(char *);
+
+int misc_init_r(void)
+{
+	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+
+	/*
+	 * Re-configure flash setup using auto-detected info
+	 */
+	if (flash_info[1].size > 0) {
+		out_be32(&im->sysconf.lpcs1aw,
+			CSAW_START(gd->bd->bi_flashstart + flash_info[1].size) |
+			CSAW_STOP(gd->bd->bi_flashstart + flash_info[1].size,
+				  flash_info[1].size));
+		sync_law(&im->sysconf.lpcs1aw);
+		/*
+		 * Re-check to get correct base address
+		 */
+		flash_get_size (gd->bd->bi_flashstart + flash_info[1].size, 1);
+	} else {
+		/* Disable Bank 1 */
+		out_be32(&im->sysconf.lpcs1aw, 0x01000100);
+		sync_law(&im->sysconf.lpcs1aw);
+	}
+
+	out_be32(&im->sysconf.lpcs0aw,
+		CSAW_START(gd->bd->bi_flashstart) |
+		CSAW_STOP(gd->bd->bi_flashstart, flash_info[0].size));
+	sync_law(&im->sysconf.lpcs0aw);
+
+	/*
+	 * Re-check to get correct base address
+	 */
+	flash_get_size (gd->bd->bi_flashstart, 0);
+
+	/*
+	 * Re-do flash protection upon new addresses
+	 */
+	flash_protect (FLAG_PROTECT_CLEAR,
+		       gd->bd->bi_flashstart, 0xffffffff,
+		       &flash_info[0]);
+
+	/* Monitor protection ON by default */
+	flash_protect (FLAG_PROTECT_SET,
+		       CONFIG_SYS_MONITOR_BASE,
+		       CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1,
+		       &flash_info[0]);
+
+	/* Environment protection ON by default */
+	flash_protect (FLAG_PROTECT_SET,
+		       CONFIG_ENV_ADDR,
+		       CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
+		       &flash_info[0]);
+
+#ifdef CONFIG_ENV_ADDR_REDUND
+	/* Redundant environment protection ON by default */
+	flash_protect (FLAG_PROTECT_SET,
+		       CONFIG_ENV_ADDR_REDUND,
+		       CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
+		       &flash_info[0]);
+#endif
+
+#ifdef CONFIG_FSL_DIU_FB
+	set_lcd_brightness(0);
+	/* Switch LCD-Backlight and LVDS-Interface on */
+	setbits_be32(&im->gpio.gpdir, 0x01040000);
+	clrsetbits_be32(&im->gpio.gpdat, 0x01000000, 0x00040000);
+#endif
+
+	return 0;
+}
+
+static  iopin_t ioregs_init[] = {
+	/* FUNC1=LPC_CS4 */
+	{
+		offsetof(struct ioctrl512x, io_control_pata_ce1), 1, 0,
+		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(1) |
+		IO_PIN_PUE(1) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+	/* FUNC3=GPIO10 */
+	{
+		offsetof(struct ioctrl512x, io_control_pata_ce2), 1, 0,
+		IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
+	},
+	/* FUNC1=CAN3_TX */
+	{
+		offsetof(struct ioctrl512x, io_control_pata_isolate), 1, 0,
+		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
+	},
+	/* FUNC3=GPIO14 */
+	{
+		offsetof(struct ioctrl512x, io_control_pata_iochrdy), 1, 0,
+		IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
+	},
+	/* FUNC2=DIU_LD22 Sets Next 2 to DIU_LD pads */
+	/* DIU_LD22-DIU_LD23 */
+	{
+		offsetof(struct ioctrl512x, io_control_pci_ad31), 2, 0,
+		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
+	},
+	/* FUNC2=USB1_DATA7 Sets Next 12 to USB1 pads */
+	/* USB1_DATA7-USB1_DATA0, USB1_STOP, USB1_NEXT, USB1_CLK, USB1_DIR */
+	{
+		offsetof(struct ioctrl512x, io_control_pci_ad29), 12, 0,
+		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
+	},
+	/* FUNC1=VIU_DATA0 Sets Next 3 to VIU_DATA pads */
+	/* VIU_DATA0-VIU_DATA2 */
+	{
+		offsetof(struct ioctrl512x, io_control_pci_ad17), 3, 0,
+		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
+	},
+	/* FUNC2=FEC_TXD_0 */
+	{
+		offsetof(struct ioctrl512x, io_control_pci_ad14), 1, 0,
+		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
+	},
+	/* FUNC1=VIU_DATA3 Sets Next 2 to VIU_DATA pads */
+	/* VIU_DATA3, VIU_DATA4 */
+	{
+		offsetof(struct ioctrl512x, io_control_pci_ad13), 2, 0,
+		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
+	},
+	/* FUNC2=FEC_RXD_1 Sets Next 12 to FEC pads */
+	/* FEC_RXD_1, FEC_RXD_0, FEC_RX_CLK, FEC_TX_CLK, FEC_RX_ER, FEC_RX_DV */
+	/* FEC_TX_EN, FEC_TX_ER, FEC_CRS, FEC_MDC, FEC_MDIO, FEC_COL */
+	{
+		offsetof(struct ioctrl512x, io_control_pci_ad11), 12, 0,
+		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
+	},
+	/* FUNC2=DIU_LD03 Sets Next 25 to DIU pads */
+	/* DIU_LD00-DIU_LD21 */
+	{
+		offsetof(struct ioctrl512x, io_control_pci_cbe0), 22, 0,
+		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
+	},
+	/* FUNC2=DIU_CLK Sets Next 3 to DIU pads */
+	/* DIU_CLK, DIU_VSYNC, DIU_HSYNC */
+	{
+		offsetof(struct ioctrl512x, io_control_spdif_txclk), 3, 0,
+		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+	/* FUNC2=CAN3_RX */
+	{
+		offsetof(struct ioctrl512x, io_control_irq1), 1, 0,
+		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
+	},
+	/* Sets lowest slew on 2 CAN_TX Pins*/
+	{
+		offsetof(struct ioctrl512x, io_control_can1_tx), 2, 0,
+		IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
+	},
+	/* FUNC3=CAN4_TX Sets Next 2 to CAN4 pads */
+	/* CAN4_TX, CAN4_RX */
+	{
+		offsetof(struct ioctrl512x, io_control_j1850_tx), 2, 0,
+		IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
+	},
+	/* FUNC3=GPIO8 Sets Next 2 to GPIO pads */
+	/* GPIO8, GPIO9 */
+	{
+		offsetof(struct ioctrl512x, io_control_psc0_0), 2, 0,
+		IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
+	},
+	/* FUNC1=FEC_TXD_1 Sets Next 3 to FEC pads */
+	/* FEC_TXD_1, FEC_TXD_2, FEC_TXD_3 */
+	{
+		offsetof(struct ioctrl512x, io_control_psc0_4), 3, 0,
+		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+	/* FUNC1=FEC_RXD_3 Sets Next 2 to FEC pads */
+	/* FEC_RXD_3, FEC_RXD_2 */
+	{
+		offsetof(struct ioctrl512x, io_control_psc1_4), 2, 0,
+		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+	/* FUNC3=GPIO17 */
+	{
+		offsetof(struct ioctrl512x, io_control_psc2_1), 1, 0,
+		IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
+	},
+	/* FUNC3=GPIO2/GPT2 Sets Next 3 to GPIO pads */
+	/* GPIO2, GPIO20, GPIO21 */
+	{
+		offsetof(struct ioctrl512x, io_control_psc2_4), 3, 0,
+		IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
+	},
+	/* FUNC2=VIU_PIX_CLK */
+	{
+		offsetof(struct ioctrl512x, io_control_psc3_4), 1, 0,
+		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+	/* FUNC3=GPIO24 Sets Next 2 to GPIO pads */
+	/* GPIO24, GPIO25 */
+	{
+		offsetof(struct ioctrl512x, io_control_psc4_0), 2, 0,
+		IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
+	},
+	/* FUNC1=NFC_CE2 */
+	{
+		offsetof(struct ioctrl512x, io_control_psc4_4), 1, 0,
+		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(1) |
+		IO_PIN_PUE(1) | IO_PIN_ST(0) | IO_PIN_DS(0)
+	},
+	/* FUNC2=VIU_DATA5 Sets Next 5 to VIU_DATA pads */
+	/* VIU_DATA5-VIU_DATA9 */
+	{
+		offsetof(struct ioctrl512x, io_control_psc5_0), 5, 0,
+		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+	/* FUNC1=LPC_TSIZ1 Sets Next 2 to LPC_TSIZ pads */
+	/* LPC_TSIZ1-LPC_TSIZ2 */
+	{
+		offsetof(struct ioctrl512x, io_control_psc6_0), 2, 0,
+		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+	/* FUNC1=LPC_TS */
+	{
+		offsetof(struct ioctrl512x, io_control_psc6_4), 1, 0,
+		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+	/* FUNC3=GPIO16 */
+	{
+		offsetof(struct ioctrl512x, io_control_psc7_0), 1, 0,
+		IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
+	},
+	/* FUNC3=GPIO18 Sets Next 3 to GPIO pads */
+	/* GPIO18-GPIO19, GPT7/GPIO7 */
+	{
+		offsetof(struct ioctrl512x, io_control_psc7_2), 3, 0,
+		IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
+	},
+	/* FUNC3=GPIO0/GPT0 */
+	{
+		offsetof(struct ioctrl512x, io_control_psc8_4), 1, 0,
+		IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
+	},
+	/* FUNC3=GPIO11 Sets Next 4 to GPIO pads */
+	/* GPIO11, GPIO2, GPIO12, GPIO13 */
+	{
+		offsetof(struct ioctrl512x, io_control_psc10_3), 4, 0,
+		IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
+	},
+	/* FUNC2=DIU_DE */
+	{
+		offsetof(struct ioctrl512x, io_control_psc11_4), 1, 0,
+		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	}
+};
+
+int checkboard (void)
+{
+	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+
+	puts("Board: PDM360NG\n");
+
+	/* initialize function mux & slew rate IO inter alia on IO Pins  */
+
+	iopin_initialize(ioregs_init, ARRAY_SIZE(ioregs_init));
+
+	/* initialize IO_CONTROL_GP (GPIO/GPT-mux-register) */
+	setbits_be32(&im->io_ctrl.io_control_gp,
+		     (1 << 0) |   /* GP_MUX7->GPIO7 */
+		     (1 << 5));	  /* GP_MUX2->GPIO2 */
+
+	/* configure GPIO24 (VIU_CE), output/high */
+	setbits_be32(&im->gpio.gpdir, 0x80);
+	setbits_be32(&im->gpio.gpdat, 0x80);
+
+	return 0;
+}
+
+#ifdef CONFIG_OF_BOARD_SETUP
+#ifdef CONFIG_FDT_FIXUP_PARTITIONS
+struct node_info nodes[] = {
+	{ "fsl,mpc5121-nfc",	MTD_DEV_TYPE_NAND, },
+	{ "cfi-flash",		MTD_DEV_TYPE_NOR,  },
+};
+#endif
+
+#if defined(CONFIG_VIDEO)
+/*
+ * EDID block has been generated using Phoenix EDID Designer 1.3.
+ * This tool creates a text file containing:
+ *
+ * EDID BYTES:
+ * 0x   00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
+ *     ------------------------------------------------
+ * 00 | 00 FF FF FF FF FF FF 00 42 C9 34 12 01 00 00 00
+ * 10 | 0A 0C 01 03 80 98 5B 78 CA 7E 50 A0 58 4E 96 25
+ * 20 | 1E 50 54 00 00 00 01 01 01 01 01 01 01 01 01 01
+ * 30 | 01 01 01 01 01 01 80 0C 20 00 31 E0 2D 10 2A 80
+ * 40 | 12 08 30 E4 10 00 00 18 00 00 00 FD 00 38 3C 1F
+ * 50 | 3C 04 0A 20 20 20 20 20 20 20 00 00 00 FF 00 50
+ * 60 | 4D 30 37 30 57 4C 33 0A 0A 0A 0A 0A 00 00 00 FF
+ * 70 | 00 41 30 30 30 30 30 30 30 30 30 30 30 31 00 D4
+ *
+ * Then this data has been manually converted to the char
+ * array below.
+ */
+static unsigned char edid_buf[128] = {
+	0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00,
+	0x42, 0xC9, 0x34, 0x12, 0x01, 0x00, 0x00, 0x00,
+	0x0A, 0x0C, 0x01, 0x03, 0x80, 0x98, 0x5B, 0x78,
+	0xCA, 0x7E, 0x50, 0xA0, 0x58, 0x4E, 0x96, 0x25,
+	0x1E, 0x50, 0x54, 0x00, 0x00, 0x00, 0x01, 0x01,
+	0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
+	0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x80, 0x0C,
+	0x20, 0x00, 0x31, 0xE0, 0x2D, 0x10, 0x2A, 0x80,
+	0x12, 0x08, 0x30, 0xE4, 0x10, 0x00, 0x00, 0x18,
+	0x00, 0x00, 0x00, 0xFD, 0x00, 0x38, 0x3C, 0x1F,
+	0x3C, 0x04, 0x0A, 0x20, 0x20, 0x20, 0x20, 0x20,
+	0x20, 0x20, 0x00, 0x00, 0x00, 0xFF, 0x00, 0x50,
+	0x4D, 0x30, 0x37, 0x30, 0x57, 0x4C, 0x33, 0x0A,
+	0x0A, 0x0A, 0x0A, 0x0A, 0x00, 0x00, 0x00, 0xFF,
+	0x00, 0x41, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30,
+	0x30, 0x30, 0x30, 0x30, 0x30, 0x31, 0x00, 0xD4,
+};
+#endif
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+	u32 val[8];
+	int rc, i = 0;
+
+	ft_cpu_setup(blob, bd);
+#ifdef CONFIG_FDT_FIXUP_PARTITIONS
+	fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
+#endif
+#if defined(CONFIG_VIDEO)
+	fdt_add_edid(blob, "fsl,mpc5121-diu", edid_buf);
+#endif
+
+	/* Fixup NOR FLASH mapping */
+	val[i++] = 0;				/* chip select number */
+	val[i++] = 0;				/* always 0 */
+	val[i++] = gd->bd->bi_flashstart;
+	val[i++] = gd->bd->bi_flashsize;
+
+	/* Fixup MRAM mapping */
+	val[i++] = 2;				/* chip select number */
+	val[i++] = 0;				/* always 0 */
+	val[i++] = CONFIG_SYS_MRAM_BASE;
+	val[i++] = CONFIG_SYS_MRAM_SIZE;
+
+	rc = fdt_find_and_setprop(blob, "/localbus", "ranges",
+				  val, i * sizeof(u32), 1);
+	if (rc)
+		printf("Unable to update localbus ranges, err=%s\n",
+		       fdt_strerror(rc));
+
+	/* Fixup reg property in NOR Flash node */
+	i = 0;
+	val[i++] = 0;			/* always 0 */
+	val[i++] = 0;			/* start at offset 0 */
+	val[i++] = flash_info[0].size;	/* size of Bank 0 */
+
+	/* Second Bank available? */
+	if (flash_info[1].size > 0) {
+		val[i++] = 0;			/* always 0 */
+		val[i++] = flash_info[0].size;	/* offset of Bank 1 */
+		val[i++] = flash_info[1].size;	/* size of Bank 1 */
+	}
+
+	rc = fdt_find_and_setprop(blob, "/localbus/flash", "reg",
+				  val, i * sizeof(u32), 1);
+	if (rc)
+		printf("Unable to update flash reg property, err=%s\n",
+		       fdt_strerror(rc));
+
+	return 0;
+}
+#endif /* CONFIG_OF_BOARD_SETUP */
+
+/*
+ * If argument is NULL, set the LCD brightness to the
+ * value from "brightness" environment variable. Set
+ * the LCD brightness to the value specified by the
+ * argument otherwise. Default brightness is zero.
+ */
+#define MAX_BRIGHTNESS	99
+static int set_lcd_brightness(char *brightness)
+{
+	struct stdio_dev *cop_port;
+	char *env;
+	char cmd_buf[20];
+	int val = 0;
+	int cs = 0;
+	int len, i;
+
+	if (brightness) {
+		val = simple_strtol(brightness, NULL, 10);
+	} else {
+		env = getenv("brightness");
+		if (env)
+			val = simple_strtol(env, NULL, 10);
+	}
+
+	if (val < 0)
+		val = 0;
+
+	if (val > MAX_BRIGHTNESS)
+		val = MAX_BRIGHTNESS;
+
+	sprintf(cmd_buf, "$SB;%04d;", val);
+
+	len = strlen(cmd_buf);
+	for (i = 1; i <= len; i++)
+		cs += cmd_buf[i];
+
+	cs = (~cs + 1) & 0xff;
+	sprintf(cmd_buf + len, "%02X\n", cs);
+
+	/* IO Coprocessor communication */
+	cop_port = open_port(4, CONFIG_SYS_PDM360NG_COPROC_BAUDRATE);
+	if (!cop_port) {
+		printf("Error: Can't open IO Coprocessor port.\n");
+		return -1;
+	}
+
+	debug("%s: cmd: %s", __func__, cmd_buf);
+	write_port(cop_port, cmd_buf);
+	/*
+	 * Wait for transmission and maybe response data
+	 * before closing the port.
+	 */
+	udelay(CONFIG_SYS_PDM360NG_COPROC_READ_DELAY);
+	memset(cmd_buf, 0, sizeof(cmd_buf));
+	len = read_port(cop_port, cmd_buf, sizeof(cmd_buf));
+	if (len)
+		printf("Error: %s\n", cmd_buf);
+
+	close_port(4);
+
+	return 0;
+}
+
+static int cmd_lcd_brightness(cmd_tbl_t *cmdtp, int flag,
+			      int argc, char * const argv[])
+{
+	if (argc < 2)
+		return cmd_usage(cmdtp);
+
+	return set_lcd_brightness(argv[1]);
+}
+
+U_BOOT_CMD(lcdbr, 2, 1, cmd_lcd_brightness,
+	"set LCD brightness",
+	"<brightness> - set LCD backlight level to <brightness>.\n"
+);
diff --git a/board/phytec/pcm030/Kconfig b/board/phytec/pcm030/Kconfig
new file mode 100644
index 0000000000..3a3eab8576
--- /dev/null
+++ b/board/phytec/pcm030/Kconfig
@@ -0,0 +1,12 @@ 
+if TARGET_PCM030
+
+config SYS_BOARD
+	default "pcm030"
+
+config SYS_VENDOR
+	default "phytec"
+
+config SYS_CONFIG_NAME
+	default "pcm030"
+
+endif
diff --git a/board/phytec/pcm030/MAINTAINERS b/board/phytec/pcm030/MAINTAINERS
new file mode 100644
index 0000000000..4e2ab0d64e
--- /dev/null
+++ b/board/phytec/pcm030/MAINTAINERS
@@ -0,0 +1,7 @@ 
+PCM030 BOARD
+M:	Jon Smirl <jonsmirl@gmail.com>
+S:	Maintained
+F:	board/phytec/pcm030/
+F:	include/configs/pcm030.h
+F:	configs/pcm030_defconfig
+F:	configs/pcm030_LOWBOOT_defconfig
diff --git a/board/phytec/pcm030/Makefile b/board/phytec/pcm030/Makefile
new file mode 100644
index 0000000000..2bb49dc7aa
--- /dev/null
+++ b/board/phytec/pcm030/Makefile
@@ -0,0 +1,8 @@ 
+#
+# (C) Copyright 2003-2007
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	:= pcm030.o
diff --git a/board/phytec/pcm030/README b/board/phytec/pcm030/README
new file mode 100644
index 0000000000..05faab68c8
--- /dev/null
+++ b/board/phytec/pcm030/README
@@ -0,0 +1,42 @@ 
+To build RAMBOOT, replace this section the main Makefile
+
+pcm030_config \
+pcm030_RAMBOOT_config \
+pcm030_LOWBOOT_config:	unconfig
+	@ >include/config.h
+	@[ -z "$(findstring LOWBOOT_,$@)" ] || \
+		{ echo "CONFIG_SYS_TEXT_BASE = 0xFF000000"	>board/phytec/pcm030/config.tmp ; \
+		  echo "... with LOWBOOT configuration" ; \
+		}
+	@[ -z "$(findstring RAMBOOT_,$@)" ] || \
+	       { echo "CONFIG_SYS_TEXT_BASE = 0x00100000" >board/phycore_mpc5200b_tiny/\
+			config.tmp ; \
+		 echo "... with RAMBOOT configuration" ; \
+		 echo "... remember to make sure that MBAR is already \
+				switched to 0xF0000000 !!!" ; \
+	       }
+	@$(MKCONFIG) -a pcm030 ppc mpc5xxx pcm030 phytec
+	@ echo "remember to set pcm030_REV to 0 for rev 1245.0 rev or to 1 for rev 1245.1"
+
+Alternative SDRAM settings:
+
+#define SDRAM_MODE	0x018D0000
+#define SDRAM_EMODE	0x40090000
+#define SDRAM_CONTROL	0x715f0f00
+#define SDRAM_CONFIG1	0x73722930
+#define SDRAM_CONFIG2	0x47770000
+
+/* Settings for XLB = 99 MHz */
+#define SDRAM_MODE	0x008D0000
+#define SDRAM_EMODE	0x40090000
+#define SDRAM_CONTROL	0x714b0f00
+#define SDRAM_CONFIG1	0x63611730
+#define SDRAM_CONFIG2	0x47670000
+
+The board ships default with the environment in EEPROM
+Moving the environment to flash can be more reliable
+
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0xfe0000)
+#define CONFIG_ENV_SIZE		0x20000
+#define CONFIG_ENV_SECT_SIZE	0x20000
diff --git a/board/phytec/pcm030/mt46v32m16-75.h b/board/phytec/pcm030/mt46v32m16-75.h
new file mode 100644
index 0000000000..47fc7c04bd
--- /dev/null
+++ b/board/phytec/pcm030/mt46v32m16-75.h
@@ -0,0 +1,21 @@ 
+/*
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * Eric Schumann, Phytec Messtechnik
+ * adapted for mt46v32m16-75 DDR-RAM
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#define SDRAM_DDR	1		/* is DDR */
+
+/* Settings for XLB = 132 MHz */
+
+#define SDRAM_MODE	0x018D0000
+#define SDRAM_EMODE	0x40090000
+#define SDRAM_CONTROL	0x71500F00
+#define SDRAM_CONFIG1	0x73711930
+#define SDRAM_CONFIG2	0x47770000
+
+#define SDRAM_TAPDELAY	0x10000000 /* reserved Bit in MPC5200 B3-Step */
diff --git a/board/phytec/pcm030/pcm030.c b/board/phytec/pcm030/pcm030.c
new file mode 100644
index 0000000000..bdd980da91
--- /dev/null
+++ b/board/phytec/pcm030/pcm030.c
@@ -0,0 +1,209 @@ 
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * (C) Copyright 2006
+ * Eric Schumann, Phytec Messtechnik GmbH
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <pci.h>
+#include <asm/io.h>
+
+#include "mt46v32m16-75.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifndef CONFIG_SYS_RAMBOOT
+static void sdram_start(int hi_addr)
+{
+	volatile struct mpc5xxx_cdm *cdm =
+		(struct mpc5xxx_cdm *)MPC5XXX_CDM;
+	volatile struct mpc5xxx_sdram *sdram =
+		(struct mpc5xxx_sdram *)MPC5XXX_SDRAM;
+
+	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
+
+	/* unlock mode register */
+	out_be32 (&sdram->ctrl,
+		(SDRAM_CONTROL | 0x80000000 | hi_addr_bit));
+
+	/* precharge all banks */
+	out_be32 (&sdram->ctrl,
+		(SDRAM_CONTROL | 0x80000002 | hi_addr_bit));
+
+#ifdef SDRAM_DDR
+	/* set mode register: extended mode */
+	out_be32 (&sdram->mode, (SDRAM_EMODE));
+
+	/* set mode register: reset DLL */
+	out_be32 (&sdram->mode,
+		(SDRAM_MODE | 0x04000000));
+#endif
+
+	/* precharge all banks */
+	out_be32 (&sdram->ctrl,
+		(SDRAM_CONTROL | 0x80000002 | hi_addr_bit));
+
+	/* auto refresh */
+	out_be32 (&sdram->ctrl,
+		(SDRAM_CONTROL | 0x80000004 | hi_addr_bit));
+
+	/* set mode register */
+	out_be32 (&sdram->mode, (SDRAM_MODE));
+
+	/* normal operation */
+	out_be32 (&sdram->ctrl,
+		(SDRAM_CONTROL | hi_addr_bit));
+
+	/* set CDM clock enable register, set MPC5200B SDRAM bus */
+	/* to reduced driver strength */
+	out_be32 (&cdm->clock_enable, (0x00CFFFFF));
+}
+#endif
+
+/*
+ * ATTENTION: Although partially referenced dram_init does NOT make
+ *	real use of CONFIG_SYS_SDRAM_BASE. The code does not
+ *	work if CONFIG_SYS_SDRAM_BASE
+ *	is something else than 0x00000000.
+ */
+
+int dram_init(void)
+{
+	volatile struct mpc5xxx_mmap_ctl *mm =
+		(struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR;
+	volatile struct mpc5xxx_cdm *cdm =
+		(struct mpc5xxx_cdm *)MPC5XXX_CDM;
+	volatile struct mpc5xxx_sdram *sdram =
+		(struct mpc5xxx_sdram *)MPC5XXX_SDRAM;
+	ulong dramsize = 0;
+	ulong dramsize2 = 0;
+#ifndef CONFIG_SYS_RAMBOOT
+	ulong test1, test2;
+
+	/* setup SDRAM chip selects */
+							 /* 256MB at 0x0 */
+	out_be32 (&mm->sdram0, 0x0000001b);
+							 /* disabled */
+	out_be32 (&mm->sdram1, 0x10000000);
+
+	/* setup config registers */
+	out_be32 (&sdram->config1, SDRAM_CONFIG1);
+	out_be32 (&sdram->config2, SDRAM_CONFIG2);
+
+#if defined(SDRAM_DDR) && defined(SDRAM_TAPDELAY)
+	/* set tap delay */
+	out_be32 (&cdm->porcfg, SDRAM_TAPDELAY);
+#endif
+
+	/* find RAM size using SDRAM CS0 only */
+	sdram_start(0);
+	test1 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x10000000);
+	sdram_start(1);
+	test2 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x10000000);
+	if (test1 > test2) {
+		sdram_start(0);
+		dramsize = test1;
+	} else
+		dramsize = test2;
+
+	/* memory smaller than 1MB is impossible */
+	if (dramsize < (1 << 20))
+		dramsize = 0;
+
+	/* set SDRAM CS0 size according to the amount of RAM found */
+	if (dramsize > 0) {
+		out_be32 (&mm->sdram0,
+			(0x13 + __builtin_ffs(dramsize >> 20) - 1));
+	} else {
+							/* disabled */
+		out_be32 (&mm->sdram0, 0);
+	}
+
+#else /* CONFIG_SYS_RAMBOOT */
+
+	/* retrieve size of memory connected to SDRAM CS0 */
+	dramsize = in_be32(&mm->sdram0) & 0xFF;
+	if (dramsize >= 0x13)
+		dramsize = (1 << (dramsize - 0x13)) << 20;
+	else
+		dramsize = 0;
+
+	/* retrieve size of memory connected to SDRAM CS1 */
+	dramsize2 = in_be32(&mm->sdram1) & 0xFF;
+	if (dramsize2 >= 0x13)
+		dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
+	else
+		dramsize2 = 0;
+
+#endif /* CONFIG_SYS_RAMBOOT */
+
+	gd->ram_size = dramsize + dramsize2;
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	puts("Board: phyCORE-MPC5200B-tiny\n");
+	return 0;
+}
+
+#ifdef CONFIG_PCI
+static struct pci_controller hose;
+
+extern void pci_mpc5xxx_init(struct pci_controller *);
+
+void pci_init_board(void)
+{
+	pci_mpc5xxx_init(&hose);
+}
+#endif
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, bd_t *bd)
+{
+	ft_cpu_setup(blob, bd);
+
+	return 0;
+}
+#endif /* CONFIG_OF_BOARD_SETUP */
+
+#if defined(CONFIG_IDE) && defined(CONFIG_IDE_RESET)
+
+#define GPIO_PSC2_4	0x02000000UL
+
+void init_ide_reset(void)
+{
+	volatile struct mpc5xxx_wu_gpio *wu_gpio =
+		(struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
+	debug("init_ide_reset\n");
+
+	/* Configure PSC2_4 as GPIO output for ATA reset */
+	setbits_be32(&wu_gpio->enable, GPIO_PSC2_4);
+	setbits_be32(&wu_gpio->ddr, GPIO_PSC2_4);
+	/* Deassert reset */
+	setbits_be32(&wu_gpio->dvo, GPIO_PSC2_4);
+}
+
+void ide_set_reset(int idereset)
+{
+	volatile struct mpc5xxx_wu_gpio *wu_gpio =
+		(struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
+	debug("ide_reset(%d)\n", idereset);
+
+	if (idereset) {
+		clrbits_be32(&wu_gpio->dvo, GPIO_PSC2_4);
+		/* Make a delay. MPC5200 spec says 25 usec min */
+		udelay(500000);
+	} else
+		setbits_be32(&wu_gpio->dvo, GPIO_PSC2_4);
+}
+#endif /* defined(CONFIG_IDE) && defined(CONFIG_IDE_RESET) */
diff --git a/board/tqc/tqm5200/Kconfig b/board/tqc/tqm5200/Kconfig
new file mode 100644
index 0000000000..738dc80551
--- /dev/null
+++ b/board/tqc/tqm5200/Kconfig
@@ -0,0 +1,25 @@ 
+if TARGET_CHARON
+
+config SYS_BOARD
+	default "tqm5200"
+
+config SYS_VENDOR
+	default "tqc"
+
+config SYS_CONFIG_NAME
+	default "charon"
+
+endif
+
+if TARGET_TQM5200
+
+config SYS_BOARD
+	default "tqm5200"
+
+config SYS_VENDOR
+	default "tqc"
+
+config SYS_CONFIG_NAME
+	default "TQM5200"
+
+endif
diff --git a/board/tqc/tqm5200/MAINTAINERS b/board/tqc/tqm5200/MAINTAINERS
new file mode 100644
index 0000000000..12d143d73f
--- /dev/null
+++ b/board/tqc/tqm5200/MAINTAINERS
@@ -0,0 +1,23 @@ 
+TQM5200 BOARD
+#M:	-
+S:	Maintained
+F:	board/tqc/tqm5200/
+F:	include/configs/aev.h
+F:	configs/aev_defconfig
+F:	include/configs/TQM5200.h
+F:	configs/cam5200_defconfig
+F:	configs/cam5200_niosflash_defconfig
+F:	configs/fo300_defconfig
+F:	configs/MiniFAP_defconfig
+F:	configs/TQM5200_defconfig
+F:	configs/TQM5200_B_defconfig
+F:	configs/TQM5200_B_HIGHBOOT_defconfig
+F:	configs/TQM5200_STK100_defconfig
+F:	configs/TQM5200S_defconfig
+F:	configs/TQM5200S_HIGHBOOT_defconfig
+
+CHARON BOARD
+M:	Heiko Schocher <hs@denx.de>
+S:	Maintained
+F:	include/configs/charon.h
+F:	configs/charon_defconfig
diff --git a/board/tqc/tqm5200/Makefile b/board/tqc/tqm5200/Makefile
new file mode 100644
index 0000000000..f7c97b72c8
--- /dev/null
+++ b/board/tqc/tqm5200/Makefile
@@ -0,0 +1,8 @@ 
+#
+# (C) Copyright 2003-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	:= tqm5200.o cmd_stk52xx.o cam5200_flash.o
diff --git a/board/tqc/tqm5200/cam5200_flash.c b/board/tqc/tqm5200/cam5200_flash.c
new file mode 100644
index 0000000000..c3ae5c010b
--- /dev/null
+++ b/board/tqc/tqm5200/cam5200_flash.c
@@ -0,0 +1,768 @@ 
+/*
+ * (C) Copyright 2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <asm/processor.h>
+
+#if defined(CONFIG_CAM5200) && defined(CONFIG_CAM5200_NIOSFLASH)
+
+#if 0
+#define DEBUGF(x...) printf(x)
+#else
+#define DEBUGF(x...)
+#endif
+
+#define swap16(x) __swab16(x)
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips */
+
+/*
+ * CAM5200 is a TQM5200B based board. Additionally it also features
+ * a NIOS cpu. The NIOS CPU peripherals are accessible through MPC5xxx
+ * Local Bus on CS5. This includes 32 bit wide RAM and SRAM as well as
+ * 16 bit wide flash device. Big Endian order on a 32 bit CS5 makes
+ * access to flash chip slightly more complicated as additional byte
+ * swapping is necessary within each 16 bit wide flash 'word'.
+ *
+ * This driver's task is to handle both flash devices: 32 bit TQM5200B
+ * flash chip and 16 bit NIOS cpu flash chip. In the below
+ * flash_addr_table table we use least significant address bit to mark
+ * 16 bit flash bank and two sets of routines *_32 and *_16 to handle
+ * specifics of both flashes.
+ */
+static unsigned long flash_addr_table[][CONFIG_SYS_MAX_FLASH_BANKS] = {
+	{CONFIG_SYS_BOOTCS_START, CONFIG_SYS_CS5_START | 1}
+};
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static int write_word(flash_info_t * info, ulong dest, ulong data);
+#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV
+static int write_word_32(flash_info_t * info, ulong dest, ulong data);
+static int write_word_16(flash_info_t * info, ulong dest, ulong data);
+static int flash_erase_32(flash_info_t * info, int s_first, int s_last);
+static int flash_erase_16(flash_info_t * info, int s_first, int s_last);
+static ulong flash_get_size_32(vu_long * addr, flash_info_t * info);
+static ulong flash_get_size_16(vu_long * addr, flash_info_t * info);
+#endif
+
+void flash_print_info(flash_info_t * info)
+{
+	int i, k;
+	int size, erased;
+	volatile unsigned long *flash;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+		case FLASH_MAN_AMD:
+			printf("AMD ");
+			break;
+		case FLASH_MAN_FUJ:
+			printf("FUJITSU ");
+			break;
+		default:
+			printf("Unknown Vendor ");
+			break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+		case FLASH_S29GL128N:
+			printf ("S29GL128N (256 Mbit, uniform sector size)\n");
+			break;
+		case FLASH_AM320B:
+			printf ("29LV320B (32 Mbit, bottom boot sect)\n");
+			break;
+		case FLASH_AM320T:
+			printf ("29LV320T (32 Mbit, top boot sect)\n");
+			break;
+		default:
+			printf("Unknown Chip Type\n");
+			break;
+	}
+
+	printf("  Size: %ld KB in %d Sectors\n",
+			info->size >> 10, info->sector_count);
+
+	printf("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		/*
+		 * Check if whole sector is erased
+		 */
+		if (i != (info->sector_count - 1))
+			size = info->start[i + 1] - info->start[i];
+		else
+			size = info->start[0] + info->size - info->start[i];
+
+		erased = 1;
+		flash = (volatile unsigned long *)info->start[i];
+		size = size >> 2;	/* divide by 4 for longword access */
+
+		for (k = 0; k < size; k++) {
+			if (*flash++ != 0xffffffff) {
+				erased = 0;
+				break;
+			}
+		}
+
+		if ((i % 5) == 0)
+			printf("\n   ");
+
+		printf(" %08lX%s%s", info->start[i],
+				erased ? " E" : "  ",
+				info->protect[i] ? "RO " : "   ");
+	}
+	printf("\n");
+	return;
+}
+
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV
+static ulong flash_get_size(vu_long * addr, flash_info_t * info)
+{
+
+	DEBUGF("get_size: FLASH ADDR %08lx\n", addr);
+
+	/* bit 0 used for big flash marking */
+	if ((ulong)addr & 0x1)
+		return flash_get_size_16((vu_long *)((ulong)addr & 0xfffffffe), info);
+	else
+		return flash_get_size_32(addr, info);
+}
+
+static ulong flash_get_size_32(vu_long * addr, flash_info_t * info)
+#else
+static ulong flash_get_size(vu_long * addr, flash_info_t * info)
+#endif
+{
+	short i;
+	CONFIG_SYS_FLASH_WORD_SIZE value;
+	ulong base = (ulong) addr;
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) addr;
+
+	DEBUGF("get_size32: FLASH ADDR: %08x\n", (unsigned)addr);
+
+	/* Write auto select command: read Manufacturer ID */
+	addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+	addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+	addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00900090;
+	udelay(1000);
+
+	value = addr2[0];
+	DEBUGF("FLASH MANUFACT: %x\n", value);
+
+	switch (value) {
+		case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_MANUFACT:
+			info->flash_id = FLASH_MAN_AMD;
+			break;
+		default:
+			info->flash_id = FLASH_UNKNOWN;
+			info->sector_count = 0;
+			info->size = 0;
+			return (0);	/* no or unknown flash  */
+	}
+
+	value = addr2[1];	/* device ID            */
+	DEBUGF("\nFLASH DEVICEID: %x\n", value);
+
+	switch (value) {
+		case AMD_ID_MIRROR:
+			DEBUGF("Mirror Bit flash: addr[14] = %08lX  addr[15] = %08lX\n",
+					addr[14], addr[15]);
+			switch(addr[14]) {
+				case AMD_ID_GL128N_2:
+					if (addr[15] != AMD_ID_GL128N_3) {
+						DEBUGF("Chip: S29GL128N -> unknown\n");
+						info->flash_id = FLASH_UNKNOWN;
+					} else {
+						DEBUGF("Chip: S29GL128N\n");
+						info->flash_id += FLASH_S29GL128N;
+						info->sector_count = 128;
+						info->size = 0x02000000;
+					}
+					break;
+				default:
+					info->flash_id = FLASH_UNKNOWN;
+					return(0);
+			}
+			break;
+
+		default:
+			info->flash_id = FLASH_UNKNOWN;
+			return (0);	/* => no or unknown flash */
+	}
+
+	/* set up sector start address table */
+	for (i = 0; i < info->sector_count; i++)
+		info->start[i] = base + (i * 0x00040000);
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[i]);
+
+		info->protect[i] = addr2[2] & 1;
+	}
+
+	/* issue bank reset to return to read mode */
+	addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0;
+
+	return (info->size);
+}
+
+static int wait_for_DQ7_32(flash_info_t * info, int sect)
+{
+	ulong start, now, last;
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr =
+		(CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]);
+
+	start = get_timer(0);
+	last = start;
+	while ((addr[0] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) !=
+			(CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) {
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+			printf("Timeout\n");
+			return -1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			putc('.');
+			last = now;
+		}
+	}
+	return 0;
+}
+
+#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV
+int flash_erase(flash_info_t * info, int s_first, int s_last)
+{
+	if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) {
+		return flash_erase_16(info, s_first, s_last);
+	} else {
+		return flash_erase_32(info, s_first, s_last);
+	}
+}
+
+static int flash_erase_32(flash_info_t * info, int s_first, int s_last)
+#else
+int flash_erase(flash_info_t * info, int s_first, int s_last)
+#endif
+{
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]);
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2;
+	int flag, prot, sect;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN)
+			printf("- missing\n");
+		else
+			printf("- no sectors to erase\n");
+		return 1;
+	}
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf("Can't erase unknown flash type - aborted\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect])
+			prot++;
+	}
+
+	if (prot)
+		printf("- Warning: %d protected sectors will not be erased!", prot);
+
+	printf("\n");
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]);
+
+			addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+			addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+			addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080;
+			addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+			addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+			addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00300030;	/* sector erase */
+
+			/*
+			 * Wait for each sector to complete, it's more
+			 * reliable.  According to AMD Spec, you must
+			 * issue all erase commands within a specified
+			 * timeout.  This has been seen to fail, especially
+			 * if printf()s are included (for debug)!!
+			 */
+			wait_for_DQ7_32(info, sect);
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay(1000);
+
+	/* reset to read mode */
+	addr = (CONFIG_SYS_FLASH_WORD_SIZE *) info->start[0];
+	addr[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0;	/* reset bank */
+
+	printf(" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	ulong cp, wp, data;
+	int i, l, rc;
+
+	wp = (addr & ~3);	/* get lower word aligned address */
+
+	/*
+	 * handle unaligned start bytes
+	 */
+	if ((l = addr - wp) != 0) {
+		data = 0;
+		for (i = 0, cp = wp; i < l; ++i, ++cp)
+			data = (data << 8) | (*(uchar *) cp);
+
+		for (; i < 4 && cnt > 0; ++i) {
+			data = (data << 8) | *src++;
+			--cnt;
+			++cp;
+		}
+
+		for (; cnt == 0 && i < 4; ++i, ++cp)
+			data = (data << 8) | (*(uchar *) cp);
+
+		if ((rc = write_word(info, wp, data)) != 0)
+			return (rc);
+
+		wp += 4;
+	}
+
+	/*
+	 * handle word aligned part
+	 */
+	while (cnt >= 4) {
+		data = 0;
+		for (i = 0; i < 4; ++i)
+			data = (data << 8) | *src++;
+
+		if ((rc = write_word(info, wp, data)) != 0)
+			return (rc);
+
+		wp += 4;
+		cnt -= 4;
+	}
+
+	if (cnt == 0)
+		return (0);
+
+	/*
+	 * handle unaligned tail bytes
+	 */
+	data = 0;
+	for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
+		data = (data << 8) | *src++;
+		--cnt;
+	}
+	for (; i < 4; ++i, ++cp)
+		data = (data << 8) | (*(uchar *) cp);
+
+	return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV
+static int write_word(flash_info_t * info, ulong dest, ulong data)
+{
+	if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) {
+		return write_word_16(info, dest, data);
+	} else {
+		return write_word_32(info, dest, data);
+	}
+}
+
+static int write_word_32(flash_info_t * info, ulong dest, ulong data)
+#else
+static int write_word(flash_info_t * info, ulong dest, ulong data)
+#endif
+{
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]);
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *) dest;
+	ulong *datap = &data;
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 =
+			(volatile CONFIG_SYS_FLASH_WORD_SIZE *)datap;
+	ulong start;
+	int i, flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_long *)dest) & data) != data)
+		return (2);
+
+	for (i = 0; i < 4 / sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++) {
+		/* Disable interrupts which might cause a timeout here */
+		flag = disable_interrupts();
+
+		addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+		addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+		addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00A000A0;
+
+		dest2[i] = data2[i];
+
+		/* re-enable interrupts if necessary */
+		if (flag)
+			enable_interrupts();
+
+		/* data polling for D7 */
+		start = get_timer(0);
+		while ((dest2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) !=
+				(data2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080)) {
+
+			if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT)
+				return (1);
+		}
+	}
+
+	return (0);
+}
+
+#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV
+
+#undef  CONFIG_SYS_FLASH_WORD_SIZE
+#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+static ulong flash_get_size_16(vu_long * addr, flash_info_t * info)
+{
+	short i;
+	CONFIG_SYS_FLASH_WORD_SIZE value;
+	ulong base = (ulong) addr;
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) addr;
+
+	DEBUGF("get_size16: FLASH ADDR: %08x\n", (unsigned)addr);
+
+	/* issue bank reset to return to read mode */
+	addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xF000F000;
+
+	/* Write auto select command: read Manufacturer ID */
+	addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAA00AA00;
+	addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55005500;
+	addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x90009000;
+	udelay(1000);
+
+	value = swap16(addr2[0]);
+	DEBUGF("FLASH MANUFACT: %x\n", value);
+
+	switch (value) {
+		case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_MANUFACT:
+			info->flash_id = FLASH_MAN_AMD;
+			break;
+		case (CONFIG_SYS_FLASH_WORD_SIZE) FUJ_MANUFACT:
+			info->flash_id = FLASH_MAN_FUJ;
+			break;
+		default:
+			info->flash_id = FLASH_UNKNOWN;
+			info->sector_count = 0;
+			info->size = 0;
+			return (0);	/* no or unknown flash  */
+	}
+
+	value = swap16(addr2[1]);	/* device ID            */
+	DEBUGF("\nFLASH DEVICEID: %x\n", value);
+
+	switch (value) {
+		case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320B:
+			info->flash_id += FLASH_AM320B;
+			info->sector_count = 71;
+			info->size = 0x00400000;
+			break;	/* => 4 MB	*/
+		case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320T:
+			info->flash_id += FLASH_AM320T;
+			info->sector_count = 71;
+			info->size = 0x00400000;
+			break;	/* => 4 MB	*/
+		default:
+			info->flash_id = FLASH_UNKNOWN;
+			return (0);	/* => no or unknown flash */
+	}
+
+	if (info->flash_id & FLASH_BTYPE) {
+		/* set sector offsets for bottom boot block type        */
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00002000;
+		info->start[2] = base + 0x00004000;
+		info->start[3] = base + 0x00006000;
+		info->start[4] = base + 0x00008000;
+		info->start[5] = base + 0x0000a000;
+		info->start[6] = base + 0x0000c000;
+		info->start[7] = base + 0x0000e000;
+
+		for (i = 8; i < info->sector_count; i++)
+			info->start[i] = base + (i * 0x00010000) - 0x00070000;
+	} else {
+		/* set sector offsets for top boot block type           */
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00002000;
+		info->start[i--] = base + info->size - 0x00004000;
+		info->start[i--] = base + info->size - 0x00006000;
+		info->start[i--] = base + info->size - 0x00008000;
+		info->start[i--] = base + info->size - 0x0000a000;
+		info->start[i--] = base + info->size - 0x0000c000;
+		info->start[i--] = base + info->size - 0x0000e000;
+
+		for (; i >= 0; i--)
+			info->start[i] = base + i * 0x00010000;
+	}
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
+		/* D0 = 1 if protected */
+		addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[i]);
+
+		info->protect[i] = addr2[2] & 1;
+	}
+
+	/* issue bank reset to return to read mode */
+	addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xF000F000;
+
+	return (info->size);
+}
+
+static int wait_for_DQ7_16(flash_info_t * info, int sect)
+{
+	ulong start, now, last;
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr =
+		(CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]);
+
+	start = get_timer(0);
+	last = start;
+	while ((addr[0] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x80008000) !=
+			(CONFIG_SYS_FLASH_WORD_SIZE) 0x80008000) {
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
+			printf("Timeout\n");
+			return -1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			putc('.');
+			last = now;
+		}
+	}
+	return 0;
+}
+
+static int flash_erase_16(flash_info_t * info, int s_first, int s_last)
+{
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]);
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2;
+	int flag, prot, sect;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN)
+			printf("- missing\n");
+		else
+			printf("- no sectors to erase\n");
+		return 1;
+	}
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf("Can't erase unknown flash type - aborted\n");
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect])
+			prot++;
+	}
+
+	if (prot)
+		printf("- Warning: %d protected sectors will not be erased!",	prot);
+
+	printf("\n");
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]);
+
+			addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAA00AA00;
+			addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55005500;
+			addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x80008000;
+			addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAA00AA00;
+			addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55005500;
+			addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x30003000;	/* sector erase */
+
+			/*
+			 * Wait for each sector to complete, it's more
+			 * reliable.  According to AMD Spec, you must
+			 * issue all erase commands within a specified
+			 * timeout.  This has been seen to fail, especially
+			 * if printf()s are included (for debug)!!
+			 */
+			wait_for_DQ7_16(info, sect);
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay(1000);
+
+	/* reset to read mode */
+	addr = (CONFIG_SYS_FLASH_WORD_SIZE *) info->start[0];
+	addr[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xF000F000;	/* reset bank */
+
+	printf(" done\n");
+	return 0;
+}
+
+static int write_word_16(flash_info_t * info, ulong dest, ulong data)
+{
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]);
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *) dest;
+	ulong *datap = &data;
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 =
+			(volatile CONFIG_SYS_FLASH_WORD_SIZE *)datap;
+	ulong start;
+	int i;
+
+	/* Check if Flash is (sufficiently) erased */
+	for (i = 0; i < 4 / sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++) {
+		if ((dest2[i] & swap16(data2[i])) != swap16(data2[i]))
+			return (2);
+	}
+
+	for (i = 0; i < 4 / sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++) {
+		int flag;
+
+		/* Disable interrupts which might cause a timeout here */
+		flag = disable_interrupts();
+
+		addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAA00AA00;
+		addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55005500;
+		addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xA000A000;
+
+		dest2[i] = swap16(data2[i]);
+
+		/* re-enable interrupts if necessary */
+		if (flag)
+			enable_interrupts();
+
+		/* data polling for D7 */
+		start = get_timer(0);
+		while ((dest2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x80008000) !=
+				(swap16(data2[i]) & (CONFIG_SYS_FLASH_WORD_SIZE) 0x80008000)) {
+
+			if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
+				return (1);
+			}
+		}
+	}
+
+	return (0);
+}
+#endif /* CONFIG_SYS_FLASH_2ND_16BIT_DEV */
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size(vu_long * addr, flash_info_t * info);
+static int write_word(flash_info_t * info, ulong dest, ulong data);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init(void)
+{
+	unsigned long total_b = 0;
+	unsigned long size_b[CONFIG_SYS_MAX_FLASH_BANKS];
+	unsigned short index = 0;
+	int i;
+
+	DEBUGF("\n");
+	DEBUGF("FLASH: Index: %d\n", index);
+
+	/* Init: no FLASHes known */
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+		flash_info[i].sector_count = -1;
+		flash_info[i].size = 0;
+
+		/* check whether the address is 0 */
+		if (flash_addr_table[index][i] == 0)
+			continue;
+
+		/* call flash_get_size() to initialize sector address */
+		size_b[i] = flash_get_size((vu_long *) flash_addr_table[index][i],
+				&flash_info[i]);
+
+		flash_info[i].size = size_b[i];
+
+		if (flash_info[i].flash_id == FLASH_UNKNOWN) {
+			printf("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
+					i+1, size_b[i], size_b[i] << 20);
+			flash_info[i].sector_count = -1;
+			flash_info[i].size = 0;
+		}
+
+		/* Monitor protection ON by default */
+		(void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE,
+				    CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1,
+				    &flash_info[i]);
+#if defined(CONFIG_ENV_IS_IN_FLASH)
+		(void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR,
+				    CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
+				    &flash_info[i]);
+#if defined(CONFIG_ENV_ADDR_REDUND)
+		(void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND,
+				    CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
+				    &flash_info[i]);
+#endif
+#endif
+		total_b += flash_info[i].size;
+	}
+
+	return total_b;
+}
+#endif /* if defined(CONFIG_CAM5200) && defined(CONFIG_CAM5200_NIOSFLASH) */
diff --git a/board/tqc/tqm5200/cmd_stk52xx.c b/board/tqc/tqm5200/cmd_stk52xx.c
new file mode 100644
index 0000000000..a3916ed957
--- /dev/null
+++ b/board/tqc/tqm5200/cmd_stk52xx.c
@@ -0,0 +1,1228 @@ 
+/*
+ * (C) Copyright 2005
+ * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * STK52XX specific functions
+ */
+/*#define DEBUG*/
+
+#include <common.h>
+#include <command.h>
+#include <console.h>
+
+#if defined(CONFIG_CMD_BSP)
+
+#if defined(CONFIG_STK52XX) || defined(CONFIG_FO300)
+#define DEFAULT_VOL	45
+#define DEFAULT_FREQ	500
+#define DEFAULT_DURATION	200
+#define LEFT		1
+#define RIGHT		2
+#define LEFT_RIGHT	3
+#define BL_OFF		0
+#define BL_ON		1
+
+#define SM501_GPIO_CTRL_LOW		0x00000008UL
+#define SM501_GPIO_CTRL_HIGH		0x0000000CUL
+#define SM501_POWER_MODE0_GATE		0x00000040UL
+#define SM501_POWER_MODE1_GATE		0x00000048UL
+#define POWER_MODE_GATE_GPIO_PWM_I2C	0x00000040UL
+#define SM501_GPIO_DATA_LOW		0x00010000UL
+#define SM501_GPIO_DATA_HIGH		0x00010004UL
+#define SM501_GPIO_DATA_DIR_LOW		0x00010008UL
+#define SM501_GPIO_DATA_DIR_HIGH	0x0001000CUL
+#define SM501_PANEL_DISPLAY_CONTROL	0x00080000UL
+
+static int i2s_squarewave(unsigned long duration, unsigned int freq,
+			  unsigned int channel);
+static int i2s_sawtooth(unsigned long duration, unsigned int freq,
+			unsigned int channel);
+static void spi_init(void);
+static int spi_transmit(unsigned char data);
+static void pcm1772_write_reg(unsigned char addr, unsigned char data);
+static void set_attenuation(unsigned char attenuation);
+
+static void spi_init(void)
+{
+	struct mpc5xxx_spi *spi = (struct mpc5xxx_spi*)MPC5XXX_SPI;
+	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO;
+
+	/* PSC3 as SPI and GPIOs */
+	gpio->port_config &= 0xFFFFF0FF;
+	gpio->port_config |= 0x00000800;
+	/*
+	 * Its important to use the correct order when initializing the
+	 * registers
+	 */
+	spi->ddr = 0x0F; /* set all SPI pins as output */
+	spi->pdr = 0x08; /* set SS high */
+	spi->cr1 = 0x50; /* SPI is master, SS is general purpose output */
+	spi->cr2 = 0x00; /* normal operation */
+	spi->brr = 0xFF; /* baud rate: IPB clock / 2048 */
+}
+
+static int spi_transmit(unsigned char data)
+{
+	struct mpc5xxx_spi *spi = (struct mpc5xxx_spi*)MPC5XXX_SPI;
+
+	spi->dr = data;
+	/* wait for SPI transmission completed */
+	while (!(spi->sr & 0x80)) {
+		if (spi->sr & 0x40) {	/* if write collision occurred */
+			int dummy;
+
+			/* do dummy read to clear status register */
+			dummy = spi->dr;
+			printf("SPI write collision: dr=0x%x\n", dummy);
+			return -1;
+		}
+	}
+	return (spi->dr);
+}
+
+static void pcm1772_write_reg(unsigned char addr, unsigned char data)
+{
+	struct mpc5xxx_spi *spi = (struct mpc5xxx_spi*)MPC5XXX_SPI;
+
+	spi->pdr = 0x00; /* Set SS low */
+	spi_transmit(addr);
+	spi_transmit(data);
+	/* wait some time to meet MS# hold time of PCM1772 */
+	udelay (1);
+	spi->pdr = 0x08; /* set SS high */
+}
+
+static void set_attenuation(unsigned char attenuation)
+{
+	pcm1772_write_reg(0x01, attenuation); /* left channel */
+	debug ("PCM1772 attenuation left set to %d.\n", attenuation);
+	pcm1772_write_reg(0x02, attenuation); /* right channel */
+	debug ("PCM1772 attenuation right set to %d.\n", attenuation);
+}
+
+void amplifier_init(void)
+{
+	static int init_done = 0;
+	int i;
+	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO;
+
+	/* Do this only once, because of the long time delay */
+	if (!init_done) {
+		/* configure PCM1772 audio format as I2S */
+		pcm1772_write_reg(0x03, 0x01);
+		/* enable audio amplifier */
+		gpio->sint_gpioe |=  0x02;	/* PSC3_5 as GPIO */
+		gpio->sint_ode &= ~0x02;	/* PSC3_5 is not open Drain */
+		gpio->sint_dvo &= ~0x02;	/* PSC3_5 is LOW */
+		gpio->sint_ddr |=  0x02;	/* PSC3_5 as output */
+		/*
+		 * wait some time to allow amplifier to recover from shutdown
+		 * mode.
+		 */
+		for(i = 0; i < 350; i++)
+			udelay(1000);
+		/*
+		 * The used amplifier (LM4867) has a so called "pop and click"
+		 * elmination filter. The input signal of the amplifier must
+		 * exceed a certain level once after power up to activate the
+		 * generation of the output signal. This is achieved by
+		 * sending a low frequent (nearly inaudible) sawtooth with a
+		 * sufficient signal level.
+		 */
+		set_attenuation(50);
+		i2s_sawtooth (200, 5, LEFT_RIGHT);
+		init_done = 1;
+	}
+}
+
+static void i2s_init(void)
+{
+	unsigned long i;
+	struct mpc5xxx_psc *psc = (struct mpc5xxx_psc*)MPC5XXX_PSC2;
+	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO;
+
+	gpio->port_config |= 0x00000070; /* PSC2 ports as Codec with MCLK */
+	psc->command = (PSC_RX_DISABLE | PSC_TX_DISABLE);
+	psc->sicr = 0x22E00000;		/* 16 bit data; I2S */
+
+	*(vu_long *)(CONFIG_SYS_MBAR + 0x22C) = 0x805d; /* PSC2 CDM MCLK config; MCLK
+						  * 5.617 MHz */
+	*(vu_long *)(CONFIG_SYS_MBAR + 0x214) |= 0x00000040; /* CDM clock enable
+						       * register */
+	psc->ccr = 0x1F03;	/* 16 bit data width; 5.617MHz MCLK */
+	psc->ctur = 0x0F;	/* 16 bit frame width */
+
+	for (i = 0; i < 128; i++)
+		psc->psc_buffer_32 = 0; /* clear tx fifo */
+}
+
+static int i2s_play_wave(unsigned long addr, unsigned long len)
+{
+	unsigned long i;
+	unsigned char *wave_file = (uchar *)addr + 44;	/* quick'n dirty: skip
+							 * wav header*/
+	struct mpc5xxx_psc *psc = (struct mpc5xxx_psc*)MPC5XXX_PSC2;
+
+	/*
+	 * play wave file in memory; bytes/words are be swapped
+	 */
+	psc->command = (PSC_RX_ENABLE | PSC_TX_ENABLE);
+
+	for(i = 0;i < (len / 4); i++) {
+		unsigned char swapped[4];
+		unsigned long *p = (unsigned long*)swapped;
+
+		swapped[3] = *wave_file++;
+		swapped[2] = *wave_file++;
+		swapped[1] = *wave_file++;
+		swapped[0] = *wave_file++;
+
+		psc->psc_buffer_32 =  *p;
+
+		while (psc->tfnum > 400) {
+			if(ctrlc())
+				return 0;
+		}
+	}
+	while (psc->tfnum > 0);		/* wait for fifo empty */
+	udelay (100);
+	psc->command = (PSC_RX_DISABLE | PSC_TX_DISABLE);
+	return 0;
+}
+
+static int i2s_sawtooth(unsigned long duration, unsigned int freq,
+			unsigned int channel)
+{
+	long i,j;
+	unsigned long data;
+	struct mpc5xxx_psc *psc = (struct mpc5xxx_psc*)MPC5XXX_PSC2;
+
+	psc->command = (PSC_RX_ENABLE | PSC_TX_ENABLE);
+
+	/*
+	 * Generate sawtooth. Start with middle level up to highest level. Then
+	 * go to lowest level and back to middle level.
+	 */
+	for(j = 0; j < ((duration * freq) / 1000); j++)	{
+		for(i = 0; i <= 0x7FFF; i += (0x7FFF/(44100/(freq*4))))	{
+			data = (i & 0xFFFF);
+			/* data format: right data left data) */
+			if (channel == LEFT_RIGHT)
+				data |= (data<<16);
+			if (channel == RIGHT)
+				data = (data<<16);
+			psc->psc_buffer_32 = data;
+			while (psc->tfnum > 400);
+		}
+		for(i = 0x7FFF; i >= -0x7FFF; i -= (0xFFFF/(44100/(freq*2)))) {
+			data = (i & 0xFFFF);
+			/* data format: right data left data) */
+			if (channel == LEFT_RIGHT)
+				data |= (data<<16);
+			if (channel == RIGHT)
+				data = (data<<16);
+			psc->psc_buffer_32 = data;
+			while (psc->tfnum > 400);
+		}
+		for(i = -0x7FFF; i <= 0; i += (0x7FFF/(44100/(freq*4)))) {
+			data = (i & 0xFFFF);
+			/* data format: right data left data) */
+			if (channel == LEFT_RIGHT)
+				data |= (data<<16);
+			if (channel == RIGHT)
+				data = (data<<16);
+			psc->psc_buffer_32 = data;
+			while (psc->tfnum > 400);
+		}
+	}
+	while (psc->tfnum > 0);		/* wait for fifo empty */
+	udelay (100);
+	psc->command = (PSC_RX_DISABLE | PSC_TX_DISABLE);
+
+	return 0;
+}
+
+static int i2s_squarewave(unsigned long duration, unsigned int freq,
+			 unsigned int channel)
+{
+	long i,j;
+	unsigned long data;
+	struct mpc5xxx_psc *psc = (struct mpc5xxx_psc*)MPC5XXX_PSC2;
+
+	psc->command = (PSC_RX_ENABLE | PSC_TX_ENABLE);
+
+	/*
+	 * Generate sqarewave. Start with high level, duty cycle 1:1.
+	 */
+	for(j = 0; j < ((duration * freq) / 1000); j++)	{
+		for(i = 0; i < (44100/(freq*2)); i ++) {
+			data = 0x7FFF;
+			/* data format: right data left data) */
+			if (channel == LEFT_RIGHT)
+				data |= (data<<16);
+			if (channel == RIGHT)
+				data = (data<<16);
+			psc->psc_buffer_32 = data;
+			while (psc->tfnum > 400);
+		}
+		for(i = 0; i < (44100/(freq*2)); i ++) {
+			data = 0x8000;
+			/* data format: right data left data) */
+			if (channel == LEFT_RIGHT)
+				data |= (data<<16);
+			if (channel == RIGHT)
+				data = (data<<16);
+			psc->psc_buffer_32 = data;
+			while (psc->tfnum > 400);
+		}
+	}
+	while (psc->tfnum > 0);		/* wait for fifo empty */
+	udelay (100);
+	psc->command = (PSC_RX_DISABLE | PSC_TX_DISABLE);
+
+	return 0;
+}
+
+static int cmd_sound(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	unsigned long reg, val, duration;
+	char *tmp;
+	unsigned int freq, channel;
+	unsigned char volume;
+	int rcode = 1;
+
+#ifdef CONFIG_STK52XX_REV100
+	printf ("Revision 100 of STK52XX not supported!\n");
+	return 1;
+#endif
+	spi_init();
+	i2s_init();
+	amplifier_init();
+
+	if ((tmp = getenv ("volume")) != NULL) {
+		volume = simple_strtoul (tmp, NULL, 10);
+	} else {
+		volume = DEFAULT_VOL;
+	}
+	set_attenuation(volume);
+
+	switch (argc) {
+	case 0:
+	case 1:
+		return cmd_usage(cmdtp);
+	case 2:
+		if (strncmp(argv[1],"saw",3) == 0) {
+			printf ("Play sawtooth\n");
+			rcode = i2s_sawtooth (DEFAULT_DURATION, DEFAULT_FREQ,
+					      LEFT_RIGHT);
+			return rcode;
+		} else if (strncmp(argv[1],"squ",3) == 0) {
+			printf ("Play squarewave\n");
+			rcode = i2s_squarewave (DEFAULT_DURATION, DEFAULT_FREQ,
+						LEFT_RIGHT);
+			return rcode;
+		}
+
+		return cmd_usage(cmdtp);
+	case 3:
+		if (strncmp(argv[1],"saw",3) == 0) {
+			duration = simple_strtoul(argv[2], NULL, 10);
+			printf ("Play sawtooth\n");
+			rcode = i2s_sawtooth (duration, DEFAULT_FREQ,
+					      LEFT_RIGHT);
+			return rcode;
+		} else if (strncmp(argv[1],"squ",3) == 0) {
+			duration = simple_strtoul(argv[2], NULL, 10);
+			printf ("Play squarewave\n");
+			rcode = i2s_squarewave (duration, DEFAULT_FREQ,
+						LEFT_RIGHT);
+			return rcode;
+		}
+		return cmd_usage(cmdtp);
+	case 4:
+		if (strncmp(argv[1],"saw",3) == 0) {
+			duration = simple_strtoul(argv[2], NULL, 10);
+			freq = (unsigned int)simple_strtoul(argv[3], NULL, 10);
+			printf ("Play sawtooth\n");
+			rcode = i2s_sawtooth (duration, freq,
+					      LEFT_RIGHT);
+			return rcode;
+		} else if (strncmp(argv[1],"squ",3) == 0) {
+			duration = simple_strtoul(argv[2], NULL, 10);
+			freq = (unsigned int)simple_strtoul(argv[3], NULL, 10);
+			printf ("Play squarewave\n");
+			rcode = i2s_squarewave (duration, freq,
+						LEFT_RIGHT);
+			return rcode;
+		} else if (strcmp(argv[1],"pcm1772") == 0) {
+			reg = simple_strtoul(argv[2], NULL, 10);
+			val = simple_strtoul(argv[3], NULL, 10);
+			printf("Set PCM1772 %lu. %lu\n", reg, val);
+			pcm1772_write_reg((uchar)reg, (uchar)val);
+			return 0;
+		}
+		return cmd_usage(cmdtp);
+	case 5:
+		if (strncmp(argv[1],"saw",3) == 0) {
+			duration = simple_strtoul(argv[2], NULL, 10);
+			freq = (unsigned int)simple_strtoul(argv[3], NULL, 10);
+			if (strncmp(argv[4],"l",1) == 0)
+				channel = LEFT;
+			else if (strncmp(argv[4],"r",1) == 0)
+				channel = RIGHT;
+			else
+				channel = LEFT_RIGHT;
+			printf ("Play squarewave\n");
+			rcode = i2s_sawtooth (duration, freq,
+					      channel);
+			return rcode;
+		} else if (strncmp(argv[1],"squ",3) == 0) {
+			duration = simple_strtoul(argv[2], NULL, 10);
+			freq = (unsigned int)simple_strtoul(argv[3], NULL, 10);
+			if (strncmp(argv[4],"l",1) == 0)
+				channel = LEFT;
+			else if (strncmp(argv[4],"r",1) == 0)
+				channel = RIGHT;
+			else
+				channel = LEFT_RIGHT;
+			printf ("Play squarewave\n");
+			rcode = i2s_squarewave (duration, freq,
+						channel);
+			return rcode;
+		}
+		return cmd_usage(cmdtp);
+	}
+	printf ("Usage:\nsound cmd [arg1] [arg2] ...\n");
+	return 1;
+}
+
+static int cmd_wav(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	unsigned long length, addr;
+	unsigned char volume;
+	int rcode = 1;
+	char *tmp;
+
+#ifdef CONFIG_STK52XX_REV100
+	printf ("Revision 100 of STK52XX not supported!\n");
+	return 1;
+#endif
+	spi_init();
+	i2s_init();
+	amplifier_init();
+
+	switch (argc) {
+
+	case 3:
+		length = simple_strtoul(argv[2], NULL, 16);
+		addr = simple_strtoul(argv[1], NULL, 16);
+		break;
+
+	case 2:
+		if ((tmp = getenv ("filesize")) != NULL) {
+			length = simple_strtoul (tmp, NULL, 16);
+		} else {
+			puts ("No filesize provided\n");
+			return 1;
+		}
+		addr = simple_strtoul(argv[1], NULL, 16);
+
+	case 1:
+		if ((tmp = getenv ("filesize")) != NULL) {
+			length = simple_strtoul (tmp, NULL, 16);
+		} else {
+			puts ("No filesize provided\n");
+			return 1;
+		}
+		if ((tmp = getenv ("loadaddr")) != NULL) {
+			addr = simple_strtoul (tmp, NULL, 16);
+		} else {
+			puts ("No loadaddr provided\n");
+			return 1;
+		}
+		break;
+
+	default:
+		printf("Usage:\nwav <addr> <length[s]\n");
+		return 1;
+		break;
+	}
+
+	if ((tmp = getenv ("volume")) != NULL) {
+		volume = simple_strtoul (tmp, NULL, 10);
+	} else {
+		volume = DEFAULT_VOL;
+	}
+	set_attenuation(volume);
+
+	printf("Play wave file at %lX with length %lX\n", addr, length);
+	rcode = i2s_play_wave(addr, length);
+
+	return rcode;
+}
+
+static int cmd_beep(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	unsigned char volume;
+	unsigned int channel;
+	int rcode;
+	char *tmp;
+
+#ifdef CONFIG_STK52XX_REV100
+	printf ("Revision 100 of STK52XX not supported!\n");
+	return 1;
+#endif
+	spi_init();
+	i2s_init();
+	amplifier_init();
+
+	switch (argc) {
+	case 0:
+	case 1:
+		channel = LEFT_RIGHT;
+		break;
+	case 2:
+		if (strncmp(argv[1],"l",1) == 0)
+			channel = LEFT;
+		else if (strncmp(argv[1],"r",1) == 0)
+			channel = RIGHT;
+		else
+			channel = LEFT_RIGHT;
+		break;
+	default:
+		return cmd_usage(cmdtp);
+	}
+
+	if ((tmp = getenv ("volume")) != NULL) {
+		volume = simple_strtoul (tmp, NULL, 10);
+	} else {
+		volume = DEFAULT_VOL;
+	}
+	set_attenuation(volume);
+
+	printf("Beep on ");
+	if (channel == LEFT)
+		printf ("left ");
+	else if (channel == RIGHT)
+		printf ("right ");
+	else
+		printf ("left and right ");
+	printf ("channel\n");
+
+	rcode = i2s_squarewave (DEFAULT_DURATION, DEFAULT_FREQ, channel);
+
+	return rcode;
+}
+#endif
+
+#if defined(CONFIG_STK52XX)
+void led_init(void)
+{
+	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
+	struct mpc5xxx_gpt_0_7 *gpt = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT;
+
+	/* configure PSC3 for SPI and GPIO */
+	gpio->port_config &= ~(0x00000F00);
+	gpio->port_config |=   0x00000800;
+
+	gpio->simple_gpioe &= ~(0x00000F00);
+	gpio->simple_gpioe |=   0x00000F00;
+
+	gpio->simple_ddr &= ~(0x00000F00);
+	gpio->simple_ddr |=   0x00000F00;
+
+	/* configure timer 4-7 for simple GPIO output */
+	gpt->gpt4.emsr |=  0x00000024;
+	gpt->gpt5.emsr |=  0x00000024;
+	gpt->gpt6.emsr |=  0x00000024;
+	gpt->gpt7.emsr |=  0x00000024;
+
+#ifndef CONFIG_TQM5200S
+	/* enable SM501 GPIO control (in both power modes) */
+	*(vu_long *) (SM501_MMIO_BASE+SM501_POWER_MODE0_GATE) |=
+		POWER_MODE_GATE_GPIO_PWM_I2C;
+	*(vu_long *) (SM501_MMIO_BASE+SM501_POWER_MODE1_GATE) |=
+		POWER_MODE_GATE_GPIO_PWM_I2C;
+
+	/* configure SM501 gpio pins 24-27 as output */
+	*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_CTRL_LOW) &= ~(0xF << 24);
+	*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_DIR_LOW) |= (0xF << 24);
+
+	/* configure SM501 gpio pins 48-51 as output */
+	*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_DIR_HIGH) |= (0xF << 16);
+#endif /* !CONFIG_TQM5200S */
+}
+
+/*
+ * return 1 if led number unknown
+ * return 0 else
+ */
+int do_led(char * const argv[])
+{
+	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
+	struct mpc5xxx_gpt_0_7 *gpt = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT;
+
+	switch	(simple_strtoul(argv[2], NULL, 10)) {
+
+	case 0:
+		if (strcmp (argv[3], "on") == 0) {
+			gpio->simple_dvo |=   (1 << 8);
+		} else {
+			gpio->simple_dvo &= ~(1 << 8);
+		}
+		break;
+
+	case 1:
+		if (strcmp (argv[3], "on") == 0) {
+			gpio->simple_dvo |=   (1 << 9);
+		} else {
+			gpio->simple_dvo &= ~(1 << 9);
+		}
+		break;
+
+	case 2:
+		if (strcmp (argv[3], "on") == 0) {
+			gpio->simple_dvo |=   (1 << 10);
+		} else {
+			gpio->simple_dvo &= ~(1 << 10);
+		}
+		break;
+
+	case 3:
+		if (strcmp (argv[3], "on") == 0) {
+			gpio->simple_dvo |=   (1 << 11);
+		} else {
+			gpio->simple_dvo &= ~(1 << 11);
+		}
+		break;
+
+	case 4:
+		if (strcmp (argv[3], "on") == 0) {
+			gpt->gpt4.emsr |=  (1 << 4);
+		} else {
+			gpt->gpt4.emsr &=  ~(1 << 4);
+		}
+		break;
+
+	case 5:
+		if (strcmp (argv[3], "on") == 0) {
+			gpt->gpt5.emsr |=  (1 << 4);
+		} else {
+			gpt->gpt5.emsr &=  ~(1 << 4);
+		}
+		break;
+
+	case 6:
+		if (strcmp (argv[3], "on") == 0) {
+			gpt->gpt6.emsr |=  (1 << 4);
+		} else {
+			gpt->gpt6.emsr &=  ~(1 << 4);
+		}
+		break;
+
+	case 7:
+		if (strcmp (argv[3], "on") == 0) {
+			gpt->gpt7.emsr |=  (1 << 4);
+		} else {
+			gpt->gpt7.emsr &=  ~(1 << 4);
+		}
+		break;
+#ifndef CONFIG_TQM5200S
+	case 24:
+		if (strcmp (argv[3], "on") == 0) {
+			*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) |=
+				(0x1 << 24);
+		} else {
+			*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) &=
+				~(0x1 << 24);
+		}
+		break;
+
+	case 25:
+		if (strcmp (argv[3], "on") == 0) {
+			*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) |=
+				(0x1 << 25);
+		} else {
+			*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) &=
+				~(0x1 << 25);
+		}
+		break;
+
+	case 26:
+		if (strcmp (argv[3], "on") == 0) {
+			*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) |=
+				(0x1 << 26);
+		} else {
+			*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) &=
+				~(0x1 << 26);
+		}
+		break;
+
+	case 27:
+		if (strcmp (argv[3], "on") == 0) {
+			*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) |=
+				(0x1 << 27);
+		} else {
+			*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_LOW) &=
+				~(0x1 << 27);
+		}
+		break;
+
+	case 48:
+		if (strcmp (argv[3], "on") == 0) {
+			*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) |=
+				(0x1 << 16);
+		} else {
+			*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) &=
+				~(0x1 << 16);
+		}
+		break;
+
+	case 49:
+		if (strcmp (argv[3], "on") == 0) {
+			*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) |=
+				(0x1 << 17);
+		} else {
+			*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) &=
+				~(0x1 << 17);
+		}
+		break;
+
+	case 50:
+		if (strcmp (argv[3], "on") == 0) {
+			*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) |=
+				(0x1 << 18);
+		} else {
+			*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) &=
+				~(0x1 << 18);
+		}
+		break;
+
+	case 51:
+		if (strcmp (argv[3], "on") == 0) {
+			*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) |=
+				(0x1 << 19);
+		} else {
+			*(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) &=
+				~(0x1 << 19);
+		}
+		break;
+#endif /* !CONFIG_TQM5200S */
+	default:
+		printf ("%s: invalid led number %s\n", __FUNCTION__, argv[2]);
+		return 1;
+	}
+
+	return 0;
+}
+#endif
+
+#if defined(CONFIG_STK52XX) || defined(CONFIG_FO300)
+/*
+ * return 1 on CAN initialization failure
+ * return 0 if no failure
+ */
+int can_init(void)
+{
+	static int init_done = 0;
+	int i;
+	struct mpc5xxx_mscan *can1 =
+		(struct mpc5xxx_mscan *)(CONFIG_SYS_MBAR + 0x0900);
+	struct mpc5xxx_mscan *can2 =
+		(struct mpc5xxx_mscan *)(CONFIG_SYS_MBAR + 0x0980);
+
+	/* GPIO configuration of the CAN pins is done in TQM5200.h */
+
+	if (!init_done) {
+		/* init CAN 1 */
+		can1->canctl1 |= 0x80;	/* CAN enable */
+		udelay(100);
+
+		i = 0;
+		can1->canctl0 |= 0x02;	/* sleep mode */
+		/* wait until sleep mode reached */
+		while (!(can1->canctl1 & 0x02)) {
+			udelay(10);
+		i++;
+		if (i == 10) {
+			printf ("%s: CAN1 initialize error, "
+				"can not enter sleep mode!\n",
+				__FUNCTION__);
+			return 1;
+		}
+		}
+		i = 0;
+		can1->canctl0 = 0x01;	/* enter init mode */
+		/* wait until init mode reached */
+		while (!(can1->canctl1 & 0x01)) {
+			udelay(10);
+			i++;
+			if (i == 10) {
+				printf ("%s: CAN1 initialize error, "
+					"can not enter init mode!\n",
+					__FUNCTION__);
+				return 1;
+			}
+		}
+		can1->canctl1 = 0x80;
+		can1->canctl1 |= 0x40;
+		can1->canbtr0 = 0x0F;
+		can1->canbtr1 = 0x7F;
+		can1->canidac &= ~(0x30);
+		can1->canidar1 = 0x00;
+		can1->canidar3 = 0x00;
+		can1->canidar5 = 0x00;
+		can1->canidar7 = 0x00;
+		can1->canidmr0 = 0xFF;
+		can1->canidmr1 = 0xFF;
+		can1->canidmr2 = 0xFF;
+		can1->canidmr3 = 0xFF;
+		can1->canidmr4 = 0xFF;
+		can1->canidmr5 = 0xFF;
+		can1->canidmr6 = 0xFF;
+		can1->canidmr7 = 0xFF;
+
+		i = 0;
+		can1->canctl0 &= ~(0x01);	/* leave init mode */
+		can1->canctl0 &= ~(0x02);
+		/* wait until init and sleep mode left */
+		while ((can1->canctl1 & 0x01) || (can1->canctl1 & 0x02)) {
+			udelay(10);
+			i++;
+			if (i == 10) {
+				printf ("%s: CAN1 initialize error, "
+					"can not leave init/sleep mode!\n",
+					__FUNCTION__);
+				return 1;
+			}
+		}
+
+		/* init CAN 2 */
+		can2->canctl1 |= 0x80;	/* CAN enable */
+		udelay(100);
+
+		i = 0;
+		can2->canctl0 |= 0x02;	/* sleep mode */
+		/* wait until sleep mode reached */
+		while (!(can2->canctl1 & 0x02))	{
+			udelay(10);
+			i++;
+			if (i == 10) {
+				printf ("%s: CAN2 initialize error, "
+					"can not enter sleep mode!\n",
+					__FUNCTION__);
+				return 1;
+			}
+		}
+		i = 0;
+		can2->canctl0 = 0x01;	/* enter init mode */
+		/* wait until init mode reached */
+		while (!(can2->canctl1 & 0x01))	{
+			udelay(10);
+			i++;
+			if (i == 10) {
+				printf ("%s: CAN2 initialize error, "
+					"can not enter init mode!\n",
+					__FUNCTION__);
+				return 1;
+			}
+		}
+		can2->canctl1 = 0x80;
+		can2->canctl1 |= 0x40;
+		can2->canbtr0 = 0x0F;
+		can2->canbtr1 = 0x7F;
+		can2->canidac &= ~(0x30);
+		can2->canidar1 = 0x00;
+		can2->canidar3 = 0x00;
+		can2->canidar5 = 0x00;
+		can2->canidar7 = 0x00;
+		can2->canidmr0 = 0xFF;
+		can2->canidmr1 = 0xFF;
+		can2->canidmr2 = 0xFF;
+		can2->canidmr3 = 0xFF;
+		can2->canidmr4 = 0xFF;
+		can2->canidmr5 = 0xFF;
+		can2->canidmr6 = 0xFF;
+		can2->canidmr7 = 0xFF;
+		can2->canctl0 &= ~(0x01);	/* leave init mode */
+		can2->canctl0 &= ~(0x02);
+
+		i = 0;
+		/* wait until init mode left */
+		while ((can2->canctl1 & 0x01) || (can2->canctl1 & 0x02)) {
+			udelay(10);
+			i++;
+			if (i == 10) {
+				printf ("%s: CAN2 initialize error, "
+					"can not leave init/sleep mode!\n",
+					__FUNCTION__);
+				return 1;
+			}
+		}
+		init_done = 1;
+	}
+	return 0;
+}
+
+/*
+ * return 1 on CAN failure
+ * return 0 if no failure
+ */
+int do_can(char * const argv[])
+{
+	int i;
+	struct mpc5xxx_mscan *can1 =
+		(struct mpc5xxx_mscan *)(CONFIG_SYS_MBAR + 0x0900);
+	struct mpc5xxx_mscan *can2 =
+		(struct mpc5xxx_mscan *)(CONFIG_SYS_MBAR + 0x0980);
+
+	/* send a message on CAN1 */
+	can1->cantbsel = 0x01;
+	can1->cantxfg.idr[0] = 0x55;
+	can1->cantxfg.idr[1] = 0x00;
+	can1->cantxfg.idr[1] &= ~0x8;
+	can1->cantxfg.idr[1] &= ~0x10;
+	can1->cantxfg.dsr[0] = 0xCC;
+	can1->cantxfg.dlr = 1;
+	can1->cantxfg.tbpr = 0;
+	can1->cantflg = 0x01;
+
+	i = 0;
+	while ((can1->cantflg & 0x01) == 0) {
+		i++;
+		if (i == 10) {
+			printf ("%s: CAN1 send timeout, "
+				"can not send message!\n",
+				__FUNCTION__);
+			return 1;
+		}
+		udelay(1000);
+	}
+	udelay(1000);
+
+	i = 0;
+	while (!(can2->canrflg & 0x01))	{
+		i++;
+		if (i == 10) {
+			printf ("%s: CAN2 receive timeout, "
+				"no message received!\n",
+				__FUNCTION__);
+			return 1;
+		}
+		udelay(1000);
+	}
+
+	if (can2->canrxfg.dsr[0] != 0xCC) {
+		printf ("%s: CAN2 receive error, "
+			 "data mismatch!\n",
+			__FUNCTION__);
+		return 1;
+	}
+
+	/* send a message on CAN2 */
+	can2->cantbsel = 0x01;
+	can2->cantxfg.idr[0] = 0x55;
+	can2->cantxfg.idr[1] = 0x00;
+	can2->cantxfg.idr[1] &= ~0x8;
+	can2->cantxfg.idr[1] &= ~0x10;
+	can2->cantxfg.dsr[0] = 0xCC;
+	can2->cantxfg.dlr = 1;
+	can2->cantxfg.tbpr = 0;
+	can2->cantflg = 0x01;
+
+	i = 0;
+	while ((can2->cantflg & 0x01) == 0) {
+		i++;
+		if (i == 10) {
+			printf ("%s: CAN2 send error, "
+				"can not send message!\n",
+				__FUNCTION__);
+			return 1;
+		}
+		udelay(1000);
+	}
+	udelay(1000);
+
+	i = 0;
+	while (!(can1->canrflg & 0x01))	{
+		i++;
+		if (i == 10) {
+			printf ("%s: CAN1 receive timeout, "
+				"no message received!\n",
+				__FUNCTION__);
+			return 1;
+		}
+		udelay(1000);
+	}
+
+	if (can1->canrxfg.dsr[0] != 0xCC) {
+		printf ("%s: CAN1 receive error 0x%02x\n",
+			__FUNCTION__, (can1->canrxfg.dsr[0]));
+		return 1;
+	}
+
+	return 0;
+}
+
+/*
+ * return 1 if rs232 port unknown
+ * return 2 on txd/rxd failure (only rs232 2)
+ * return 3 on rts/cts failure
+ * return 0 if no failure
+ */
+int do_rs232(char * const argv[])
+{
+	int error_status = 0;
+	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
+	struct mpc5xxx_psc *psc1 = (struct mpc5xxx_psc *)MPC5XXX_PSC1;
+
+	switch	(simple_strtoul(argv[2], NULL, 10)) {
+
+	case 1:
+		/* check RTS <-> CTS loop */
+		/* set rts to 0 */
+		psc1->op1 |= 0x01;
+
+		/* wait some time before requesting status */
+		udelay(10);
+
+		/* check status at cts */
+		if ((psc1->ip & 0x01) != 0) {
+			error_status = 3;
+			printf ("%s: failure at rs232_1, cts status is %d "
+				"(should be 0)\n",
+				__FUNCTION__, (psc1->ip & 0x01));
+		}
+
+		/* set rts to 1 */
+		psc1->op0 |= 0x01;
+
+		/* wait some time before requesting status */
+		udelay(10);
+
+		/* check status at cts */
+		if ((psc1->ip & 0x01) != 1) {
+			error_status = 3;
+			printf ("%s: failure at rs232_1, cts status is %d "
+				"(should be 1)\n",
+				__FUNCTION__, (psc1->ip & 0x01));
+		}
+
+		break;
+
+	case 2:
+		/* set PSC3_0, PSC3_2 as output and PSC3_1, PSC3_3 as input */
+		gpio->simple_ddr &= ~(0x00000F00);
+		gpio->simple_ddr |=   0x00000500;
+
+		/* check TXD <-> RXD loop */
+		/* set TXD to 1 */
+		gpio->simple_dvo |=   (1 << 8);
+
+		/* wait some time before requesting status */
+		udelay(10);
+
+		if ((gpio->simple_ival & 0x00000200) != 0x00000200) {
+			error_status = 2;
+			printf ("%s: failure at rs232_2, rxd status is %d "
+				"(should be 1)\n",
+				__FUNCTION__,
+				(gpio->simple_ival & 0x00000200) >> 9);
+		}
+
+		/* set TXD to 0 */
+		gpio->simple_dvo &= ~(1 << 8);
+
+		/* wait some time before requesting status */
+		udelay(10);
+
+		if ((gpio->simple_ival & 0x00000200) != 0x00000000) {
+			error_status = 2;
+			printf ("%s: failure at rs232_2, rxd status is %d "
+				"(should be 0)\n",
+				__FUNCTION__,
+				(gpio->simple_ival & 0x00000200) >> 9);
+		}
+
+		/* check RTS <-> CTS loop */
+		/* set RTS to 1 */
+		gpio->simple_dvo |=   (1 << 10);
+
+		/* wait some time before requesting status */
+		udelay(10);
+
+		if ((gpio->simple_ival & 0x00000800) != 0x00000800) {
+			error_status = 3;
+			printf ("%s: failure at rs232_2, cts status is %d "
+				"(should be 1)\n",
+				__FUNCTION__,
+				(gpio->simple_ival & 0x00000800) >> 11);
+		}
+
+		/* set RTS to 0 */
+		gpio->simple_dvo &= ~(1 << 10);
+
+		/* wait some time before requesting status */
+		udelay(10);
+
+		if ((gpio->simple_ival & 0x00000800) != 0x00000000) {
+			error_status = 3;
+			printf ("%s: failure at rs232_2, cts status is %d "
+				"(should be 0)\n",
+				__FUNCTION__,
+				(gpio->simple_ival & 0x00000800) >> 11);
+		}
+
+		/* set PSC3_0, PSC3_1, PSC3_2 and PSC3_3 as output */
+		gpio->simple_ddr &= ~(0x00000F00);
+		gpio->simple_ddr |=   0x00000F00;
+		break;
+
+	default:
+		printf ("%s: invalid rs232 number %s\n", __FUNCTION__, argv[2]);
+		error_status = 1;
+		break;
+	}
+
+	return error_status;
+}
+
+#if !defined(CONFIG_FO300) && !defined(CONFIG_TQM5200S)
+static void sm501_backlight (unsigned int state)
+{
+	if (state == BL_ON) {
+		*(vu_long *)(SM501_MMIO_BASE+SM501_PANEL_DISPLAY_CONTROL) |=
+			(1 << 26) | (1 << 27);
+	} else if (state == BL_OFF)
+		*(vu_long *)(SM501_MMIO_BASE+SM501_PANEL_DISPLAY_CONTROL) &=
+			~((1 << 26) | (1 << 27));
+}
+#endif /* !CONFIG_FO300 & !CONFIG_TQM5200S */
+
+int cmd_fkt(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	int rcode;
+
+#ifdef CONFIG_STK52XX_REV100
+	printf ("Revision 100 of STK52XX not supported!\n");
+	return 1;
+#endif
+#if defined(CONFIG_STK52XX)
+	led_init();
+#endif
+	can_init();
+
+	switch (argc) {
+
+	case 0:
+	case 1:
+		break;
+
+	case 2:
+		if (strncmp (argv[1], "can", 3) == 0) {
+			rcode = do_can (argv);
+			if (rcode == 0)
+				printf ("OK\n");
+			else
+				printf ("Error\n");
+			return rcode;
+		}
+		break;
+
+	case 3:
+		if (strncmp (argv[1], "rs232", 3) == 0) {
+			rcode = do_rs232 (argv);
+			if (rcode == 0)
+				printf ("OK\n");
+			else
+				printf ("Error\n");
+			return rcode;
+#if !defined(CONFIG_FO300) && !defined(CONFIG_TQM5200S)
+		} else if (strncmp (argv[1], "backlight", 4) == 0) {
+			if (strncmp (argv[2], "on", 2) == 0) {
+				sm501_backlight (BL_ON);
+				return 0;
+			}
+			else if (strncmp (argv[2], "off", 3) == 0) {
+				sm501_backlight (BL_OFF);
+				return 0;
+			}
+#endif /* !CONFIG_FO300 & !CONFIG_TQM5200S */
+		}
+		break;
+
+#if defined(CONFIG_STK52XX)
+	case 4:
+		if (strcmp (argv[1], "led") == 0) {
+			return (do_led (argv));
+		}
+		break;
+#endif
+
+	default:
+		break;
+	}
+
+	printf ("Usage:\nfkt cmd [arg1] [arg2] ...\n");
+	return 1;
+}
+
+
+U_BOOT_CMD(
+	sound ,    5,    1,     cmd_sound,
+	"Sound sub-system",
+	"saw [duration] [freq] [channel]\n"
+	"    - generate sawtooth for 'duration' ms with frequency 'freq'\n"
+	"      on left \"l\" or right \"r\" channel\n"
+	"sound square [duration] [freq] [channel]\n"
+	"    - generate squarewave for 'duration' ms with frequency 'freq'\n"
+	"      on left \"l\" or right \"r\" channel\n"
+	"pcm1772 reg val"
+);
+
+U_BOOT_CMD(
+	wav ,    3,    1,     cmd_wav,
+	"play wav file",
+	"[addr] [bytes]\n"
+	"    - play wav file at address 'addr' with length 'bytes'"
+);
+
+U_BOOT_CMD(
+	beep ,    2,    1,     cmd_beep,
+	"play short beep",
+	"[channel]\n"
+	"    - play short beep on \"l\"eft or \"r\"ight channel"
+);
+#endif /* CONFIG_STK52XX  || CONFIG_FO300 */
+
+#if defined(CONFIG_STK52XX)
+U_BOOT_CMD(
+	fkt ,	4,	1,	cmd_fkt,
+	"Function test routines",
+	"led number on/off\n"
+	"     - 'number's like printed on STK52XX board\n"
+	"fkt can\n"
+	"     - loopback plug for X83 required\n"
+	"fkt rs232 number\n"
+	"     - loopback plug(s) for X2 required"
+#ifndef CONFIG_TQM5200S
+	"\n"
+	"fkt backlight on/off\n"
+	"     - switch backlight on or off"
+#endif /* !CONFIG_TQM5200S */
+);
+#elif defined(CONFIG_FO300)
+U_BOOT_CMD(
+	fkt ,	3,	1,	cmd_fkt,
+	"Function test routines",
+	"fkt can\n"
+	"     - loopback plug for X16/X29 required\n"
+	"fkt rs232 number\n"
+	"     - loopback plug(s) for X21/X22 required"
+);
+#endif
+#endif
diff --git a/board/tqc/tqm5200/mt48lc16m16a2-75.h b/board/tqc/tqm5200/mt48lc16m16a2-75.h
new file mode 100644
index 0000000000..3d9979664f
--- /dev/null
+++ b/board/tqc/tqm5200/mt48lc16m16a2-75.h
@@ -0,0 +1,18 @@ 
+/*
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#define SDRAM_DDR	0		/* is SDR */
+
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE	0x00CD0000
+/* #define SDRAM_MODE	0x008D0000 */ /* CAS latency 2 */
+#define SDRAM_CONTROL	0x504F0000
+#define SDRAM_CONFIG1	0xD2322800
+/* #define SDRAM_CONFIG1	0xD2222800 */ /* CAS latency 2 */
+/*#define SDRAM_CONFIG1	0xD7322800 */ /* SDRAM controller bug workaround */
+#define SDRAM_CONFIG2	0x8AD70000
+/*#define SDRAM_CONFIG2	0xDDD70000 */ /* SDRAM controller bug workaround */
diff --git a/board/tqc/tqm5200/tqm5200.c b/board/tqc/tqm5200/tqm5200.c
new file mode 100644
index 0000000000..cb99afdb90
--- /dev/null
+++ b/board/tqc/tqm5200/tqm5200.c
@@ -0,0 +1,875 @@ 
+/*
+ * (C) Copyright 2003-2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * (C) Copyright 2004-2006
+ * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <console.h>
+#include <mpc5xxx.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <libfdt.h>
+#include <netdev.h>
+#include <video.h>
+
+#ifdef CONFIG_VIDEO_SM501
+#include <sm501.h>
+#endif
+
+#if defined(CONFIG_MPC5200_DDR)
+#include "mt46v16m16-75.h"
+#else
+#include "mt48lc16m16a2-75.h"
+#endif
+
+#ifdef CONFIG_OF_LIBFDT
+#include <fdt_support.h>
+#endif /* CONFIG_OF_LIBFDT */
+
+D