From patchwork Mon Jun 19 02:17:59 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Azhar Shaikh X-Patchwork-Id: 777540 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.sourceforge.net (lists.sourceforge.net [216.34.181.88]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3wrZQH3lfRz9s3w for ; Mon, 19 Jun 2017 12:18:15 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=sourceforge.net header.i=@sourceforge.net header.b="HoONXS2h"; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=sf.net header.i=@sf.net header.b="QBKfzB/s"; dkim-atps=neutral Received: from localhost ([127.0.0.1] helo=sfs-ml-1.v29.ch3.sourceforge.com) by sfs-ml-1.v29.ch3.sourceforge.com with esmtp (Exim 4.76) (envelope-from ) id 1dMmGX-0005vC-Uf; Mon, 19 Jun 2017 02:18:09 +0000 Received: from sog-mx-4.v43.ch3.sourceforge.com ([172.29.43.194] helo=mx.sourceforge.net) by sfs-ml-1.v29.ch3.sourceforge.com with esmtp (Exim 4.76) (envelope-from ) id 1dMmGX-0005v7-3C for tpmdd-devel@lists.sourceforge.net; Mon, 19 Jun 2017 02:18:09 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=sourceforge.net; s=x; h=References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From; bh=wwl4OR4bBs3WiORWyPacVJSD6O6tSxlaGB5VxdkrDf8=; b=HoONXS2haewwkTfpYSB1ol0ZiobMDPkCL2bX+xUBqZf/5Gozvw/gRMY6KVU4ebMur9PoGEuC4lbs2GPzKrbfBy/+hV7v3PneLKB+hfFnFrPsyL1mua2bFJL8/7LiFT821xBi8M+GITQzwo9tb8GPg2vSu8da4VFGOrLKw4SWRjI=; DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=sf.net; s=x; h=References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From; bh=wwl4OR4bBs3WiORWyPacVJSD6O6tSxlaGB5VxdkrDf8=; b=QBKfzB/sLVp9h3Fac+S4IGGSbVVajf7IzxmGzH3uynIUn7CyOq0GuvuLr0wStmwV03vojCTvsFfuuu2zmCo2C7vvk0MMpGU0dMz+LATDC7Su0OUlRWZXzyPN71RdpnceozSThweK2NW9aMt/AcTc2eTT3AwX/WpNY0kp3Oa2OE4=; Received-SPF: fail (sog-mx-4.v43.ch3.sourceforge.com: domain of intel.com does not designate 134.134.136.31 as permitted sender) client-ip=134.134.136.31; envelope-from=azhar.shaikh@intel.com; helo=mga06.intel.com; Received: from mga06.intel.com ([134.134.136.31]) by sog-mx-4.v43.ch3.sourceforge.com with esmtps (TLSv1:AES256-SHA:256) (Exim 4.76) id 1dMmGT-0002NM-M6 for tpmdd-devel@lists.sourceforge.net; Mon, 19 Jun 2017 02:18:09 +0000 Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga104.jf.intel.com with ESMTP; 18 Jun 2017 19:17:59 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.39,359,1493708400"; d="scan'208";a="982413903" Received: from otc-chromeosbuild-0.jf.intel.com ([10.54.30.57]) by orsmga003.jf.intel.com with ESMTP; 18 Jun 2017 19:17:59 -0700 From: Azhar Shaikh To: jarkko.sakkinen@linux.intel.com, jgunthorpe@obsidianresearch.com, tpmdd-devel@lists.sourceforge.net, linux-kernel@vger.kernel.org Date: Sun, 18 Jun 2017 19:17:59 -0700 Message-Id: <1497838679-147957-1-git-send-email-azhar.shaikh@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1496369044-38234-1-git-send-email-azhar.shaikh@intel.com> References: <1496369044-38234-1-git-send-email-azhar.shaikh@intel.com> X-Spam-Score: 1.7 (+) X-Spam-Report: Spam Filtering performed by mx.sourceforge.net. See http://spamassassin.org/tag/ for more details. 4.0 SPF_CHECK_FAIL SPF reports sender host as NOT permitted to send mails from -0.0 T_RP_MATCHES_RCVD Envelope sender domain matches handover relay domain 0.9 SPF_FAIL SPF: sender does not match SPF record (fail) -3.2 AWL AWL: Adjusted score from AWL reputation of From: address X-Headers-End: 1dMmGT-0002NM-M6 Subject: [tpmdd-devel] [PATCH v5] tpm: Enable CLKRUN protocol for Braswell systems X-BeenThere: tpmdd-devel@lists.sourceforge.net X-Mailman-Version: 2.1.21 Precedence: list List-Id: Tpm Device Driver maintainance List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-security-module@vger.kernel.org, azhar.shaikh@intel.com MIME-Version: 1.0 Errors-To: tpmdd-devel-bounces@lists.sourceforge.net To overcome a hardware limitation on Intel Braswell systems, disable CLKRUN protocol during TPM transactions and re-enable once the transaction is completed. Signed-off-by: Azhar Shaikh Reviewed-by: Jarkko Sakkinen Tested-by: Jarkko Sakkinen (compilation) --- Changes from v1: - Add CONFIG_X86 around disable_lpc_clk_run() and enable_lpc_clk_run() to avoid - build breakage on architectures which do not implement kmap_atomic_pfn() Changes from v2: - Use ioremap()/iounmap() instead of kmap_atomic_pfn()/kunmap_atomic() - Move is_bsw() and all macros from tpm.h to tpm_tis.c file. - Add the is_bsw() check in disable_lpc_clk_run() and enable_lpc_clk_run() - instead of adding it in each read/write API. Changes from v3: - Move the code under #ifdef CONFIG_X86 and create stub functions for everything else - Rename the functions disable_lpc_clk_run() -> tpm_platform_begin_xfer() and - enable_lpc_clk_run() -> tpm_platform_end_xfer() - Remove wmb() - Correct the parameters for outb() Changes from v4: - Rebased to apply on git://git.infradead.org/users/jjs/linux-tpmdd.git drivers/char/tpm/tpm.h | 4 ++ drivers/char/tpm/tpm_tis.c | 112 +++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 116 insertions(+) diff --git a/drivers/char/tpm/tpm.h b/drivers/char/tpm/tpm.h index 1df0521138d3..cdd261383dea 100644 --- a/drivers/char/tpm/tpm.h +++ b/drivers/char/tpm/tpm.h @@ -36,6 +36,10 @@ #include #include +#ifdef CONFIG_X86 +#include +#endif + enum tpm_const { TPM_MINOR = 224, /* officially assigned */ TPM_BUFSIZE = 4096, diff --git a/drivers/char/tpm/tpm_tis.c b/drivers/char/tpm/tpm_tis.c index b14d4aa97af8..506e62ca3576 100644 --- a/drivers/char/tpm/tpm_tis.c +++ b/drivers/char/tpm/tpm_tis.c @@ -132,13 +132,93 @@ static int check_acpi_tpm2(struct device *dev) } #endif +#ifdef CONFIG_X86 +#define INTEL_LEGACY_BLK_BASE_ADDR 0xFED08000 +#define ILB_REMAP_SIZE 0x100 +#define LPC_CNTRL_REG_OFFSET 0x84 +#define LPC_CLKRUN_EN (1 << 2) + +void __iomem *ilb_base_addr; + +static inline bool is_bsw(void) +{ + return ((boot_cpu_data.x86_model == INTEL_FAM6_ATOM_AIRMONT) ? 1 : 0); +} + +/** + * tpm_platform_begin_xfer() - clear LPC CLKRUN_EN i.e. clocks will be running + */ +static void tpm_platform_begin_xfer(void) +{ + u32 clkrun_val; + + if (!is_bsw()) + return; + + clkrun_val = ioread32(ilb_base_addr + LPC_CNTRL_REG_OFFSET); + + /* Disable LPC CLKRUN# */ + clkrun_val &= ~LPC_CLKRUN_EN; + iowrite32(clkrun_val, ilb_base_addr + LPC_CNTRL_REG_OFFSET); + + /* + * Write any random value on port 0x80 which is on LPC, to make + * sure LPC clock is running before sending any TPM command. + */ + outb(0xCC, 0x80); + +} + +/** + * tpm_platform_end_xfer() - set LPC CLKRUN_EN i.e. clocks can be turned off + */ +static void tpm_platform_end_xfer(void) +{ + u32 clkrun_val; + + if (!is_bsw()) + return; + + clkrun_val = ioread32(ilb_base_addr + LPC_CNTRL_REG_OFFSET); + + /* Enable LPC CLKRUN# */ + clkrun_val |= LPC_CLKRUN_EN; + iowrite32(clkrun_val, ilb_base_addr + LPC_CNTRL_REG_OFFSET); + + /* + * Write any random value on port 0x80 which is on LPC, to make + * sure LPC clock is running before sending any TPM command. + */ + outb(0xCC, 0x80); + +} +#else +static inline bool is_bsw(void) +{ + return false; +} + +static void tpm_platform_begin_xfer(void) +{ +} + +static void tpm_platform_end_xfer(void) +{ +} +#endif + static int tpm_tcg_read_bytes(struct tpm_tis_data *data, u32 addr, u16 len, u8 *result) { struct tpm_tis_tcg_phy *phy = to_tpm_tis_tcg_phy(data); + tpm_platform_begin_xfer(); + while (len--) *result++ = ioread8(phy->iobase + addr); + + tpm_platform_end_xfer(); + return 0; } @@ -147,8 +227,13 @@ static int tpm_tcg_write_bytes(struct tpm_tis_data *data, u32 addr, u16 len, { struct tpm_tis_tcg_phy *phy = to_tpm_tis_tcg_phy(data); + tpm_platform_begin_xfer(); + while (len--) iowrite8(*value++, phy->iobase + addr); + + tpm_platform_end_xfer(); + return 0; } @@ -156,7 +241,12 @@ static int tpm_tcg_read16(struct tpm_tis_data *data, u32 addr, u16 *result) { struct tpm_tis_tcg_phy *phy = to_tpm_tis_tcg_phy(data); + tpm_platform_begin_xfer(); + *result = ioread16(phy->iobase + addr); + + tpm_platform_end_xfer(); + return 0; } @@ -164,7 +254,12 @@ static int tpm_tcg_read32(struct tpm_tis_data *data, u32 addr, u32 *result) { struct tpm_tis_tcg_phy *phy = to_tpm_tis_tcg_phy(data); + tpm_platform_begin_xfer(); + *result = ioread32(phy->iobase + addr); + + tpm_platform_end_xfer(); + return 0; } @@ -172,7 +267,12 @@ static int tpm_tcg_write32(struct tpm_tis_data *data, u32 addr, u32 value) { struct tpm_tis_tcg_phy *phy = to_tpm_tis_tcg_phy(data); + tpm_platform_begin_xfer(); + iowrite32(value, phy->iobase + addr); + + tpm_platform_end_xfer(); + return 0; } @@ -230,6 +330,12 @@ static int tpm_tis_pnp_init(struct pnp_dev *pnp_dev, else tpm_info.irq = -1; +#ifdef CONFIG_X86 + if (is_bsw()) + ilb_base_addr = ioremap(INTEL_LEGACY_BLK_BASE_ADDR, + ILB_REMAP_SIZE); +#endif + return tpm_tis_init(&pnp_dev->dev, &tpm_info); } @@ -253,6 +359,12 @@ static void tpm_tis_pnp_remove(struct pnp_dev *dev) tpm_chip_unregister(chip); tpm_tis_remove(chip); + +#ifdef CONFIG_X86 + if (is_bsw()) + iounmap(ilb_base_addr); +#endif + } static struct pnp_driver tis_pnp_driver = {