From patchwork Thu Jan 6 16:41:13 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kumar Gala X-Patchwork-Id: 77735 X-Patchwork-Delegate: galak@kernel.crashing.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 41C85B70CC for ; Fri, 7 Jan 2011 03:41:27 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 1184C2816E; Thu, 6 Jan 2011 17:41:25 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id E3HdkWdDg5Xv; Thu, 6 Jan 2011 17:41:24 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 2BD5428170; Thu, 6 Jan 2011 17:41:23 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 12A9A28170 for ; Thu, 6 Jan 2011 17:41:21 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id ZBG-2ZdSICJP for ; Thu, 6 Jan 2011 17:41:19 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) by theia.denx.de (Postfix) with ESMTPS id 05BDF2816E for ; Thu, 6 Jan 2011 17:41:17 +0100 (CET) Received: from localhost (localhost.localdomain [127.0.0.1]) by gate.crashing.org (8.14.1/8.13.8) with ESMTP id p06GfDHF025360 for ; Thu, 6 Jan 2011 10:41:14 -0600 From: Kumar Gala To: u-boot@lists.denx.de Date: Thu, 6 Jan 2011 10:41:13 -0600 Message-Id: <1294332073-28231-1-git-send-email-galak@kernel.crashing.org> X-Mailer: git-send-email 1.6.0.6 Subject: [U-Boot] [PATCH] powerpc/85xx: Rework corenet_ds pci_init_board to use common FSL PCIe code X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.9 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Remove duplicated code in corenet_ds boards and utilize the common fsl_pcie_init_board(). Signed-off-by: Kumar Gala --- board/freescale/corenet_ds/pci.c | 118 +------------------------------------- 1 files changed, 2 insertions(+), 116 deletions(-) diff --git a/board/freescale/corenet_ds/pci.c b/board/freescale/corenet_ds/pci.c index 775b623..18a75de 100644 --- a/board/freescale/corenet_ds/pci.c +++ b/board/freescale/corenet_ds/pci.c @@ -1,5 +1,5 @@ /* - * Copyright 2007-2010 Freescale Semiconductor, Inc. + * Copyright 2007-2011 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -28,123 +28,9 @@ #include #include -#ifdef CONFIG_PCIE1 -static struct pci_controller pcie1_hose; -#endif - -#ifdef CONFIG_PCIE2 -static struct pci_controller pcie2_hose; -#endif - -#ifdef CONFIG_PCIE3 -static struct pci_controller pcie3_hose; -#endif - -#ifdef CONFIG_PCIE4 -static struct pci_controller pcie4_hose; -#endif - void pci_init_board(void) { - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - struct fsl_pci_info pci_info[4]; - u32 devdisr; - int first_free_busno = 0; - int num = 0; - - int pcie_ep, pcie_configured; - - devdisr = in_be32(&gur->devdisr); - - debug (" pci_init_board: devdisr=%x\n", devdisr); - -#ifdef CONFIG_PCIE1 - pcie_configured = is_serdes_configured(PCIE1); - - if (pcie_configured && !(devdisr & FSL_CORENET_DEVDISR_PCIE1)) { - set_next_law(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, - LAW_TRGT_IF_PCIE_1); - set_next_law(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, - LAW_TRGT_IF_PCIE_1); - SET_STD_PCIE_INFO(pci_info[num], 1); - pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); - printf("PCIE1: connected to Slot 1 as %s (base addr %lx)\n", - pcie_ep ? "End Point" : "Root Complex", - pci_info[num].regs); - first_free_busno = fsl_pci_init_port(&pci_info[num++], - &pcie1_hose, first_free_busno); - } else { - printf("PCIE1: disabled\n"); - } -#else - setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_PCIE1); /* disable */ -#endif - -#ifdef CONFIG_PCIE2 - pcie_configured = is_serdes_configured(PCIE2); - - if (pcie_configured && !(devdisr & FSL_CORENET_DEVDISR_PCIE2)) { - set_next_law(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_512M, - LAW_TRGT_IF_PCIE_2); - set_next_law(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, - LAW_TRGT_IF_PCIE_2); - SET_STD_PCIE_INFO(pci_info[num], 2); - pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs); - printf("PCIE2: connected to Slot 3 as %s (base addr %lx)\n", - pcie_ep ? "End Point" : "Root Complex", - pci_info[num].regs); - first_free_busno = fsl_pci_init_port(&pci_info[num++], - &pcie2_hose, first_free_busno); - } else { - printf("PCIE2: disabled\n"); - } -#else - setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_PCIE2); /* disable */ -#endif - -#ifdef CONFIG_PCIE3 - pcie_configured = is_serdes_configured(PCIE3); - - if (pcie_configured && !(devdisr & FSL_CORENET_DEVDISR_PCIE3)) { - set_next_law(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_512M, - LAW_TRGT_IF_PCIE_3); - set_next_law(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_64K, - LAW_TRGT_IF_PCIE_3); - SET_STD_PCIE_INFO(pci_info[num], 3); - pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs); - printf("PCIE3: connected to Slot 2 as %s (base addr %lx)\n", - pcie_ep ? "End Point" : "Root Complex", - pci_info[num].regs); - first_free_busno = fsl_pci_init_port(&pci_info[num++], - &pcie3_hose, first_free_busno); - } else { - printf("PCIE3: disabled\n"); - } -#else - setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_PCIE3); /* disable */ -#endif - -#ifdef CONFIG_PCIE4 - pcie_configured = is_serdes_configured(PCIE4); - - if (pcie_configured && !(devdisr & FSL_CORENET_DEVDISR_PCIE4)) { - set_next_law(CONFIG_SYS_PCIE4_MEM_PHYS, LAW_SIZE_512M, - LAW_TRGT_IF_PCIE_4); - set_next_law(CONFIG_SYS_PCIE4_IO_PHYS, LAW_SIZE_64K, - LAW_TRGT_IF_PCIE_4); - SET_STD_PCIE_INFO(pci_info[num], 4); - pcie_ep = fsl_setup_hose(&pcie4_hose, pci_info[num].regs); - printf("PCIE4: connected to as %s (base addr %lx)\n", - pcie_ep ? "End Point" : "Root Complex", - pci_info[num].regs); - first_free_busno = fsl_pci_init_port(&pci_info[num++], - &pcie4_hose, first_free_busno); - } else { - printf("PCIE4: disabled\n"); - } -#else - setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_PCIE4); /* disable */ -#endif + fsl_pcie_init_board(0); } void pci_of_setup(void *blob, bd_t *bd)