From patchwork Wed Jan 5 00:19:25 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Fang, Changpeng" X-Patchwork-Id: 77552 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id 20B56B6F2B for ; Wed, 5 Jan 2011 11:20:39 +1100 (EST) Received: (qmail 5943 invoked by alias); 5 Jan 2011 00:20:05 -0000 Received: (qmail 5399 invoked by uid 22791); 5 Jan 2011 00:19:48 -0000 X-SWARE-Spam-Status: No, hits=-1.8 required=5.0 tests=AWL, BAYES_00, TW_AV, TW_BD, TW_VZ, TW_ZB X-Spam-Check-By: sourceware.org Received: from tx2ehsobe003.messaging.microsoft.com (HELO TX2EHSOBE006.bigfish.com) (65.55.88.13) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Wed, 05 Jan 2011 00:19:32 +0000 Received: from mail15-tx2-R.bigfish.com (10.9.14.251) by TX2EHSOBE006.bigfish.com (10.9.40.26) with Microsoft SMTP Server id 14.1.225.8; Wed, 5 Jan 2011 00:19:28 +0000 Received: from mail15-tx2 (localhost.localdomain [127.0.0.1]) by mail15-tx2-R.bigfish.com (Postfix) with ESMTP id 3E32D2E0104 for ; Wed, 5 Jan 2011 00:19:28 +0000 (UTC) X-SpamScore: -3 X-BigFish: VPS-3(zz4015Lzz1202hzzz32i668h34h61h) X-Spam-TCS-SCL: 0:0 X-Forefront-Antispam-Report: KIP:(null); UIP:(null); IPVD:NLI; H:ausb3twp02.amd.com; RD:none; EFVD:NLI Received: from mail15-tx2 (localhost.localdomain [127.0.0.1]) by mail15-tx2 (MessageSwitch) id 129418676847813_12727; Wed, 5 Jan 2011 00:19:28 +0000 (UTC) Received: from TX2EHSMHS034.bigfish.com (unknown [10.9.14.250]) by mail15-tx2.bigfish.com (Postfix) with ESMTP id 0887B1010050 for ; Wed, 5 Jan 2011 00:19:28 +0000 (UTC) Received: from ausb3twp02.amd.com (163.181.249.109) by TX2EHSMHS034.bigfish.com (10.9.99.134) with Microsoft SMTP Server id 14.1.225.8; Wed, 5 Jan 2011 00:19:27 +0000 X-M-MSG: Received: from sausexedgep01.amd.com (sausexedgep01-ext.amd.com [163.181.249.72]) (using TLSv1 with cipher AES128-SHA (128/128 bits)) (No client certificate requested) by ausb3twp02.amd.com (Tumbleweed MailGate 3.7.2) with ESMTP id 22513C87B8 for ; Tue, 4 Jan 2011 18:19:24 -0600 (CST) Received: from sausexhtp02.amd.com (163.181.3.152) by sausexedgep01.amd.com (163.181.36.54) with Microsoft SMTP Server (TLS) id 8.3.106.1; Tue, 4 Jan 2011 18:22:34 -0600 Received: from SAUSEXMBP01.amd.com ([163.181.3.198]) by sausexhtp02.amd.com ([163.181.3.152]) with mapi; Tue, 4 Jan 2011 18:19:25 -0600 From: "Fang, Changpeng" To: "gcc-patches@gcc.gnu.org" Date: Tue, 4 Jan 2011 18:19:25 -0600 Subject: Bobcat (btver1) Enablement Message-ID: MIME-Version: 1.0 X-OriginatorOrg: amd.com Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Hi, This patch does the basic enablement for AMD's first APU architecture -- Bobcat. It defines -march=btver1 and -mtune=btver1, and lets -march=native correctly recognizes bobcat. In addition, it does limited tuning for bobcat. The patch passed bootstrapping and gcc regression tests on x86_64-unknown-linux-gnu. Programs (cou2000, cpu2006 and polyhedron 2005, etc) compile and run OK with -march=btver1 on the bobcat system. Is it OK to commit to trunk now? Thanks, Changpeng From 5a97154db22f3bcc06125f55cd1f632dc4374626 Mon Sep 17 00:00:00 2001 From: Changpeng Fang Date: Tue, 4 Jan 2011 11:45:32 -0800 Subject: [PATCH] Bobcat (btver1) Enablement * config.gcc (i[34567]86-*-linux* | ...): Add btver1. (case ${target}): Add btver1. * config/i386/driver-i386.c (host_detect_local_cpu): Let -march=native recognize btver1 processors. * config/i386/i386-c.c (ix86_target_macros_internal): Add btver1 def_and_undef * config/i386/i386.c (struct processor_costs btver1_cost): New btver1 cost table. (m_BTVER1): New definition. ( m_AMD_MULTIPLE): Includes m_BTVER1. (initial_ix86_tune_features): Add btver1 tune. (processor_target_table): Add btver1 entry. (static const char *const cpu_names): Add btver1 entry. (software_prefetching_beneficial_p): Add btver1. (ix86_option_override_internal): Add btver1 instruction sets. (ix86_issue_rate): Add btver1. (ix86_adjust_cost): Add btver1. * config/i386/i386.h (TARGET_BTVER1): New definition. (enum target_cpu_default): Add TARGET_CPU_DEFAULT_btver1. (enum processor_type): Add PROCESSOR_BTVER1. * config/i386/i386.md (define_attr "cpu"): Add btver1. --- gcc/config.gcc | 22 ++++++--- gcc/config/i386/driver-i386.c | 5 ++ gcc/config/i386/i386-c.c | 7 +++ gcc/config/i386/i386.c | 105 ++++++++++++++++++++++++++++++++++++++--- gcc/config/i386/i386.h | 3 + gcc/config/i386/i386.md | 2 +- 6 files changed, 129 insertions(+), 15 deletions(-) diff --git a/gcc/config.gcc b/gcc/config.gcc index 81eeb84..96ff86c 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -1236,7 +1236,7 @@ i[34567]86-*-linux* | i[34567]86-*-kfreebsd*-gnu | i[34567]86-*-knetbsd*-gnu | i need_64bit_hwint=yes need_64bit_isa=yes case X"${with_cpu}" in - Xgeneric|Xatom|Xcore2|Xcorei7|Xcorei7-avx|Xnocona|Xx86-64|Xbdver1|Xamdfam10|Xbarcelona|Xk8|Xopteron|Xathlon64|Xathlon-fx|Xathlon64-sse3|Xk8-sse3|Xopteron-sse3) + Xgeneric|Xatom|Xcore2|Xcorei7|Xcorei7-avx|Xnocona|Xx86-64|Xbdver1|Xbtver1|Xamdfam10|Xbarcelona|Xk8|Xopteron|Xathlon64|Xathlon-fx|Xathlon64-sse3|Xk8-sse3|Xopteron-sse3) ;; X) if test x$with_cpu_64 = x; then @@ -1245,7 +1245,7 @@ i[34567]86-*-linux* | i[34567]86-*-kfreebsd*-gnu | i[34567]86-*-knetbsd*-gnu | i ;; *) echo "Unsupported CPU used in --with-cpu=$with_cpu, supported values:" 1>&2 - echo "generic atom core2 corei7 corei7-avx nocona x86-64 bdver1 amdfam10 barcelona k8 opteron athlon64 athlon-fx athlon64-sse3 k8-sse3 opteron-sse3" 1>&2 + echo "generic atom core2 corei7 corei7-avx nocona x86-64 bdver1 btver1 amdfam10 barcelona k8 opteron athlon64 athlon-fx athlon64-sse3 k8-sse3 opteron-sse3" 1>&2 exit 1 ;; esac @@ -1374,7 +1374,7 @@ i[34567]86-*-solaris2*) need_64bit_isa=yes use_gcc_stdint=wrap case X"${with_cpu}" in - Xgeneric|Xatom|Xcore2|Xcorei7|Xcorei7-avx|Xnocona|Xx86-64|Xbdver1|Xamdfam10|Xbarcelona|Xk8|Xopteron|Xathlon64|Xathlon-fx|Xathlon64-sse3|Xk8-sse3|Xopteron-sse3) + Xgeneric|Xatom|Xcore2|Xcorei7|Xcorei7-avx|Xnocona|Xx86-64|Xbdver1|Xbtver1|Xamdfam10|Xbarcelona|Xk8|Xopteron|Xathlon64|Xathlon-fx|Xathlon64-sse3|Xk8-sse3|Xopteron-sse3) ;; X) if test x$with_cpu_64 = x; then @@ -1383,7 +1383,7 @@ i[34567]86-*-solaris2*) ;; *) echo "Unsupported CPU used in --with-cpu=$with_cpu, supported values:" 1>&2 - echo "generic atom core2 corei7 corei7-avx nocona x86-64 bdver1 amdfam10 barcelona k8 opteron athlon64 athlon-fx athlon64-sse3 k8-sse3 opteron-sse3" 1>&2 + echo "generic atom core2 corei7 corei7-avx nocona x86-64 bdver1 btver1 amdfam10 barcelona k8 opteron athlon64 athlon-fx athlon64-sse3 k8-sse3 opteron-sse3" 1>&2 exit 1 ;; esac @@ -1454,7 +1454,7 @@ i[34567]86-*-mingw* | x86_64-*-mingw*) if test x$enable_targets = xall; then tm_defines="${tm_defines} TARGET_BI_ARCH=1" case X"${with_cpu}" in - Xgeneric|Xatom|Xcore2|Xcorei7|Xcorei7-avx|Xnocona|Xx86-64|Xbdver1|Xamdfam10|Xbarcelona|Xk8|Xopteron|Xathlon64|Xathlon-fx|Xathlon64-sse3|Xk8-sse3|Xopteron-sse3) + Xgeneric|Xatom|Xcore2|Xcorei7|Xcorei7-avx|Xnocona|Xx86-64|Xbdver1|Xbtver1|Xamdfam10|Xbarcelona|Xk8|Xopteron|Xathlon64|Xathlon-fx|Xathlon64-sse3|Xk8-sse3|Xopteron-sse3) ;; X) if test x$with_cpu_64 = x; then @@ -1463,7 +1463,7 @@ i[34567]86-*-mingw* | x86_64-*-mingw*) ;; *) echo "Unsupported CPU used in --with-cpu=$with_cpu, supported values:" 1>&2 - echo "generic atom core2 corei7 Xcorei7-avx nocona x86-64 bdver1 amdfam10 barcelona k8 opteron athlon64 athlon-fx athlon64-sse3 k8-sse3 opteron-sse3" 1>&2 + echo "generic atom core2 corei7 Xcorei7-avx nocona x86-64 bdver1 btver1 amdfam10 barcelona k8 opteron athlon64 athlon-fx athlon64-sse3 k8-sse3 opteron-sse3" 1>&2 exit 1 ;; esac @@ -2797,6 +2797,10 @@ case ${target} in arch=bdver1 cpu=bdver1 ;; + btver1-*) + arch=btver1 + cpu=btver1 + ;; amdfam10-*|barcelona-*) arch=amdfam10 cpu=amdfam10 @@ -2886,6 +2890,10 @@ case ${target} in arch=bdver1 cpu=bdver1 ;; + btver1-*) + arch=btver1 + cpu=btver1 + ;; amdfam10-*|barcelona-*) arch=amdfam10 cpu=amdfam10 @@ -3302,7 +3310,7 @@ case "${target}" in ;; "" | x86-64 | generic | native \ | k8 | k8-sse3 | athlon64 | athlon64-sse3 | opteron \ - | opteron-sse3 | athlon-fx | bdver1 | amdfam10 \ + | opteron-sse3 | athlon-fx | bdver1 | btver1 | amdfam10 \ | barcelona | nocona | core2 | corei7 | corei7-avx | atom) # OK ;; diff --git a/gcc/config/i386/driver-i386.c b/gcc/config/i386/driver-i386.c index 618f875..35962c8 100644 --- a/gcc/config/i386/driver-i386.c +++ b/gcc/config/i386/driver-i386.c @@ -500,6 +500,8 @@ const char *host_detect_local_cpu (int argc, const char **argv) processor = PROCESSOR_GEODE; else if (has_xop) processor = PROCESSOR_BDVER1; + else if (has_sse4a && has_ssse3) + processor = PROCESSOR_BTVER1; else if (has_sse4a) processor = PROCESSOR_AMDFAM10; else if (has_sse2 || has_longmode) @@ -647,6 +649,9 @@ const char *host_detect_local_cpu (int argc, const char **argv) case PROCESSOR_BDVER1: cpu = "bdver1"; break; + case PROCESSOR_BTVER1: + cpu = "btver1"; + break; default: /* Use something reasonable. */ diff --git a/gcc/config/i386/i386-c.c b/gcc/config/i386/i386-c.c index 6adf613..1497351 100644 --- a/gcc/config/i386/i386-c.c +++ b/gcc/config/i386/i386-c.c @@ -110,6 +110,10 @@ ix86_target_macros_internal (int isa_flag, def_or_undef (parse_in, "__bdver1"); def_or_undef (parse_in, "__bdver1__"); break; + case PROCESSOR_BTVER1: + def_or_undef (parse_in, "__btver1"); + def_or_undef (parse_in, "__btver1__"); + break; case PROCESSOR_PENTIUM4: def_or_undef (parse_in, "__pentium4"); def_or_undef (parse_in, "__pentium4__"); @@ -194,6 +198,9 @@ ix86_target_macros_internal (int isa_flag, case PROCESSOR_BDVER1: def_or_undef (parse_in, "__tune_bdver1__"); break; + case PROCESSOR_BTVER1: + def_or_undef (parse_in, "__tune_btver1__"); + break; case PROCESSOR_PENTIUM4: def_or_undef (parse_in, "__tune_pentium4__"); break; diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 50dac35..59a182c 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -1231,6 +1231,88 @@ struct processor_costs bdver1_cost = { 1, /* cond_not_taken_branch_cost. */ }; +struct processor_costs btver1_cost = { + COSTS_N_INSNS (1), /* cost of an add instruction */ + COSTS_N_INSNS (2), /* cost of a lea instruction */ + COSTS_N_INSNS (1), /* variable shift costs */ + COSTS_N_INSNS (1), /* constant shift costs */ + {COSTS_N_INSNS (3), /* cost of starting multiply for QI */ + COSTS_N_INSNS (4), /* HI */ + COSTS_N_INSNS (3), /* SI */ + COSTS_N_INSNS (4), /* DI */ + COSTS_N_INSNS (5)}, /* other */ + 0, /* cost of multiply per each bit set */ + {COSTS_N_INSNS (19), /* cost of a divide/mod for QI */ + COSTS_N_INSNS (35), /* HI */ + COSTS_N_INSNS (51), /* SI */ + COSTS_N_INSNS (83), /* DI */ + COSTS_N_INSNS (83)}, /* other */ + COSTS_N_INSNS (1), /* cost of movsx */ + COSTS_N_INSNS (1), /* cost of movzx */ + 8, /* "large" insn */ + 9, /* MOVE_RATIO */ + 4, /* cost for loading QImode using movzbl */ + {3, 4, 3}, /* cost of loading integer registers + in QImode, HImode and SImode. + Relative to reg-reg move (2). */ + {3, 4, 3}, /* cost of storing integer registers */ + 4, /* cost of reg,reg fld/fst */ + {4, 4, 12}, /* cost of loading fp registers + in SFmode, DFmode and XFmode */ + {6, 6, 8}, /* cost of storing fp registers + in SFmode, DFmode and XFmode */ + 2, /* cost of moving MMX register */ + {3, 3}, /* cost of loading MMX registers + in SImode and DImode */ + {4, 4}, /* cost of storing MMX registers + in SImode and DImode */ + 2, /* cost of moving SSE register */ + {4, 4, 3}, /* cost of loading SSE registers + in SImode, DImode and TImode */ + {4, 4, 5}, /* cost of storing SSE registers + in SImode, DImode and TImode */ + 3, /* MMX or SSE register to integer */ + /* On K8: + MOVD reg64, xmmreg Double FSTORE 4 + MOVD reg32, xmmreg Double FSTORE 4 + On AMDFAM10: + MOVD reg64, xmmreg Double FADD 3 + 1/1 1/1 + MOVD reg32, xmmreg Double FADD 3 + 1/1 1/1 */ + 32, /* size of l1 cache. */ + 512, /* size of l2 cache. */ + 64, /* size of prefetch block */ + 100, /* number of parallel prefetches */ + 2, /* Branch cost */ + COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */ + COSTS_N_INSNS (4), /* cost of FMUL instruction. */ + COSTS_N_INSNS (19), /* cost of FDIV instruction. */ + COSTS_N_INSNS (2), /* cost of FABS instruction. */ + COSTS_N_INSNS (2), /* cost of FCHS instruction. */ + COSTS_N_INSNS (35), /* cost of FSQRT instruction. */ + + /* BTVER1 has optimized REP instruction for medium sized blocks, but for + very small blocks it is better to use loop. For large blocks, libcall can + do nontemporary accesses and beat inline considerably. */ + {{libcall, {{6, loop}, {14, unrolled_loop}, {-1, rep_prefix_4_byte}}}, + {libcall, {{16, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}}, + {{libcall, {{8, loop}, {24, unrolled_loop}, + {2048, rep_prefix_4_byte}, {-1, libcall}}}, + {libcall, {{48, unrolled_loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}}, + 4, /* scalar_stmt_cost. */ + 2, /* scalar load_cost. */ + 2, /* scalar_store_cost. */ + 6, /* vec_stmt_cost. */ + 0, /* vec_to_scalar_cost. */ + 2, /* scalar_to_vec_cost. */ + 2, /* vec_align_load_cost. */ + 2, /* vec_unalign_load_cost. */ + 2, /* vec_store_cost. */ + 2, /* cond_taken_branch_cost. */ + 1, /* cond_not_taken_branch_cost. */ +}; + static const struct processor_costs pentium4_cost = { COSTS_N_INSNS (1), /* cost of an add instruction */ @@ -1624,7 +1706,8 @@ const struct processor_costs *ix86_cost = &pentium_cost; #define m_ATHLON_K8 (m_K8 | m_ATHLON) #define m_AMDFAM10 (1<