[U-Boot,2/7] rockchip: use common sdram function

Message ID	1497346202-774-3-git-send-email-kever.yang@rock-chips.com
State	Superseded
Delegated to:	Philipp Tomsich
Headers	show Return-Path: <u-boot-bounces@lists.denx.de> From: Kever Yang <kever.yang@rock-chips.com> To: sjg@chromium.org Date: Tue, 13 Jun 2017 17:29:57 +0800 Message-Id: <1497346202-774-3-git-send-email-kever.yang@rock-chips.com> In-Reply-To: <1497346202-774-1-git-send-email-kever.yang@rock-chips.com> References: <1497346202-774-1-git-send-email-kever.yang@rock-chips.com> Cc: Stephen Warren <swarren@nvidia.com>, u-boot@lists.denx.de, Jacob Chen <jacob-chen@iotwrt.com>, Klaus Goger <klaus.goger@theobroma-systems.com>, Andy Yan <andy.yan@rock-chips.com> Subject: [U-Boot] [PATCH 2/7] rockchip: use common sdram function Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" <u-boot-bounces@lists.denx.de>

diff --git a/arch/arm/include/asm/arch-rockchip/ddr_rk3288.h b/arch/arm/include/asm/arch-rockchip/ddr_rk3288.h index 9a59075..35696c7 100644 --- a/arch/arm/include/asm/arch-rockchip/ddr_rk3288.h +++ b/arch/arm/include/asm/arch-rockchip/ddr_rk3288.h @@ -441,52 +441,4 @@ enum { /* mr1 for ddr3 */ #define DDR3_DLL_DISABLE 1 -/* - *TODO(sjg@chromium.org): We use a PMU register to store SDRAM information for - * passing from SPL to U-Boot. It would probably be better to use a normal C - * structure in SRAM. - * - * sys_reg bitfield struct - * [31] row_3_4_ch1 - * [30] row_3_4_ch0 - * [29:28] chinfo - * [27] rank_ch1 - * [26:25] col_ch1 - * [24] bk_ch1 - * [23:22] cs0_row_ch1 - * [21:20] cs1_row_ch1 - * [19:18] bw_ch1 - * [17:16] dbw_ch1; - * [15:13] ddrtype - * [12] channelnum - * [11] rank_ch0 - * [10:9] col_ch0 - * [8] bk_ch0 - * [7:6] cs0_row_ch0 - * [5:4] cs1_row_ch0 - * [3:2] bw_ch0 - * [1:0] dbw_ch0 -*/ -#define SYS_REG_DDRTYPE_SHIFT 13 -#define SYS_REG_DDRTYPE_MASK 7 -#define SYS_REG_NUM_CH_SHIFT 12 -#define SYS_REG_NUM_CH_MASK 1 -#define SYS_REG_ROW_3_4_SHIFT(ch) (30 + (ch)) -#define SYS_REG_ROW_3_4_MASK 1 -#define SYS_REG_CHINFO_SHIFT(ch) (28 + (ch)) -#define SYS_REG_RANK_SHIFT(ch) (11 + (ch) * 16) -#define SYS_REG_RANK_MASK 1 -#define SYS_REG_COL_SHIFT(ch) (9 + (ch) * 16) -#define SYS_REG_COL_MASK 3 -#define SYS_REG_BK_SHIFT(ch) (8 + (ch) * 16) -#define SYS_REG_BK_MASK 1 -#define SYS_REG_CS0_ROW_SHIFT(ch) (6 + (ch) * 16) -#define SYS_REG_CS0_ROW_MASK 3 -#define SYS_REG_CS1_ROW_SHIFT(ch) (4 + (ch) * 16) -#define SYS_REG_CS1_ROW_MASK 3 -#define SYS_REG_BW_SHIFT(ch) (2 + (ch) * 16) -#define SYS_REG_BW_MASK 3 -#define SYS_REG_DBW_SHIFT(ch) ((ch) * 16) -#define SYS_REG_DBW_MASK 3 - #endif diff --git a/arch/arm/mach-rockchip/rk3188-board.c b/arch/arm/mach-rockchip/rk3188-board.c index 4be711e..3e76100 100644 --- a/arch/arm/mach-rockchip/rk3188-board.c +++ b/arch/arm/mach-rockchip/rk3188-board.c @@ -72,28 +72,6 @@ err: #endif } -int dram_init(void) -{ - struct ram_info ram; - struct udevice *dev; - int ret; - - ret = uclass_get_device(UCLASS_RAM, 0, &dev); - if (ret) { - debug("DRAM init failed: %d\n", ret); - return ret; - } - ret = ram_get_info(dev, &ram); - if (ret) { - debug("Cannot get DRAM size: %d\n", ret); - return ret; - } - debug("SDRAM base=%lx, size=%x\n", ram.base, ram.size); - gd->ram_size = ram.size; - - return 0; -} - #ifndef CONFIG_SYS_DCACHE_OFF void enable_caches(void) { diff --git a/arch/arm/mach-rockchip/rk3188/sdram_rk3188.c b/arch/arm/mach-rockchip/rk3188/sdram_rk3188.c index 946a9f1..1d2d416 100644 --- a/arch/arm/mach-rockchip/rk3188/sdram_rk3188.c +++ b/arch/arm/mach-rockchip/rk3188/sdram_rk3188.c @@ -22,6 +22,7 @@ #include <asm/arch/grf_rk3188.h> #include <asm/arch/pmu_rk3188.h> #include <asm/arch/sdram.h> +#include <asm/arch/sdram_common.h> #include <linux/err.h> DECLARE_GLOBAL_DATA_PTR; @@ -796,49 +797,7 @@ error: printf("DRAM init failed!\n"); hang(); } -#endif /* CONFIG_SPL_BUILD */ - -size_t sdram_size_mb(struct rk3188_pmu *pmu) -{ - u32 rank, col, bk, cs0_row, cs1_row, bw, row_3_4; - size_t chipsize_mb = 0; - size_t size_mb = 0; - u32 ch; - u32 sys_reg = readl(&pmu->sys_reg[2]); - u32 chans; - - chans = 1 + ((sys_reg >> SYS_REG_NUM_CH_SHIFT) & SYS_REG_NUM_CH_MASK); - - for (ch = 0; ch < chans; ch++) { - rank = 1 + (sys_reg >> SYS_REG_RANK_SHIFT(ch) & - SYS_REG_RANK_MASK); - col = 9 + (sys_reg >> SYS_REG_COL_SHIFT(ch) & SYS_REG_COL_MASK); - bk = 3 - ((sys_reg >> SYS_REG_BK_SHIFT(ch)) & SYS_REG_BK_MASK); - cs0_row = 13 + (sys_reg >> SYS_REG_CS0_ROW_SHIFT(ch) & - SYS_REG_CS0_ROW_MASK); - cs1_row = 13 + (sys_reg >> SYS_REG_CS1_ROW_SHIFT(ch) & - SYS_REG_CS1_ROW_MASK); - bw = (2 >> ((sys_reg >> SYS_REG_BW_SHIFT(ch)) & - SYS_REG_BW_MASK)); - row_3_4 = sys_reg >> SYS_REG_ROW_3_4_SHIFT(ch) & - SYS_REG_ROW_3_4_MASK; - chipsize_mb = (1 << (cs0_row + col + bk + bw - 20)); - - if (rank > 1) - chipsize_mb += chipsize_mb >> - (cs0_row - cs1_row); - if (row_3_4) - chipsize_mb = chipsize_mb * 3 / 4; - size_mb += chipsize_mb; - } - - /* there can be no more than 2gb of memory */ - size_mb = min(size_mb, 0x80000000 >> 20); - - return size_mb; -} -#ifdef CONFIG_SPL_BUILD static int setup_sdram(struct udevice *dev) { struct dram_info *priv = dev_get_priv(dev); @@ -915,12 +874,15 @@ static int rk3188_dmc_probe(struct udevice *dev) { #ifdef CONFIG_SPL_BUILD struct rk3188_sdram_params *plat = dev_get_platdata(dev); -#endif - struct dram_info *priv = dev_get_priv(dev); struct regmap *map; - int ret; struct udevice *dev_clk; + int ret; +#endif + struct dram_info *priv = dev_get_priv(dev); + + priv->pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU); +#ifdef CONFIG_SPL_BUILD #if CONFIG_IS_ENABLED(OF_PLATDATA) ret = conv_of_platdata(dev); if (ret) @@ -932,12 +894,9 @@ static int rk3188_dmc_probe(struct udevice *dev) priv->chan[0].msch = regmap_get_range(map, 0); priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); - priv->pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU); -#ifdef CONFIG_SPL_BUILD priv->chan[0].pctl = regmap_get_range(plat->map, 0); priv->chan[0].publ = regmap_get_range(plat->map, 1); -#endif ret = rockchip_get_clk(&dev_clk); if (ret) @@ -950,13 +909,13 @@ static int rk3188_dmc_probe(struct udevice *dev) priv->cru = rockchip_get_cru(); if (IS_ERR(priv->cru)) return PTR_ERR(priv->cru); -#ifdef CONFIG_SPL_BUILD ret = setup_sdram(dev); if (ret) return ret; -#endif +#else priv->info.base = CONFIG_SYS_SDRAM_BASE; - priv->info.size = sdram_size_mb(priv->pmu) << 20; + priv->info.size = rockchip_sdram_size(&priv->pmu->sys_reg[2]); +#endif return 0; } diff --git a/arch/arm/mach-rockchip/rk3288-board.c b/arch/arm/mach-rockchip/rk3288-board.c index 9894a25..c9d16a9 100644 --- a/arch/arm/mach-rockchip/rk3288-board.c +++ b/arch/arm/mach-rockchip/rk3288-board.c @@ -155,28 +155,6 @@ err: #endif } -int dram_init(void) -{ - struct ram_info ram; - struct udevice *dev; - int ret; - - ret = uclass_get_device(UCLASS_RAM, 0, &dev); - if (ret) { - debug("DRAM init failed: %d\n", ret); - return ret; - } - ret = ram_get_info(dev, &ram); - if (ret) { - debug("Cannot get DRAM size: %d\n", ret); - return ret; - } - debug("SDRAM base=%lx, size=%x\n", ram.base, ram.size); - gd->ram_size = ram.size; - - return 0; -} - #ifndef CONFIG_SYS_DCACHE_OFF void enable_caches(void) { diff --git a/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c b/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c index 2feda61..4a9b5c9 100644 --- a/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c +++ b/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c @@ -22,6 +22,7 @@ #include <asm/arch/grf_rk3288.h> #include <asm/arch/pmu_rk3288.h> #include <asm/arch/sdram.h> +#include <asm/arch/sdram_common.h> #include <linux/err.h> #include <power/regulator.h> #include <power/rk8xx_pmic.h> @@ -923,53 +924,7 @@ error: printf("DRAM init failed!\n"); hang(); } -#endif /* CONFIG_SPL_BUILD */ - -size_t sdram_size_mb(struct rk3288_pmu *pmu) -{ - u32 rank, col, bk, cs0_row, cs1_row, bw, row_3_4; - size_t chipsize_mb = 0; - size_t size_mb = 0; - u32 ch; - u32 sys_reg = readl(&pmu->sys_reg[2]); - u32 chans; - - chans = 1 + ((sys_reg >> SYS_REG_NUM_CH_SHIFT) & SYS_REG_NUM_CH_MASK); - - for (ch = 0; ch < chans; ch++) { - rank = 1 + (sys_reg >> SYS_REG_RANK_SHIFT(ch) & - SYS_REG_RANK_MASK); - col = 9 + (sys_reg >> SYS_REG_COL_SHIFT(ch) & SYS_REG_COL_MASK); - bk = 3 - ((sys_reg >> SYS_REG_BK_SHIFT(ch)) & SYS_REG_BK_MASK); - cs0_row = 13 + (sys_reg >> SYS_REG_CS0_ROW_SHIFT(ch) & - SYS_REG_CS0_ROW_MASK); - cs1_row = 13 + (sys_reg >> SYS_REG_CS1_ROW_SHIFT(ch) & - SYS_REG_CS1_ROW_MASK); - bw = (2 >> ((sys_reg >> SYS_REG_BW_SHIFT(ch)) & - SYS_REG_BW_MASK)); - row_3_4 = sys_reg >> SYS_REG_ROW_3_4_SHIFT(ch) & - SYS_REG_ROW_3_4_MASK; - chipsize_mb = (1 << (cs0_row + col + bk + bw - 20)); - - if (rank > 1) - chipsize_mb += chipsize_mb >> - (cs0_row - cs1_row); - if (row_3_4) - chipsize_mb = chipsize_mb * 3 / 4; - size_mb += chipsize_mb; - } - /* - * we use the 0x00000000~0xfdffffff space since 0xff000000~0xffffffff - * is SoC register space (i.e. reserved), and 0xfe000000~0xfeffffff is - * inaccessible for some IP controller. - */ - size_mb = min(size_mb, 0xfe000000 >> 20); - - return size_mb; -} - -#ifdef CONFIG_SPL_BUILD # ifdef CONFIG_ROCKCHIP_FAST_SPL static int veyron_init(struct dram_info *priv) { @@ -1087,12 +1042,16 @@ static int rk3288_dmc_probe(struct udevice *dev) { #ifdef CONFIG_SPL_BUILD struct rk3288_sdram_params *plat = dev_get_platdata(dev); -#endif - struct dram_info *priv = dev_get_priv(dev); + struct udevice *dev_clk; struct regmap *map; int ret; - struct udevice *dev_clk; +#else + size_t size; +#endif + struct dram_info *priv = dev_get_priv(dev); + priv->pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU); +#ifdef CONFIG_SPL_BUILD #if CONFIG_IS_ENABLED(OF_PLATDATA) ret = conv_of_platdata(dev); if (ret) @@ -1107,14 +1066,12 @@ static int rk3288_dmc_probe(struct udevice *dev) priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); priv->sgrf = syscon_get_first_range(ROCKCHIP_SYSCON_SGRF); - priv->pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU); -#ifdef CONFIG_SPL_BUILD priv->chan[0].pctl = regmap_get_range(plat->map, 0); priv->chan[0].publ = regmap_get_range(plat->map, 1); priv->chan[1].pctl = regmap_get_range(plat->map, 2); priv->chan[1].publ = regmap_get_range(plat->map, 3); -#endif + ret = rockchip_get_clk(&dev_clk); if (ret) return ret; @@ -1126,13 +1083,20 @@ static int rk3288_dmc_probe(struct udevice *dev) priv->cru = rockchip_get_cru(); if (IS_ERR(priv->cru)) return PTR_ERR(priv->cru); -#ifdef CONFIG_SPL_BUILD ret = setup_sdram(dev); if (ret) return ret; +#else + priv->info.base = CONFIG_SYS_SDRAM_BASE; + size = rockchip_sdram_size(priv->pmu->sys_reg[2]); + + /* + * we use the 0x00000000~0xfdffffff space since 0xff000000~0xffffffff + * is SoC register space (i.e. reserved), and 0xfe000000~0xfeffffff is + * inaccessible for some IP controller. + */ + priv->info.size = min(size, 0xfe000000); #endif - priv->info.base = 0; - priv->info.size = sdram_size_mb(priv->pmu) << 20; return 0; } diff --git a/arch/arm/mach-rockchip/rk3399/sdram_rk3399.c b/arch/arm/mach-rockchip/rk3399/sdram_rk3399.c index 1b91bb1..8970bdc 100644 --- a/arch/arm/mach-rockchip/rk3399/sdram_rk3399.c +++ b/arch/arm/mach-rockchip/rk3399/sdram_rk3399.c @@ -15,6 +15,7 @@ #include <syscon.h> #include <asm/io.h> #include <asm/arch/clock.h> +#include <asm/arch/sdram_common.h> #include <asm/arch/sdram_rk3399.h> #include <asm/arch/cru_rk3399.h> #include <asm/arch/grf_rk3399.h> @@ -43,50 +44,6 @@ struct dram_info { struct rk3399_pmugrf_regs *pmugrf; }; -/* - * sys_reg bitfield struct - * [31] row_3_4_ch1 - * [30] row_3_4_ch0 - * [29:28] chinfo - * [27] rank_ch1 - * [26:25] col_ch1 - * [24] bk_ch1 - * [23:22] cs0_row_ch1 - * [21:20] cs1_row_ch1 - * [19:18] bw_ch1 - * [17:16] dbw_ch1; - * [15:13] ddrtype - * [12] channelnum - * [11] rank_ch0 - * [10:9] col_ch0 - * [8] bk_ch0 - * [7:6] cs0_row_ch0 - * [5:4] cs1_row_ch0 - * [3:2] bw_ch0 - * [1:0] dbw_ch0 -*/ -#define SYS_REG_DDRTYPE_SHIFT 13 -#define SYS_REG_DDRTYPE_MASK 7 -#define SYS_REG_NUM_CH_SHIFT 12 -#define SYS_REG_NUM_CH_MASK 1 -#define SYS_REG_ROW_3_4_SHIFT(ch) (30 + (ch)) -#define SYS_REG_ROW_3_4_MASK 1 -#define SYS_REG_CHINFO_SHIFT(ch) (28 + (ch)) -#define SYS_REG_RANK_SHIFT(ch) (11 + (ch) * 16) -#define SYS_REG_RANK_MASK 1 -#define SYS_REG_COL_SHIFT(ch) (9 + (ch) * 16) -#define SYS_REG_COL_MASK 3 -#define SYS_REG_BK_SHIFT(ch) (8 + (ch) * 16) -#define SYS_REG_BK_MASK 1 -#define SYS_REG_CS0_ROW_SHIFT(ch) (6 + (ch) * 16) -#define SYS_REG_CS0_ROW_MASK 3 -#define SYS_REG_CS1_ROW_SHIFT(ch) (4 + (ch) * 16) -#define SYS_REG_CS1_ROW_MASK 3 -#define SYS_REG_BW_SHIFT(ch) (2 + (ch) * 16) -#define SYS_REG_BW_MASK 3 -#define SYS_REG_DBW_SHIFT(ch) ((ch) * 16) -#define SYS_REG_DBW_MASK 3 - #define PRESET_SGRF_HOLD(n) ((0x1 << (6 + 16)) | ((n) << 6)) #define PRESET_GPIO0_HOLD(n) ((0x1 << (7 + 16)) | ((n) << 7)) #define PRESET_GPIO1_HOLD(n) ((0x1 << (8 + 16)) | ((n) << 8)) @@ -1231,50 +1188,6 @@ static int rk3399_dmc_init(struct udevice *dev) } #endif -size_t sdram_size_mb(struct dram_info *dram) -{ - u32 rank, col, bk, cs0_row, cs1_row, bw, row_3_4; - size_t chipsize_mb = 0; - size_t size_mb = 0; - u32 ch; - - u32 sys_reg = readl(&dram->pmugrf->os_reg2); - u32 ch_num = 1 + ((sys_reg >> SYS_REG_NUM_CH_SHIFT) - & SYS_REG_NUM_CH_MASK); - - for (ch = 0; ch < ch_num; ch++) { - rank = 1 + (sys_reg >> SYS_REG_RANK_SHIFT(ch) & - SYS_REG_RANK_MASK); - col = 9 + (sys_reg >> SYS_REG_COL_SHIFT(ch) & SYS_REG_COL_MASK); - bk = 3 - ((sys_reg >> SYS_REG_BK_SHIFT(ch)) & SYS_REG_BK_MASK); - cs0_row = 13 + (sys_reg >> SYS_REG_CS0_ROW_SHIFT(ch) & - SYS_REG_CS0_ROW_MASK); - cs1_row = 13 + (sys_reg >> SYS_REG_CS1_ROW_SHIFT(ch) & - SYS_REG_CS1_ROW_MASK); - bw = (2 >> ((sys_reg >> SYS_REG_BW_SHIFT(ch)) & - SYS_REG_BW_MASK)); - row_3_4 = sys_reg >> SYS_REG_ROW_3_4_SHIFT(ch) & - SYS_REG_ROW_3_4_MASK; - - chipsize_mb = (1 << (cs0_row + col + bk + bw - 20)); - - if (rank > 1) - chipsize_mb += chipsize_mb >> (cs0_row - cs1_row); - if (row_3_4) - chipsize_mb = chipsize_mb * 3 / 4; - size_mb += chipsize_mb; - } - - /* - * we use the 0x00000000~0xf7ffffff space - * since 0xf8000000~0xffffffff is soc register space - * so we reserve it - */ - size_mb = min_t(size_t, size_mb, 0xf8000000/(1<<20)); - - return size_mb; -} - static int rk3399_dmc_probe(struct udevice *dev) { #ifdef CONFIG_SPL_BUILD @@ -1286,7 +1199,13 @@ static int rk3399_dmc_probe(struct udevice *dev) priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF); debug("%s: pmugrf=%p\n", __func__, priv->pmugrf); priv->info.base = 0; - priv->info.size = sdram_size_mb(priv) << 20; + priv->info.size = rockchip_sdram_size(&priv->pmugrf->os_reg2); + /* + * we use the 0x00000000~0xf7ffffff space + * since 0xf8000000~0xffffffff is soc register space + * so we reserve it + */ + priv->info.size = min_t(size_t, priv->info.size, 0xf8000000); #endif return 0; } diff --git a/board/rockchip/evb_rk3328/evb-rk3328.c b/board/rockchip/evb_rk3328/evb-rk3328.c index 0a26ed5..75674bb 100644 --- a/board/rockchip/evb_rk3328/evb-rk3328.c +++ b/board/rockchip/evb_rk3328/evb-rk3328.c @@ -16,12 +16,6 @@ int board_init(void) return 0; } -int dram_init(void) -{ - gd->ram_size = 0x80000000; - return 0; -} - int dram_init_banksize(void) { /* Reserve 0x200000 for ATF bl31 */ diff --git a/board/rockchip/evb_rk3399/evb-rk3399.c b/board/rockchip/evb_rk3399/evb-rk3399.c index f63f003..950bde6 100644 --- a/board/rockchip/evb_rk3399/evb-rk3399.c +++ b/board/rockchip/evb_rk3399/evb-rk3399.c @@ -68,28 +68,6 @@ out: return 0; } -int dram_init(void) -{ - struct ram_info ram; - struct udevice *dev; - int ret; - - ret = uclass_get_device(UCLASS_RAM, 0, &dev); - if (ret) { - debug("DRAM init failed: %d\n", ret); - return ret; - } - ret = ram_get_info(dev, &ram); - if (ret) { - debug("Cannot get DRAM size: %d\n", ret); - return ret; - } - debug("SDRAM base=%llx, size=%x\n", ram.base, (unsigned int)ram.size); - gd->ram_size = ram.size; - - return 0; -} - int dram_init_banksize(void) { /* Reserve 0x200000 for ATF bl31 */ diff --git a/board/rockchip/sheep_rk3368/sheep_rk3368.c b/board/rockchip/sheep_rk3368/sheep_rk3368.c index df1fd9d..e6d2361 100644 --- a/board/rockchip/sheep_rk3368/sheep_rk3368.c +++ b/board/rockchip/sheep_rk3368/sheep_rk3368.c @@ -21,13 +21,6 @@ int board_init(void) return 0; } -int dram_init(void) -{ - gd->ram_size = 0x80000000; - - return 0; -} - int dram_init_banksize(void) { gd->bd->bi_dram[0].start = 0x200000; diff --git a/board/theobroma-systems/puma_rk3399/puma-rk3399.c b/board/theobroma-systems/puma_rk3399/puma-rk3399.c index 6fff3e1..740baf5 100644 --- a/board/theobroma-systems/puma_rk3399/puma-rk3399.c +++ b/board/theobroma-systems/puma_rk3399/puma-rk3399.c @@ -181,28 +181,6 @@ void get_board_serial(struct tag_serialnr *serialnr) } #endif -int dram_init(void) -{ - struct ram_info ram; - struct udevice *dev; - int ret; - - ret = uclass_get_device(UCLASS_RAM, 0, &dev); - if (ret) { - debug("DRAM init failed: %d\n", ret); - return ret; - } - ret = ram_get_info(dev, &ram); - if (ret) { - debug("Cannot get DRAM size: %d\n", ret); - return ret; - } - debug("SDRAM base=%llx, size=%x\n", ram.base, (unsigned int)ram.size); - gd->ram_size = ram.size; - - return 0; -} - int dram_init_banksize(void) { /* Reserve 0x200000 for ATF bl31 */

[U-Boot,2/7] rockchip: use common sdram function

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