From patchwork Tue Jan 4 15:15:49 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aurelien Jarno X-Patchwork-Id: 77498 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id DD64FB70E3 for ; Wed, 5 Jan 2011 02:25:37 +1100 (EST) Received: from localhost ([127.0.0.1]:53231 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Pa8lS-0007d5-G1 for incoming@patchwork.ozlabs.org; Tue, 04 Jan 2011 10:25:34 -0500 Received: from [140.186.70.92] (port=41178 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Pa8cM-0002A0-N1 for qemu-devel@nongnu.org; Tue, 04 Jan 2011 10:16:12 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Pa8cI-0004w9-QW for qemu-devel@nongnu.org; Tue, 04 Jan 2011 10:16:10 -0500 Received: from hall.aurel32.net ([88.191.126.93]:37450) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Pa8cI-0004ur-I3 for qemu-devel@nongnu.org; Tue, 04 Jan 2011 10:16:06 -0500 Received: from [2001:470:d4ed:0:5e26:aff:fe2b:6f5b] (helo=volta.aurel32.net) by hall.aurel32.net with esmtpsa (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.69) (envelope-from ) id 1Pa8cA-0004Nq-H1; Tue, 04 Jan 2011 16:15:58 +0100 Received: from aurel32 by volta.aurel32.net with local (Exim 4.72) (envelope-from ) id 1Pa8c8-0002G5-Dd; Tue, 04 Jan 2011 16:15:56 +0100 From: Aurelien Jarno To: qemu-devel@nongnu.org Date: Tue, 4 Jan 2011 16:15:49 +0100 Message-Id: <1294154150-7528-8-git-send-email-aurelien@aurel32.net> X-Mailer: git-send-email 1.7.2.3 In-Reply-To: <1294154150-7528-1-git-send-email-aurelien@aurel32.net> References: <1294154150-7528-1-git-send-email-aurelien@aurel32.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 3) Cc: Aurelien Jarno Subject: [Qemu-devel] [PATCH v2 7/8] target-mips: Implement correct NaN propagation rules X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Implement the correct NaN propagation rules for MIPS targets by providing an appropriate pickNaN function. Signed-off-by: Aurelien Jarno --- fpu/softfloat-specialize.h | 27 +++++++++++++++++++++++++++ 1 files changed, 27 insertions(+), 0 deletions(-) diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h index 060e3fd..1d4eab8 100644 --- a/fpu/softfloat-specialize.h +++ b/fpu/softfloat-specialize.h @@ -192,6 +192,33 @@ static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN, return 1; } } +#elif defined(TARGET_MIPS) +static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN, + flag aIsLargerSignificand) +{ + /* According to MIPS specifications, if one of the two operands is + * a sNaN, a new qNaN has to be generated. This is done in + * floatXX_maybe_silence_nan(). For qNaN inputs the specifications + * says: "When possible, this QNaN result is one of the operand QNaN + * values." In practice it seems that most implementations choose + * the first operand if both operands are qNaN. In short this gives + * the following rules: + * 1. A if it is signaling + * 2. B if it is signaling + * 3. A (quiet) + * 4. B (quiet) + * A signaling NaN is always quietened before returning it. + */ + if (aIsSNaN) { + return 0; + } else if (bIsSNaN) { + return 1; + } else if (aIsQNaN) { + return 0; + } else { + return 1; + } +} #else static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN, flag aIsLargerSignificand)