Patchwork [U-Boot,v2] mpq101: initial support for Mercury Computer Systems MPQ101 board

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Submitter Alex Dubov
Date Jan. 4, 2011, 4:49 a.m.
Message ID <894149.81831.qm@web37607.mail.mud.yahoo.com>
Download mbox | patch
Permalink /patch/77376/
State Superseded
Headers show

Comments

Alex Dubov - Jan. 4, 2011, 4:49 a.m.
Mpq101 is a RapidIO development board in AMC form factor, featuring MPC8548
processor, 512MB of hardwired DDR2 RAM and 128MB of hardwired NAND flash
memory. USB controller is available, but not presently enabled.

Additional board information is available at:
http://www.mc.com/products/boards/ensemble_mpq101_rapidio_powerquicc_iii.aspx

Environment is configured to precede the actual u-boot image so that it's
located at the beginning of flash erase block (made necessary by the recent
changes to the embedded environment handling).

Signed-off-by: Alex Dubov <oakad@yahoo.com>
---
 MAINTAINERS                    |    3 +
 board/mercury/mpq101/Makefile  |   53 ++++++
 board/mercury/mpq101/config.mk |    7 +
 board/mercury/mpq101/law.c     |   55 ++++++
 board/mercury/mpq101/mpq101.c  |  146 +++++++++++++++
 board/mercury/mpq101/tlb.c     |   82 +++++++++
 boards.cfg                     |    1 +
 include/configs/mpq101.h       |  392 ++++++++++++++++++++++++++++++++++++++++
 8 files changed, 739 insertions(+), 0 deletions(-)
 create mode 100644 board/mercury/mpq101/Makefile
 create mode 100644 board/mercury/mpq101/config.mk
 create mode 100644 board/mercury/mpq101/law.c
 create mode 100644 board/mercury/mpq101/mpq101.c
 create mode 100644 board/mercury/mpq101/tlb.c
 create mode 100644 include/configs/mpq101.h

Patch

diff --git a/MAINTAINERS b/MAINTAINERS
index 9258cb1..e31fc5e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -138,6 +138,9 @@  Jon Diekema <jon.diekema@smiths-aerospace.com>
 
 	sbc8260		MPC8260
 
+Alex Dubov <oakad@yahoo.com>
+	mpq101		MPC8548
+
 Dirk Eibach <eibach@gdsys.de>
 
 	devconcenter	PPC460EX
diff --git a/board/mercury/mpq101/Makefile b/board/mercury/mpq101/Makefile
new file mode 100644
index 0000000..58bc1b3
--- /dev/null
+++ b/board/mercury/mpq101/Makefile
@@ -0,0 +1,53 @@ 
+#
+# Copyright 2007 Freescale Semiconductor, Inc.
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	+= $(BOARD).o
+COBJS-y	+= law.o
+COBJS-y	+= tlb.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(OBJS) $(SOBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/mercury/mpq101/config.mk b/board/mercury/mpq101/config.mk
new file mode 100644
index 0000000..1870680
--- /dev/null
+++ b/board/mercury/mpq101/config.mk
@@ -0,0 +1,7 @@ 
+#
+# mpq101 board
+#
+
+# Make room for environment at the beginning of flash sector
+CONFIG_SYS_TEXT_BASE = 0xfffc0800
+LDFLAGS += --section-start=.ppcenv=$(CONFIG_ENV_ADDR)
diff --git a/board/mercury/mpq101/law.c b/board/mercury/mpq101/law.c
new file mode 100644
index 0000000..726b5c2
--- /dev/null
+++ b/board/mercury/mpq101/law.c
@@ -0,0 +1,55 @@ 
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+/*
+ * LAW(Local Access Window) configuration:
+ *
+ * 0x0000_0000     0x1fff_ffff     DDR                     SYS_SDRAM_SIZE
+ * 0xc000_0000     0xdfff_ffff     RapidIO                 512M
+ * 0xe000_0000     0xe000_ffff     CCSR                    1M
+ * 0xf000_0000     0xffff_ffff     LBC options + FLASH     256M
+ *
+ * Notes:
+ *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ *    If flash is 8M at default position (last 8M), no LAW needed.
+ *
+ * LAW 0 is reserved for boot mapping
+ */
+
+struct law_entry law_table[] = {
+	SET_LAW(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_SIZE_LOG - 1,
+		LAW_TRGT_IF_DDR_1),
+#ifdef CONFIG_SYS_RIO_MEM_PHYS
+	SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
+#endif
+	SET_LAW(CONFIG_SYS_LBC_OPTION_BASE_PHYS, LAW_SIZE_256M,
+		LAW_TRGT_IF_LBC)
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/mercury/mpq101/mpq101.c b/board/mercury/mpq101/mpq101.c
new file mode 100644
index 0000000..8399ebe
--- /dev/null
+++ b/board/mercury/mpq101/mpq101.c
@@ -0,0 +1,146 @@ 
+/*
+ * (C) Copyright 2010 Alex Dubov <oakad@yahoo.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <asm/io.h>
+#include <miiphy.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+
+void local_bus_init(void);
+void sdram_init(void);
+
+unsigned long get_clock_freq(void)
+{
+	return 33000000;
+}
+
+int checkboard (void)
+{
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
+
+	puts ("Board: Mercury Computer Systems, Inc. MPQ-101 ");
+#ifdef CONFIG_PHYS_64BIT
+	puts ("(36-bit addrmap) ");
+#endif
+	putc ('\n');
+
+	/*
+	 * Initialize local bus.
+	 */
+	local_bus_init ();
+
+	/*
+	 * Hack TSEC 3 and 4 IO voltages.
+	 */
+	out_be32(&gur->tsec34ioovcr, 0xe7e0); /*  1110 0111 1110 0xxx */
+
+	out_be32(&ecm->eedr, 0xffffffff); /* clear ecm errors */
+	out_be32(&ecm->eeer, 0xffffffff); /* enable ecm errors */
+	return 0;
+}
+
+phys_size_t
+initdram (int board_type)
+{
+	volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
+	phys_size_t dram_size = 0;
+	const char *p_mode = getenv("perf_mode");
+
+	puts("Initializing....");
+
+	ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
+	ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
+
+	ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
+	ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
+
+	if (p_mode && !strcmp("performance", p_mode)) {
+		ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_PERF;
+		ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_PERF;
+		ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1_PERF;
+		ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_PERF;
+		ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL_PERF;
+	} else {
+		ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+		ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+		ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
+		ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
+		ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
+	}
+
+	ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
+	ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
+
+	asm("sync;isync");
+	udelay(500);
+
+	ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
+	asm("sync; isync");
+	udelay(500);
+
+	dram_size = setup_ddr_tlbs(1ull << (CONFIG_SYS_SDRAM_SIZE_LOG - 20));
+
+	puts("    DDR: ");
+
+	return dram_size << 20;
+}
+
+/*
+ * Initialize Local Bus
+ */
+void
+local_bus_init(void)
+{
+	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
+
+	out_be32(&lbc->ltesr, 0xffffffff); /* Clear LBC error interrupts */
+	out_be32(&lbc->lteir, 0xffffffff); /* Enable LBC error interrupts */
+}
+
+void
+pci_init_board(void)
+{
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+
+	/* PCI is disabled */
+	out_be32(&gur->devdisr, in_be32(&gur->devdisr)
+				| MPC85xx_DEVDISR_PCI1
+				| MPC85xx_DEVDISR_PCI2
+				| MPC85xx_DEVDISR_PCIE);
+}
+
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+
+void
+ft_board_setup(void *blob, bd_t *bd)
+{
+        ft_cpu_setup(blob, bd);
+}
+
+#endif
diff --git a/board/mercury/mpq101/tlb.c b/board/mercury/mpq101/tlb.c
new file mode 100644
index 0000000..3e3d280
--- /dev/null
+++ b/board/mercury/mpq101/tlb.c
@@ -0,0 +1,82 @@ 
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+	/* TLB 0 - for temp stack in cache */
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+
+	/*
+	 * TLB 0:	256M	Non-cacheable, guarded
+	 * 0xf0000000	256M	LBC (FLASH included)
+	 * Out of reset this entry is only 4K.
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_LBC_OPTION_BASE,
+		      CONFIG_SYS_LBC_OPTION_BASE_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 0, BOOKE_PAGESZ_256M, 1),
+
+	/*
+	 * TLB 1:	1M	Non-cacheable, guarded
+	 * 0xe000_0000	1M	CCSRBAR
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 1, BOOKE_PAGESZ_1M, 1),
+
+#ifdef CONFIG_SYS_RIO_MEM_PHYS
+	/*
+	 * TLB 2:       256M    Non-cacheable, guarded
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE, CONFIG_SYS_RIO_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 2, BOOKE_PAGESZ_256M, 1),
+
+	/*
+	 * TLB 3:       256M    Non-cacheable, guarded
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE + 0x10000000,
+		      CONFIG_SYS_RIO_MEM_PHYS + 0x10000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 3, BOOKE_PAGESZ_256M, 1),
+
+#endif
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/boards.cfg b/boards.cfg
index 08e531e..a0baa4f 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -189,6 +189,7 @@  TQM834x		powerpc	mpc83xx		tqm834x		tqc
 sbc8349		powerpc	mpc83xx		sbc8349		-		-	sbc8349
 caddy2		powerpc	mpc83xx		vme8349		esd		-	vme8349:CADDY2
 vme8349		powerpc	mpc83xx		vme8349		esd		-	vme8349
+mpq101		powerpc	mpc85xx		mpq101		mercury		-	mpq101
 PM854		powerpc	mpc85xx		pm854
 PM856		powerpc	mpc85xx		pm856
 P1022DS		powerpc	mpc85xx		p1022ds		freescale
diff --git a/include/configs/mpq101.h b/include/configs/mpq101.h
new file mode 100644
index 0000000..dd8edd9
--- /dev/null
+++ b/include/configs/mpq101.h
@@ -0,0 +1,392 @@ 
+/*
+ * Copyright 2010 Alex Dubov <oakad@yahoo.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Merury Computers MPQ101 board configuration file
+ *
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#ifdef CONFIG_36BIT
+#define CONFIG_PHYS_64BIT
+#endif
+
+//#define DEBUG         5
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE      1 /* BOOKE */
+#define CONFIG_E500       1 /* BOOKE e500 family */
+#define CONFIG_MPC85xx    1 /* MPC8540/60/55/41/48 */
+#define CONFIG_MPC8548    1 /* MPC8548 specific */
+#define CONFIG_MPQ101     1 /* MPQ101 board specific */
+
+#define CONFIG_RIO
+
+#define CONFIG_TSEC_ENET      1 /* tsec ethernet support */
+#define CONFIG_ENV_OVERWRITE  1
+#define CONFIG_INTERRUPTS     1 /* enable pci, srio, ddr interrupts */
+#define CONFIG_FSL_LAW        1 /* Use common FSL init code */
+
+/*
+ * When initializing flash, if we cannot find the manufacturer ID,
+ * assume this is the AMD flash.
+ */
+#define CONFIG_ASSUME_AMD_FLASH
+
+#ifndef __ASSEMBLY__
+extern unsigned long get_clock_freq(void);
+#endif
+#define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE 1 /* toggle L2 cache */
+#define CONFIG_BTB      1 /* toggle branch predition */
+
+/*
+ * Only possible on E500 Version 2 or newer cores.
+ */
+#define CONFIG_ENABLE_36BIT_PHYS 1
+
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_ADDR_MAP         1
+#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
+#endif
+
+
+#define CONFIG_SYS_ALT_MEMTEST   1
+#define CONFIG_SYS_MEMTEST_START 0x0ff00000 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END   0x0ffffffc
+
+#define CONFIG_PANIC_HANG
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
+#define CONFIG_SYS_CCSRBAR         0xe0000000
+#ifdef CONFIG_PHYS_64BIT
+#define
+#define CONFIG_SYS_CCSRBAR_PHYS    0xfe0000000ull
+#else
+#define CONFIG_SYS_CCSRBAR_PHYS    CONFIG_SYS_CCSRBAR
+#endif
+#define CONFIG_SYS_IMMR            CONFIG_SYS_CCSRBAR
+
+/* DDR Setup */
+#define CONFIG_FSL_DDR2
+#undef CONFIG_SPD_EEPROM
+#undef CONFIG_DDR_SPD
+#undef CONFIG_DDR_DLL
+
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 1  /* DDR controller or DMA? */
+
+#define CONFIG_MEM_INIT_VALUE     0xDeadBeef
+#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
+#define CONFIG_SYS_SDRAM_BASE     CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_NUM_DDR_CONTROLLERS   1
+#define CONFIG_DIMM_SLOTS_PER_CTLR   1
+#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
+
+/* Fixed 512MB DDR2 parameters */
+#define CONFIG_SYS_SDRAM_SIZE_LOG       29 /* DDR is 512MB */
+#define CONFIG_SYS_DDR_CS0_BNDS         0x0000001f
+#define CONFIG_SYS_DDR_CS0_CONFIG       0x80014102
+#define CONFIG_SYS_DDR_TIMING_3         0x00010000
+#define CONFIG_SYS_DDR_TIMING_0         0x00260802
+#define CONFIG_SYS_DDR_TIMING_1         0x5c47a432
+#define CONFIG_SYS_DDR_TIMING_1_PERF    0x49352322
+#define CONFIG_SYS_DDR_TIMING_2         0x03984cce
+#define CONFIG_SYS_DDR_TIMING_2_PERF    0x14904cca
+#define CONFIG_SYS_DDR_MODE_1           0x00400442
+#define CONFIG_SYS_DDR_MODE_1_PERF      0x00480432
+#define CONFIG_SYS_DDR_MODE_2           0x00000000
+#define CONFIG_SYS_DDR_MODE_2_PERF      0x00000000
+#define CONFIG_SYS_DDR_INTERVAL         0x08200100
+#define CONFIG_SYS_DDR_INTERVAL_PERF    0x06180100
+#define CONFIG_SYS_DDR_CLK_CTRL         0x03800000
+#define CONFIG_SYS_DDR_CONTROL          0xc3008000 /* Type = DDR2 */
+#define CONFIG_SYS_DDR_CONTROL2         0x04400000
+
+#undef CONFIG_CLOCKS_IN_MHZ
+
+/*
+ * Local Bus Definitions
+ */
+
+/*
+ * FLASH on the Local Bus
+ * One bank, 128M, using the CFI driver.
+ */
+
+#define CONFIG_SYS_BOOT_BLOCK 0xf8000000            /* boot TLB block */
+#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_BOOT_BLOCK /* start of FLASH 128M */
+
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_FLASH_BASE_PHYS      0xff8000000ull
+#else
+#define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
+#endif
+
+/* 0xf8001801 */
+#define CONFIG_SYS_BR0_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
+				| BR_PS_32 | BR_V)
+
+/* 0xf8006ff7 */
+#define CONFIG_SYS_OR0_PRELIM  (MEG_TO_AM(128) | OR_GPCM_XAM | OR_GPCM_CSNT \
+				| OR_GPCM_ACS_DIV2 | OR_GPCM_XACS \
+				| OR_GPCM_SCY_15 | OR_GPCM_TRLX \
+				| OR_GPCM_EHTR | OR_GPCM_EAD)
+
+#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
+#undef CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS 45   /* count down from 45/5: 9..1 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS 1    /* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT  512  /* sectors per device */
+#undef  CONFIG_SYS_FLASH_CHECKSUM
+
+//#define CONFIG_SYS_BR0_PRELIM 0xff001801
+//#define CONFIG_SYS_BR1_PRELIM 0xf0001001
+
+//#define CONFIG_SYS_OR0_PRELIM 0xff006e65
+//#define CONFIG_SYS_OR1_PRELIM 0xff006e65
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT 500   /* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
+
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
+
+/*
+ * 16b peripherals on the Local Bus
+ * 64k
+ */
+#define CONFIG_SYS_LBC_OPTION_BASE   0xf0000000
+
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_LBC_OPTION_BASE_PHYS      0xff0000000ull
+#else
+#define CONFIG_SYS_LBC_OPTION_BASE_PHYS      CONFIG_SYS_LBC_OPTION_BASE
+#endif
+
+
+/* 0xf0001001 */
+#define CONFIG_SYS_BR1_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_LBC_OPTION_BASE_PHYS) \
+				| BR_PS_16 | BR_V)
+
+/* ffff7002 */
+#define CONFIG_SYS_OR1_PRELIM  (P2SZ_TO_AM(0x10000) | OR_GPCM_XAM \
+				| OR_GPCM_BCTLD | OR_GPCM_EHTR)
+
+#define CONFIG_SYS_LBC_LCRR          0x00000004 /* LB clock ratio reg */
+#define CONFIG_SYS_LBC_LBCR          0x00000000 /* LB config reg */
+
+#define CONFIG_SYS_INIT_RAM_LOCK     1
+#define CONFIG_SYS_INIT_RAM_ADDR     0xe4010000 /* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_SIZE     0x4000     /* Size of used area in RAM */
+
+#define CONFIG_SYS_GBL_DATA_OFFSET   (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET    CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN       (256 * 1024)  /* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN        (1024 * 1024) /* Reserved for malloc */
+
+/* Serial Port */
+#define CONFIG_CONS_INDEX           2
+#undef  CONFIG_SERIAL_SOFTWARE_FIFO
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE 1
+#define CONFIG_SYS_NS16550_CLK      get_bus_freq(0)
+
+#define CONFIG_SYS_BAUDRATE_TABLE \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+
+#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+#ifdef  CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#endif
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT           1
+#define CONFIG_OF_BOARD_SETUP      1
+#define CONFIG_OF_STDOUT_VIA_ALIAS 1
+
+/* new uImage format support */
+#define CONFIG_FIT              1
+#define CONFIG_FIT_VERBOSE      1 /* enable fit_format_{error,warning}() */
+
+//#define CONFIG_SYS_64BIT_VSPRINTF 1
+//#define CONFIG_SYS_64BIT_STRTOUL  1
+
+/*
+ * I2C
+ */
+#define CONFIG_FSL_I2C                 /* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C                /* I2C with hardware support*/
+#undef  CONFIG_SOFT_I2C                /* I2C bit-banged */
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_SYS_I2C_SPEED    400000 /* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE    0x7f
+#define CONFIG_SYS_I2C_OFFSET   0x3000
+#define CONFIG_SYS_I2C2_OFFSET  0x3100
+
+#ifdef CONFIG_RIO
+/*
+ * RapidIO MMU
+ */
+#define CONFIG_SYS_RIO_MEM_BASE 0xc0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_RIO_MEM_PHYS 0xfc0000000ull
+#else
+#define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BASE
+#endif
+#define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 512M */
+#endif
+
+#if defined(CONFIG_TSEC_ENET)
+
+#ifndef CONFIG_NET_MULTI
+#define CONFIG_NET_MULTI  1
+#endif
+
+#define CONFIG_MII        1       /* MII PHY management */
+#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
+#define CONFIG_TSEC1      1
+#define CONFIG_TSEC1_NAME "eTSEC0"
+#define CONFIG_TSEC2      1
+#define CONFIG_TSEC2_NAME "eTSEC1"
+#define CONFIG_TSEC3      1
+#define CONFIG_TSEC3_NAME "eTSEC2"
+#define CONFIG_TSEC4      1
+#define CONFIG_TSEC4_NAME "eTSEC3"
+#undef CONFIG_MPC85XX_FEC
+
+#define TSEC1_PHY_ADDR    0x10
+#define TSEC2_PHY_ADDR    0x11
+#define TSEC3_PHY_ADDR    0x12
+#define TSEC4_PHY_ADDR    0x13
+
+#define TSEC1_PHYIDX      0
+#define TSEC2_PHYIDX      0
+#define TSEC3_PHYIDX      0
+#define TSEC4_PHYIDX      0
+
+#define TSEC1_FLAGS       (TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC2_FLAGS       (TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC3_FLAGS       (TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC4_FLAGS       (TSEC_GIGABIT | TSEC_REDUCED)
+
+/* Options are: eTSEC[0-3] */
+#define CONFIG_ETHPRIME   "eTSEC0"
+#define CONFIG_PHY_GIGE   1 /* Include GbE speed/duplex detection */
+#endif /* CONFIG_TSEC_ENET */
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_IS_IN_FLASH 1
+#define CONFIG_SYS_USE_PPCENV  1
+#define ENV_IS_EMBEDDED        1
+#define CONFIG_ENV_SECT_SIZE   0x40000   /* 256K */
+#define CONFIG_ENV_SIZE        0x800
+#define CONFIG_ENV_ADDR        0xfffc0000
+
+#define CONFIG_LOADS_ECHO             1 /* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE  1 /* allow baudrate change */
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#undef  CONFIG_CMD_FPGA
+#undef  CONFIG_CMD_NFS
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_JFFS2
+
+#undef CONFIG_WATCHDOG /* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP                    /* undef to save memory */
+#define CONFIG_CMDLINE_EDITING                 /* Command-line editing */
+#define CONFIG_AUTO_COMPLETE                   /* add autocompletion support */
+#define CONFIG_SYS_LOAD_ADDR   0x2000000       /* default load address */
+#define CONFIG_SYS_PROMPT      "MPQ-101=> "    /* Monitor Command Prompt */
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE 1024                 /* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE 256                  /* Console I/O Buffer Size */
+#endif
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16)
+
+#define CONFIG_SYS_MAXARGS  16                /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+#define CONFIG_SYS_HZ       1000              /* decrementer freq: 1ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 16 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE  230400 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2      /* which serial port to use */
+#endif
+
+/*
+ * Environment Configuration
+ */
+
+#define CONFIG_BAUDRATE  115200
+
+#define CONFIG_LOADADDR  CONFIG_SYS_LOAD_ADDR /*default location for tftp and bootm*/
+
+#define CONFIG_BOOTDELAY 10      /* -1 disables auto-boot */
+#undef  CONFIG_BOOTARGS          /* the boot command will set bootargs*/
+
+#endif /* __CONFIG_H */