From patchwork Mon Jan 3 19:46:40 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Graeme Russ X-Patchwork-Id: 77326 X-Patchwork-Delegate: graeme.russ@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 58422B6EDF for ; Tue, 4 Jan 2011 06:51:02 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id C109E2829F; Mon, 3 Jan 2011 20:49:25 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id rxkfwpsUIxWg; Mon, 3 Jan 2011 20:49:25 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 263B128338; Mon, 3 Jan 2011 20:48:53 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 1483828356 for ; Mon, 3 Jan 2011 20:48:51 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id yU-as8cWnexm for ; Mon, 3 Jan 2011 20:48:49 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-fx0-f44.google.com (mail-fx0-f44.google.com [209.85.161.44]) by theia.denx.de (Postfix) with ESMTP id 7CB30282B7 for ; Mon, 3 Jan 2011 20:48:28 +0100 (CET) Received: by mail-fx0-f44.google.com with SMTP id 9so12889169fxm.3 for ; Mon, 03 Jan 2011 11:48:28 -0800 (PST) Received: by 10.103.221.15 with SMTP id y15mr1697653muq.100.1294084108126; Mon, 03 Jan 2011 11:48:28 -0800 (PST) Received: from helios.localdomain6 (d122-104-38-246.sbr6.nsw.optusnet.com.au [122.104.38.246]) by mx.google.com with ESMTPS id a6sm3124092fak.1.2011.01.03.11.48.24 (version=SSLv3 cipher=RC4-MD5); Mon, 03 Jan 2011 11:48:27 -0800 (PST) From: Graeme Russ To: u-boot@lists.denx.de Date: Tue, 4 Jan 2011 06:46:40 +1100 Message-Id: <1294084016-2674-21-git-send-email-graeme.russ@gmail.com> X-Mailer: git-send-email 1.7.1.422.g049e9 In-Reply-To: <1294084016-2674-1-git-send-email-graeme.russ@gmail.com> References: <1294084016-2674-1-git-send-email-graeme.russ@gmail.com> Subject: [U-Boot] [RFC][PATCH 20/36] eNET - Define MMCR values in config.h X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.9 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de --- board/eNET/eNET.c | 6 +++--- include/configs/eNET.h | 36 ++++++++++++++++++++++++++++++++++++ 2 files changed, 39 insertions(+), 3 deletions(-) --- 1.7.1.422.g049e9 diff --git a/board/eNET/eNET.c b/board/eNET/eNET.c index 3b74ce9..fa10c6e 100644 --- a/board/eNET/eNET.c +++ b/board/eNET/eNET.c @@ -90,9 +90,9 @@ int board_early_init_f(void) writew(0x0000, &sc520_mmcr->wdtmrctl); /* Chip Select Configuration */ - writew(0x0033, &sc520_mmcr->bootcsctl); - writew(0x0615, &sc520_mmcr->romcs1ctl); - writew(0x0615, &sc520_mmcr->romcs2ctl); + writew(CONFIG_SYS_SC520_BOOTCS_CTRL, &sc520_mmcr->bootcsctl); + writew(CONFIG_SYS_SC520_ROMCS1_CTRL, &sc520_mmcr->romcs1ctl); + writew(CONFIG_SYS_SC520_ROMCS2_CTRL, &sc520_mmcr->romcs2ctl); /* * Set the timer pin mapping diff --git a/include/configs/eNET.h b/include/configs/eNET.h index 082f681..4e96a3a 100644 --- a/include/configs/eNET.h +++ b/include/configs/eNET.h @@ -247,6 +247,42 @@ #define CONFIG_SYS_FPGA_MAX_FINALISE_TIME 10 /* milliseconds */ #define CONFIG_SYS_FPGA_SSI_DATA_RATE 8333 /* kHz (33.3333MHz xtal) */ +/* + * BOOTCS Control (for AM29LV040B-120JC) + * + * 000 0 00 0 000 11 0 011 }- 0x0033 + * \ / | \| | \ / \| | \ / + * | | | | | | | | + * | | | | | | | +---- 3 Wait States (First Access) + * | | | | | | +------- Reserved + * | | | | | +--------- 3 Wait States (Subsequent Access) + * | | | | +------------- Reserved + * | | | +---------------- Non-Paged Mode + * | | +------------------ 8 Bit Wide + * | +--------------------- GP Bus + * +------------------------ Reserved + */ +#define CONFIG_SYS_SC520_BOOTCS_CTRL 0x0033 + +/* + * BOOTCS Control (for E28F128J3A-150 StrataFlash) + * + * 000 0 01 1 000 01 0 101 }- 0x0615 + * \ / | \| | \ / \| | \ / + * | | | | | | | | + * | | | | | | | +---- 5 Wait States (First Access) + * | | | | | | +------- Reserved + * | | | | | +--------- 1 Wait State (Subsequent Access) + * | | | | +------------- Reserved + * | | | +---------------- Paged Mode + * | | +------------------ 16 Bit Wide + * | +--------------------- GP Bus + * +------------------------ Reserved + */ +#define CONFIG_SYS_SC520_ROMCS1_CTRL 0x0615 +#define CONFIG_SYS_SC520_ROMCS2_CTRL 0x0615 + + #ifndef __ASSEMBLER__ extern unsigned long ip;