Patchwork [U-Boot,RFC,20/36] eNET - Define MMCR values in config.h

login
register
mail settings
Submitter Graeme Russ
Date Jan. 3, 2011, 7:46 p.m.
Message ID <1294084016-2674-21-git-send-email-graeme.russ@gmail.com>
Download mbox | patch
Permalink /patch/77326/
State Superseded
Delegated to: Graeme Russ
Headers show

Comments

Graeme Russ - Jan. 3, 2011, 7:46 p.m.
---
 board/eNET/eNET.c      |    6 +++---
 include/configs/eNET.h |   36 ++++++++++++++++++++++++++++++++++++
 2 files changed, 39 insertions(+), 3 deletions(-)

--
1.7.1.422.g049e9

Patch

diff --git a/board/eNET/eNET.c b/board/eNET/eNET.c
index 3b74ce9..fa10c6e 100644
--- a/board/eNET/eNET.c
+++ b/board/eNET/eNET.c
@@ -90,9 +90,9 @@  int board_early_init_f(void)
 	writew(0x0000, &sc520_mmcr->wdtmrctl);

 	/* Chip Select Configuration */
-	writew(0x0033, &sc520_mmcr->bootcsctl);
-	writew(0x0615, &sc520_mmcr->romcs1ctl);
-	writew(0x0615, &sc520_mmcr->romcs2ctl);
+	writew(CONFIG_SYS_SC520_BOOTCS_CTRL, &sc520_mmcr->bootcsctl);
+	writew(CONFIG_SYS_SC520_ROMCS1_CTRL, &sc520_mmcr->romcs1ctl);
+	writew(CONFIG_SYS_SC520_ROMCS2_CTRL, &sc520_mmcr->romcs2ctl);

 	/*
 	 * Set the timer pin mapping
diff --git a/include/configs/eNET.h b/include/configs/eNET.h
index 082f681..4e96a3a 100644
--- a/include/configs/eNET.h
+++ b/include/configs/eNET.h
@@ -247,6 +247,42 @@ 
 #define CONFIG_SYS_FPGA_MAX_FINALISE_TIME	10	/* milliseconds */
 #define CONFIG_SYS_FPGA_SSI_DATA_RATE		8333	/* kHz (33.3333MHz xtal) */

+/*
+ * BOOTCS Control (for AM29LV040B-120JC)
+ *
+ * 000 0 00 0 000 11 0 011 }- 0x0033
+ * \ / | \| | \ / \| | \ /
+ *  |  |  | |  |   | |  |
+ *  |  |  | |  |   | |  +---- 3 Wait States (First Access)
+ *  |  |  | |  |   | +------- Reserved
+ *  |  |  | |  |   +--------- 3 Wait States (Subsequent Access)
+ *  |  |  | |  +------------- Reserved
+ *  |  |  | +---------------- Non-Paged Mode
+ *  |  |  +------------------ 8 Bit Wide
+ *  |  +--------------------- GP Bus
+ *  +------------------------ Reserved
+ */
+#define CONFIG_SYS_SC520_BOOTCS_CTRL		0x0033
+
+/*
+ * BOOTCS Control (for E28F128J3A-150 StrataFlash)
+ *
+ * 000 0 01 1 000 01 0 101 }- 0x0615
+ * \ / | \| | \ / \| | \ /
+ *  |  |  | |  |   | |  |
+ *  |  |  | |  |   | |  +---- 5 Wait States (First Access)
+ *  |  |  | |  |   | +------- Reserved
+ *  |  |  | |  |   +--------- 1 Wait State (Subsequent Access)
+ *  |  |  | |  +------------- Reserved
+ *  |  |  | +---------------- Paged Mode
+ *  |  |  +------------------ 16 Bit Wide
+ *  |  +--------------------- GP Bus
+ *  +------------------------ Reserved
+ */
+#define CONFIG_SYS_SC520_ROMCS1_CTRL		0x0615
+#define CONFIG_SYS_SC520_ROMCS2_CTRL		0x0615
+
+
 #ifndef __ASSEMBLER__
 extern unsigned long ip;