From patchwork Mon Jan 3 19:46:31 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Graeme Russ X-Patchwork-Id: 77318 X-Patchwork-Delegate: graeme.russ@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 90A78B70A9 for ; Tue, 4 Jan 2011 06:49:30 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 989C828190; Mon, 3 Jan 2011 20:48:31 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id LTHBr9F9dS2k; Mon, 3 Jan 2011 20:48:31 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id EB4D7282DD; Mon, 3 Jan 2011 20:48:10 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id BCF102826A for ; Mon, 3 Jan 2011 20:48:08 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id fIVo9S7cA9Tu for ; Mon, 3 Jan 2011 20:48:08 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-fx0-f44.google.com (mail-fx0-f44.google.com [209.85.161.44]) by theia.denx.de (Postfix) with ESMTP id B79C62823E for ; Mon, 3 Jan 2011 20:47:53 +0100 (CET) Received: by mail-fx0-f44.google.com with SMTP id 9so12889169fxm.3 for ; Mon, 03 Jan 2011 11:47:53 -0800 (PST) Received: by 10.223.72.202 with SMTP id n10mr7428271faj.74.1294084072989; Mon, 03 Jan 2011 11:47:52 -0800 (PST) Received: from helios.localdomain6 (d122-104-38-246.sbr6.nsw.optusnet.com.au [122.104.38.246]) by mx.google.com with ESMTPS id a6sm3124092fak.1.2011.01.03.11.47.49 (version=SSLv3 cipher=RC4-MD5); Mon, 03 Jan 2011 11:47:52 -0800 (PST) From: Graeme Russ To: u-boot@lists.denx.de Date: Tue, 4 Jan 2011 06:46:31 +1100 Message-Id: <1294084016-2674-12-git-send-email-graeme.russ@gmail.com> X-Mailer: git-send-email 1.7.1.422.g049e9 In-Reply-To: <1294084016-2674-1-git-send-email-graeme.russ@gmail.com> References: <1294084016-2674-1-git-send-email-graeme.russ@gmail.com> Subject: [U-Boot] [RFC][PATCH 11/36] x86 - Make cpu init functions weak X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.9 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de --- arch/i386/cpu/cpu.c | 14 ++++++++++++-- arch/i386/cpu/sc520/sc520.c | 9 ++------- arch/i386/include/asm/u-boot-i386.h | 2 ++ board/eNET/eNET.c | 22 ---------------------- 4 files changed, 16 insertions(+), 31 deletions(-) --- 1.7.1.422.g049e9 diff --git a/arch/i386/cpu/cpu.c b/arch/i386/cpu/cpu.c index e96380a..06b27c8 100644 --- a/arch/i386/cpu/cpu.c +++ b/arch/i386/cpu/cpu.c @@ -87,7 +87,7 @@ static void reload_gdt(void) } -int cpu_init_f(void) +int x86_cpu_init_f(void) { const u32 em_rst = ~X86_CR0_EM; const u32 mp_ne_set = X86_CR0_MP | X86_CR0_NE; @@ -102,15 +102,25 @@ int cpu_init_f(void) return 0; } +int cpu_init_f(void) __attribute__((weak, alias("x86_cpu_init_f"))); -int cpu_init_r(void) +int x86_cpu_init_r(void) { + const u32 nw_cd_rst = ~(X86_CR0_NW | X86_CR0_CD); + + /* turn on the cache and disable write through */ + asm("movl %%cr0, %%eax\n" + "andl %0, %%eax\n" + "movl %%eax, %%cr0\n" + "wbinvd\n" : : "i" (nw_cd_rst): "eax"); + reload_gdt(); /* Initialize core interrupt and exception functionality of CPU */ cpu_init_interrupts (); return 0; } +int cpu_init_r(void) __attribute__((weak, alias("x86_cpu_init_r"))); int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { diff --git a/arch/i386/cpu/sc520/sc520.c b/arch/i386/cpu/sc520/sc520.c index 056df56..8e8986b 100644 --- a/arch/i386/cpu/sc520/sc520.c +++ b/arch/i386/cpu/sc520/sc520.c @@ -40,10 +40,8 @@ DECLARE_GLOBAL_DATA_PTR; volatile sc520_mmcr_t *sc520_mmcr = (sc520_mmcr_t *)0xfffef000; -void init_sc520(void) +int cpu_init_f(void) { - const u32 nw_cd_rst = ~(X86_CR0_NW | X86_CR0_CD); - /* * Set the UARTxCTL register at it's slower, * baud clock giving us a 1.8432 MHz reference @@ -85,10 +83,7 @@ void init_sc520(void) /* turn on the SDRAM write buffer */ writeb(0x11, &sc520_mmcr->dbctl); - /* turn on the cache and disable write through */ - asm("movl %%cr0, %%eax\n" - "andl %0, %%eax\n" - "movl %%eax, %%cr0\n" : : "i" (nw_cd_rst): "eax"); + return x86_cpu_init_f(); } unsigned long init_sc520_dram(void) diff --git a/arch/i386/include/asm/u-boot-i386.h b/arch/i386/include/asm/u-boot-i386.h index ce097a3..80db52f 100644 --- a/arch/i386/include/asm/u-boot-i386.h +++ b/arch/i386/include/asm/u-boot-i386.h @@ -25,7 +25,9 @@ #define _U_BOOT_I386_H_ 1 /* cpu/.../cpu.c */ +int x86_cpu_init_r(void); int cpu_init_r(void); +int x86_cpu_init_f(void); int cpu_init_f(void); /* cpu/.../timer.c */ diff --git a/board/eNET/eNET.c b/board/eNET/eNET.c index 7f0e257..30d8750 100644 --- a/board/eNET/eNET.c +++ b/board/eNET/eNET.c @@ -48,33 +48,11 @@ unsigned long monitor_flash_len = CONFIG_SYS_MONITOR_LEN; static void enet_timer_isr(void); static void enet_toggle_run_led(void); -void init_sc520_enet (void) -{ - /* Set CPU Speed to 100MHz */ - writeb(0x01, &sc520_mmcr->cpuctl); - - /* wait at least one millisecond */ - asm("movl $0x2000,%%ecx\n" - "0: pushl %%ecx\n" - "popl %%ecx\n" - "loop 0b\n": : : "ecx"); - - /* turn on the SDRAM write buffer */ - writeb(0x11, &sc520_mmcr->dbctl); - - /* turn on the cache and disable write through */ - asm("movl %%cr0, %%eax\n" - "andl $0x9fffffff, %%eax\n" - "movl %%eax, %%cr0\n" : : : "eax"); -} - /* * Miscellaneous platform dependent initializations */ int board_early_init_f(void) { - init_sc520_enet(); - writeb(0x01, &sc520_mmcr->gpcsrt); /* GP Chip Select Recovery Time */ writeb(0x07, &sc520_mmcr->gpcspw); /* GP Chip Select Pulse Width */ writeb(0x00, &sc520_mmcr->gpcsoff); /* GP Chip Select Offset */