[v2,6/6] SPARCV8 asr17 register support.

Submitted by Fabien Chouteau on Jan. 3, 2011, 2:07 p.m.

Details

Message ID 7369fd37ad9bb86e6ef272c3abf80f07ab946376.1294055704.git.chouteau@adacore.com
State New
Headers show

Commit Message

Fabien Chouteau Jan. 3, 2011, 2:07 p.m.
Signed-off-by: Fabien Chouteau <chouteau@adacore.com>
---
 target-sparc/cpu.h       |    1 +
 target-sparc/helper.c    |    3 ++-
 target-sparc/translate.c |   10 ++++++++++
 3 files changed, 13 insertions(+), 1 deletions(-)

Comments

Blue Swirl Jan. 4, 2011, 6:31 p.m.
On Mon, Jan 3, 2011 at 2:07 PM, Fabien Chouteau <chouteau@adacore.com> wrote:
>
> Signed-off-by: Fabien Chouteau <chouteau@adacore.com>
> ---
>  target-sparc/cpu.h       |    1 +
>  target-sparc/helper.c    |    3 ++-
>  target-sparc/translate.c |   10 ++++++++++
>  3 files changed, 13 insertions(+), 1 deletions(-)
>
> diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h
> index 7795be4..fe082e3 100644
> --- a/target-sparc/cpu.h
> +++ b/target-sparc/cpu.h
> @@ -266,6 +266,7 @@ typedef struct sparc_def_t {
>  #define CPU_FEATURE_CMT          (1 << 12)
>  #define CPU_FEATURE_GL           (1 << 13)
>  #define CPU_FEATURE_TA0_SHUTDOWN (1 << 14) /* Shutdown on "ta 0x0" */
> +#define CPU_FEATURE_ASR17        (1 << 15)
>  #ifndef TARGET_SPARC64
>  #define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP |  \
>                               CPU_FEATURE_MUL | CPU_FEATURE_DIV |     \
> diff --git a/target-sparc/helper.c b/target-sparc/helper.c
> index 49bdb58..baab379 100644
> --- a/target-sparc/helper.c
> +++ b/target-sparc/helper.c
> @@ -1302,7 +1302,8 @@ static const sparc_def_t sparc_defs[] = {
>         .mmu_sfsr_mask = 0xffffffff,
>         .mmu_trcr_mask = 0xffffffff,
>         .nwindows = 8,
> -        .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_TA0_SHUTDOWN,
> +        .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_TA0_SHUTDOWN |
> +        CPU_FEATURE_ASR17,
>     },
>  #endif
>  };
> diff --git a/target-sparc/translate.c b/target-sparc/translate.c
> index b0e8044..05f942f 100644
> --- a/target-sparc/translate.c
> +++ b/target-sparc/translate.c
> @@ -2068,6 +2068,16 @@ static void disas_sparc_insn(DisasContext * dc)
>                 case 0x10 ... 0x1f: /* implementation-dependent in the
>                                        SPARCv8 manual, rdy on the
>                                        microSPARC II */
> +                    if (rs1 == 0x11) { /* Read Asr17 */
> +                        TCGv r_const;
> +                        CHECK_IU_FEATURE(dc, ASR17);

This would make the instruction illegal for those CPUs which didn't
have this feature, now it is handled like rdy. So please change the if
() above to also handle the feature check without the macro.

Patch hide | download patch | download mbox

diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h
index 7795be4..fe082e3 100644
--- a/target-sparc/cpu.h
+++ b/target-sparc/cpu.h
@@ -266,6 +266,7 @@  typedef struct sparc_def_t {
 #define CPU_FEATURE_CMT          (1 << 12)
 #define CPU_FEATURE_GL           (1 << 13)
 #define CPU_FEATURE_TA0_SHUTDOWN (1 << 14) /* Shutdown on "ta 0x0" */
+#define CPU_FEATURE_ASR17        (1 << 15)
 #ifndef TARGET_SPARC64
 #define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP |  \
                               CPU_FEATURE_MUL | CPU_FEATURE_DIV |     \
diff --git a/target-sparc/helper.c b/target-sparc/helper.c
index 49bdb58..baab379 100644
--- a/target-sparc/helper.c
+++ b/target-sparc/helper.c
@@ -1302,7 +1302,8 @@  static const sparc_def_t sparc_defs[] = {
         .mmu_sfsr_mask = 0xffffffff,
         .mmu_trcr_mask = 0xffffffff,
         .nwindows = 8,
-        .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_TA0_SHUTDOWN,
+        .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_TA0_SHUTDOWN |
+        CPU_FEATURE_ASR17,
     },
 #endif
 };
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index b0e8044..05f942f 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -2068,6 +2068,16 @@  static void disas_sparc_insn(DisasContext * dc)
                 case 0x10 ... 0x1f: /* implementation-dependent in the
                                        SPARCv8 manual, rdy on the
                                        microSPARC II */
+                    if (rs1 == 0x11) { /* Read Asr17 */
+                        TCGv r_const;
+                        CHECK_IU_FEATURE(dc, ASR17);
+                        /* Asr17 for a Leon3 monoprocessor */
+                        r_const = tcg_const_tl((1 << 8)
+                                               | (dc->def->nwindows - 1));
+                        gen_movl_TN_reg(rd, r_const);
+                        tcg_temp_free(r_const);
+                        break;
+                    }
 #endif
                     gen_movl_TN_reg(rd, cpu_y);
                     break;