Message ID | 89e9aab20ed3580b1c802f4f33a5461a7c240cf9.1496774336.git.paweljarosz3691@gmail.com |
---|---|
State | Changes Requested |
Delegated to: | Philipp Tomsich |
Headers | show |
On 6 June 2017 at 12:52, Paweł Jarosz <paweljarosz3691@gmail.com> wrote: Commit message? > Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com> > --- > arch/arm/mach-rockchip/rk3066/Makefile | 1 + > arch/arm/mach-rockchip/rk3066/sdram_rk3066.c | 111 +++++++++++++++++++++++++++ > 2 files changed, 112 insertions(+) > create mode 100644 arch/arm/mach-rockchip/rk3066/sdram_rk3066.c > Acked-by: Simon Glass <sjg@chromium.org> > diff --git a/arch/arm/mach-rockchip/rk3066/Makefile b/arch/arm/mach-rockchip/rk3066/Makefile > index 4cf5df2..1d38518 100644 > --- a/arch/arm/mach-rockchip/rk3066/Makefile > +++ b/arch/arm/mach-rockchip/rk3066/Makefile > @@ -6,6 +6,7 @@ > > ifndef CONFIG_TPL_BUILD > obj-y += clk_rk3066.o > +obj-y += sdram_rk3066.o > obj-y += syscon_rk3066.o > else > obj-y += sdram_init.o > diff --git a/arch/arm/mach-rockchip/rk3066/sdram_rk3066.c b/arch/arm/mach-rockchip/rk3066/sdram_rk3066.c > new file mode 100644 > index 0000000..a713ac4 > --- /dev/null > +++ b/arch/arm/mach-rockchip/rk3066/sdram_rk3066.c > @@ -0,0 +1,111 @@ > +/* > + * (C) Copyright 2015 Google, Inc > + * Copyright 2014 Rockchip Inc. > + * > + * SPDX-License-Identifier: GPL-2.0 > + * > + * Adapted from the very similar rk3288 ddr init. > + */ > + > +#include <common.h> > +#include <clk.h> > +#include <dm.h> > +#include <dt-structs.h> > +#include <errno.h> > +#include <ram.h> > +#include <regmap.h> > +#include <syscon.h> > +#include <asm/io.h> > +#include <asm/arch/clock.h> > +#include <asm/arch/cru_rk3066.h> > +#include <asm/arch/ddr_rk3188.h> > +#include <asm/arch/grf_rk3066.h> > +#include <asm/arch/pmu_rk3188.h> > +#include <asm/arch/sdram.h> > +#include <linux/err.h> > + > +DECLARE_GLOBAL_DATA_PTR; > + > +struct dram_info { > + struct ram_info info; > + struct rk3188_pmu *pmu; > +}; > + > +size_t sdram_size_mb(struct rk3188_pmu *pmu) I wonder if most of this could go in a common function, or are the registers / offsets different? > +{ > + u32 rank, col, bk, cs0_row, cs1_row, bw, row_3_4; > + size_t chipsize_mb = 0; > + size_t size_mb = 0; > + u32 ch; > + u32 sys_reg = readl(&pmu->sys_reg[2]); > + u32 chans; > + > + chans = 1 + ((sys_reg >> SYS_REG_NUM_CH_SHIFT) & SYS_REG_NUM_CH_MASK); > + > + for (ch = 0; ch < chans; ch++) { > + rank = 1 + (sys_reg >> SYS_REG_RANK_SHIFT(ch) & > + SYS_REG_RANK_MASK); > + col = 9 + (sys_reg >> SYS_REG_COL_SHIFT(ch) & SYS_REG_COL_MASK); > + bk = 3 - ((sys_reg >> SYS_REG_BK_SHIFT(ch)) & SYS_REG_BK_MASK); > + cs0_row = 13 + (sys_reg >> SYS_REG_CS0_ROW_SHIFT(ch) & > + SYS_REG_CS0_ROW_MASK); > + cs1_row = 13 + (sys_reg >> SYS_REG_CS1_ROW_SHIFT(ch) & > + SYS_REG_CS1_ROW_MASK); > + bw = (2 >> ((sys_reg >> SYS_REG_BW_SHIFT(ch)) & > + SYS_REG_BW_MASK)); > + row_3_4 = sys_reg >> SYS_REG_ROW_3_4_SHIFT(ch) & > + SYS_REG_ROW_3_4_MASK; > + chipsize_mb = (1 << (cs0_row + col + bk + bw - 20)); > + > + if (rank > 1) > + chipsize_mb += chipsize_mb >> > + (cs0_row - cs1_row); > + if (row_3_4) > + chipsize_mb = chipsize_mb * 3 / 4; > + size_mb += chipsize_mb; > + } > + > + /* there can be no more than 2gb of memory */ > + size_mb = min(size_mb, 0x80000000 >> 20); > + > + return size_mb; > +} > +
Simon, Pawel, On 06/07/2017 05:10 AM, Simon Glass wrote: > On 6 June 2017 at 12:52, Paweł Jarosz <paweljarosz3691@gmail.com> wrote: > > Commit message? > >> Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com> >> --- >> arch/arm/mach-rockchip/rk3066/Makefile | 1 + >> arch/arm/mach-rockchip/rk3066/sdram_rk3066.c | 111 +++++++++++++++++++++++++++ >> 2 files changed, 112 insertions(+) >> create mode 100644 arch/arm/mach-rockchip/rk3066/sdram_rk3066.c >> > Acked-by: Simon Glass <sjg@chromium.org> > >> diff --git a/arch/arm/mach-rockchip/rk3066/Makefile b/arch/arm/mach-rockchip/rk3066/Makefile >> index 4cf5df2..1d38518 100644 >> --- a/arch/arm/mach-rockchip/rk3066/Makefile >> +++ b/arch/arm/mach-rockchip/rk3066/Makefile >> @@ -6,6 +6,7 @@ >> >> ifndef CONFIG_TPL_BUILD >> obj-y += clk_rk3066.o >> +obj-y += sdram_rk3066.o >> obj-y += syscon_rk3066.o >> else >> obj-y += sdram_init.o >> diff --git a/arch/arm/mach-rockchip/rk3066/sdram_rk3066.c b/arch/arm/mach-rockchip/rk3066/sdram_rk3066.c >> new file mode 100644 >> index 0000000..a713ac4 >> --- /dev/null >> +++ b/arch/arm/mach-rockchip/rk3066/sdram_rk3066.c >> @@ -0,0 +1,111 @@ >> +/* >> + * (C) Copyright 2015 Google, Inc >> + * Copyright 2014 Rockchip Inc. >> + * >> + * SPDX-License-Identifier: GPL-2.0 >> + * >> + * Adapted from the very similar rk3288 ddr init. >> + */ >> + >> +#include <common.h> >> +#include <clk.h> >> +#include <dm.h> >> +#include <dt-structs.h> >> +#include <errno.h> >> +#include <ram.h> >> +#include <regmap.h> >> +#include <syscon.h> >> +#include <asm/io.h> >> +#include <asm/arch/clock.h> >> +#include <asm/arch/cru_rk3066.h> >> +#include <asm/arch/ddr_rk3188.h> >> +#include <asm/arch/grf_rk3066.h> >> +#include <asm/arch/pmu_rk3188.h> >> +#include <asm/arch/sdram.h> >> +#include <linux/err.h> >> + >> +DECLARE_GLOBAL_DATA_PTR; >> + >> +struct dram_info { >> + struct ram_info info; >> + struct rk3188_pmu *pmu; >> +}; >> + >> +size_t sdram_size_mb(struct rk3188_pmu *pmu) > I wonder if most of this could go in a common function, or are the > registers / offsets different? The definition of sys_reg for all the Rockchip SoC are the same, the only difference may be some chip have dual channel while others only have one, but the definition is not conflict. The dram driver for rk3066, rk3188 and rk3288 are very similar. Thanks, - Kever > >> +{ >> + u32 rank, col, bk, cs0_row, cs1_row, bw, row_3_4; >> + size_t chipsize_mb = 0; >> + size_t size_mb = 0; >> + u32 ch; >> + u32 sys_reg = readl(&pmu->sys_reg[2]); >> + u32 chans; >> + >> + chans = 1 + ((sys_reg >> SYS_REG_NUM_CH_SHIFT) & SYS_REG_NUM_CH_MASK); >> + >> + for (ch = 0; ch < chans; ch++) { >> + rank = 1 + (sys_reg >> SYS_REG_RANK_SHIFT(ch) & >> + SYS_REG_RANK_MASK); >> + col = 9 + (sys_reg >> SYS_REG_COL_SHIFT(ch) & SYS_REG_COL_MASK); >> + bk = 3 - ((sys_reg >> SYS_REG_BK_SHIFT(ch)) & SYS_REG_BK_MASK); >> + cs0_row = 13 + (sys_reg >> SYS_REG_CS0_ROW_SHIFT(ch) & >> + SYS_REG_CS0_ROW_MASK); >> + cs1_row = 13 + (sys_reg >> SYS_REG_CS1_ROW_SHIFT(ch) & >> + SYS_REG_CS1_ROW_MASK); >> + bw = (2 >> ((sys_reg >> SYS_REG_BW_SHIFT(ch)) & >> + SYS_REG_BW_MASK)); >> + row_3_4 = sys_reg >> SYS_REG_ROW_3_4_SHIFT(ch) & >> + SYS_REG_ROW_3_4_MASK; >> + chipsize_mb = (1 << (cs0_row + col + bk + bw - 20)); >> + >> + if (rank > 1) >> + chipsize_mb += chipsize_mb >> >> + (cs0_row - cs1_row); >> + if (row_3_4) >> + chipsize_mb = chipsize_mb * 3 / 4; >> + size_mb += chipsize_mb; >> + } >> + >> + /* there can be no more than 2gb of memory */ >> + size_mb = min(size_mb, 0x80000000 >> 20); >> + >> + return size_mb; >> +} >> + > _______________________________________________ > U-Boot mailing list > U-Boot@lists.denx.de > https://lists.denx.de/listinfo/u-boot
> Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com> > Acked-by: Simon Glass <sjg@chromium.org> > --- > arch/arm/mach-rockchip/rk3066/Makefile | 1 + > arch/arm/mach-rockchip/rk3066/sdram_rk3066.c | 111 +++++++++++++++++++++++++++ > 2 files changed, 112 insertions(+) > create mode 100644 arch/arm/mach-rockchip/rk3066/sdram_rk3066.c > Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
On Tue, 6 Jun 2017, Paweł Jarosz wrote: > Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com> > Acked-by: Simon Glass <sjg@chromium.org> > Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> > --- > arch/arm/mach-rockchip/rk3066/Makefile | 1 + > arch/arm/mach-rockchip/rk3066/sdram_rk3066.c | 111 +++++++++++++++++++++++++++ > 2 files changed, 112 insertions(+) > create mode 100644 arch/arm/mach-rockchip/rk3066/sdram_rk3066.c > > diff --git a/arch/arm/mach-rockchip/rk3066/Makefile b/arch/arm/mach-rockchip/rk3066/Makefile > index 4cf5df2..1d38518 100644 > --- a/arch/arm/mach-rockchip/rk3066/Makefile > +++ b/arch/arm/mach-rockchip/rk3066/Makefile > @@ -6,6 +6,7 @@ > > ifndef CONFIG_TPL_BUILD > obj-y += clk_rk3066.o > +obj-y += sdram_rk3066.o > obj-y += syscon_rk3066.o > else > obj-y += sdram_init.o > diff --git a/arch/arm/mach-rockchip/rk3066/sdram_rk3066.c b/arch/arm/mach-rockchip/rk3066/sdram_rk3066.c > new file mode 100644 > index 0000000..a713ac4 > --- /dev/null > +++ b/arch/arm/mach-rockchip/rk3066/sdram_rk3066.c > @@ -0,0 +1,111 @@ > +/* > + * (C) Copyright 2015 Google, Inc > + * Copyright 2014 Rockchip Inc. > + * > + * SPDX-License-Identifier: GPL-2.0 > + * > + * Adapted from the very similar rk3288 ddr init. > + */ > + > +#include <common.h> > +#include <clk.h> > +#include <dm.h> > +#include <dt-structs.h> > +#include <errno.h> > +#include <ram.h> > +#include <regmap.h> > +#include <syscon.h> > +#include <asm/io.h> > +#include <asm/arch/clock.h> > +#include <asm/arch/cru_rk3066.h> > +#include <asm/arch/ddr_rk3188.h> > +#include <asm/arch/grf_rk3066.h> > +#include <asm/arch/pmu_rk3188.h> > +#include <asm/arch/sdram.h> > +#include <linux/err.h> > + > +DECLARE_GLOBAL_DATA_PTR; > + > +struct dram_info { > + struct ram_info info; > + struct rk3188_pmu *pmu; > +}; > + > +size_t sdram_size_mb(struct rk3188_pmu *pmu) > +{ > + u32 rank, col, bk, cs0_row, cs1_row, bw, row_3_4; > + size_t chipsize_mb = 0; > + size_t size_mb = 0; > + u32 ch; > + u32 sys_reg = readl(&pmu->sys_reg[2]); > + u32 chans; > + > + chans = 1 + ((sys_reg >> SYS_REG_NUM_CH_SHIFT) & SYS_REG_NUM_CH_MASK); > + > + for (ch = 0; ch < chans; ch++) { > + rank = 1 + (sys_reg >> SYS_REG_RANK_SHIFT(ch) & > + SYS_REG_RANK_MASK); > + col = 9 + (sys_reg >> SYS_REG_COL_SHIFT(ch) & SYS_REG_COL_MASK); > + bk = 3 - ((sys_reg >> SYS_REG_BK_SHIFT(ch)) & SYS_REG_BK_MASK); > + cs0_row = 13 + (sys_reg >> SYS_REG_CS0_ROW_SHIFT(ch) & > + SYS_REG_CS0_ROW_MASK); > + cs1_row = 13 + (sys_reg >> SYS_REG_CS1_ROW_SHIFT(ch) & > + SYS_REG_CS1_ROW_MASK); > + bw = (2 >> ((sys_reg >> SYS_REG_BW_SHIFT(ch)) & > + SYS_REG_BW_MASK)); > + row_3_4 = sys_reg >> SYS_REG_ROW_3_4_SHIFT(ch) & > + SYS_REG_ROW_3_4_MASK; > + chipsize_mb = (1 << (cs0_row + col + bk + bw - 20)); > + > + if (rank > 1) > + chipsize_mb += chipsize_mb >> > + (cs0_row - cs1_row); > + if (row_3_4) > + chipsize_mb = chipsize_mb * 3 / 4; > + size_mb += chipsize_mb; > + } > + > + /* there can be no more than 2gb of memory */ > + size_mb = min(size_mb, 0x80000000 >> 20); > + > + return size_mb; > +} The common functions for these are already merged on u-boot-rockchip/next. Please update your patchset to use these instead of duplicating here. > +static int rk3066_dmc_probe(struct udevice *dev) > +{ > + struct dram_info *priv = dev_get_priv(dev); > + > + priv->pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU); > + > + priv->info.base = CONFIG_SYS_SDRAM_BASE; > + priv->info.size = sdram_size_mb(priv->pmu) << 20; > + > + return 0; > +} > + > +static int rk3066_dmc_get_info(struct udevice *dev, struct ram_info *info) > +{ > + struct dram_info *priv = dev_get_priv(dev); > + > + *info = priv->info; > + > + return 0; > +} > + > +static struct ram_ops rk3066_dmc_ops = { > + .get_info = rk3066_dmc_get_info, > +}; > + > +static const struct udevice_id rk3066_dmc_ids[] = { > + { .compatible = "rockchip,rk3066-dmc" }, > + { } > +}; > + > +U_BOOT_DRIVER(dmc_rk3066) = { > + .name = "rockchip_rk3066_dmc", > + .id = UCLASS_RAM, > + .of_match = rk3066_dmc_ids, > + .ops = &rk3066_dmc_ops, > + .probe = rk3066_dmc_probe, > + .priv_auto_alloc_size = sizeof(struct dram_info), > +}; >
diff --git a/arch/arm/mach-rockchip/rk3066/Makefile b/arch/arm/mach-rockchip/rk3066/Makefile index 4cf5df2..1d38518 100644 --- a/arch/arm/mach-rockchip/rk3066/Makefile +++ b/arch/arm/mach-rockchip/rk3066/Makefile @@ -6,6 +6,7 @@ ifndef CONFIG_TPL_BUILD obj-y += clk_rk3066.o +obj-y += sdram_rk3066.o obj-y += syscon_rk3066.o else obj-y += sdram_init.o diff --git a/arch/arm/mach-rockchip/rk3066/sdram_rk3066.c b/arch/arm/mach-rockchip/rk3066/sdram_rk3066.c new file mode 100644 index 0000000..a713ac4 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3066/sdram_rk3066.c @@ -0,0 +1,111 @@ +/* + * (C) Copyright 2015 Google, Inc + * Copyright 2014 Rockchip Inc. + * + * SPDX-License-Identifier: GPL-2.0 + * + * Adapted from the very similar rk3288 ddr init. + */ + +#include <common.h> +#include <clk.h> +#include <dm.h> +#include <dt-structs.h> +#include <errno.h> +#include <ram.h> +#include <regmap.h> +#include <syscon.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/cru_rk3066.h> +#include <asm/arch/ddr_rk3188.h> +#include <asm/arch/grf_rk3066.h> +#include <asm/arch/pmu_rk3188.h> +#include <asm/arch/sdram.h> +#include <linux/err.h> + +DECLARE_GLOBAL_DATA_PTR; + +struct dram_info { + struct ram_info info; + struct rk3188_pmu *pmu; +}; + +size_t sdram_size_mb(struct rk3188_pmu *pmu) +{ + u32 rank, col, bk, cs0_row, cs1_row, bw, row_3_4; + size_t chipsize_mb = 0; + size_t size_mb = 0; + u32 ch; + u32 sys_reg = readl(&pmu->sys_reg[2]); + u32 chans; + + chans = 1 + ((sys_reg >> SYS_REG_NUM_CH_SHIFT) & SYS_REG_NUM_CH_MASK); + + for (ch = 0; ch < chans; ch++) { + rank = 1 + (sys_reg >> SYS_REG_RANK_SHIFT(ch) & + SYS_REG_RANK_MASK); + col = 9 + (sys_reg >> SYS_REG_COL_SHIFT(ch) & SYS_REG_COL_MASK); + bk = 3 - ((sys_reg >> SYS_REG_BK_SHIFT(ch)) & SYS_REG_BK_MASK); + cs0_row = 13 + (sys_reg >> SYS_REG_CS0_ROW_SHIFT(ch) & + SYS_REG_CS0_ROW_MASK); + cs1_row = 13 + (sys_reg >> SYS_REG_CS1_ROW_SHIFT(ch) & + SYS_REG_CS1_ROW_MASK); + bw = (2 >> ((sys_reg >> SYS_REG_BW_SHIFT(ch)) & + SYS_REG_BW_MASK)); + row_3_4 = sys_reg >> SYS_REG_ROW_3_4_SHIFT(ch) & + SYS_REG_ROW_3_4_MASK; + chipsize_mb = (1 << (cs0_row + col + bk + bw - 20)); + + if (rank > 1) + chipsize_mb += chipsize_mb >> + (cs0_row - cs1_row); + if (row_3_4) + chipsize_mb = chipsize_mb * 3 / 4; + size_mb += chipsize_mb; + } + + /* there can be no more than 2gb of memory */ + size_mb = min(size_mb, 0x80000000 >> 20); + + return size_mb; +} + +static int rk3066_dmc_probe(struct udevice *dev) +{ + struct dram_info *priv = dev_get_priv(dev); + + priv->pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU); + + priv->info.base = CONFIG_SYS_SDRAM_BASE; + priv->info.size = sdram_size_mb(priv->pmu) << 20; + + return 0; +} + +static int rk3066_dmc_get_info(struct udevice *dev, struct ram_info *info) +{ + struct dram_info *priv = dev_get_priv(dev); + + *info = priv->info; + + return 0; +} + +static struct ram_ops rk3066_dmc_ops = { + .get_info = rk3066_dmc_get_info, +}; + +static const struct udevice_id rk3066_dmc_ids[] = { + { .compatible = "rockchip,rk3066-dmc" }, + { } +}; + +U_BOOT_DRIVER(dmc_rk3066) = { + .name = "rockchip_rk3066_dmc", + .id = UCLASS_RAM, + .of_match = rk3066_dmc_ids, + .ops = &rk3066_dmc_ops, + .probe = rk3066_dmc_probe, + .priv_auto_alloc_size = sizeof(struct dram_info), +};
Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com> --- arch/arm/mach-rockchip/rk3066/Makefile | 1 + arch/arm/mach-rockchip/rk3066/sdram_rk3066.c | 111 +++++++++++++++++++++++++++ 2 files changed, 112 insertions(+) create mode 100644 arch/arm/mach-rockchip/rk3066/sdram_rk3066.c