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[PULL,10/22] target/arm: add data cache invalidation cp15 instruction to cortex-r5

Message ID 95e9a242e2a393c7d4e5cc04340e39c3a9420f03.1496591095.git.mjt@msgid.tls.msk.ru
State New
Headers show

Commit Message

Michael Tokarev June 4, 2017, 3:45 p.m. UTC 
From: Luc MICHEL <luc.michel@git.antfield.fr>

The cp15, CRn=15, opc1=0, CRm=5, opc2=0 instruction invalidates all the
data cache on the cortex-r5. Implementing it as a NOP.

Signed-off-by: Luc MICHEL <luc.michel@git.antfield.fr>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
---
 target/arm/cpu.c | 2 ++
 1 file changed, 2 insertions(+)
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Patch

diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index e748097860..04a3fea03f 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1082,6 +1082,8 @@  static const ARMCPRegInfo cortexr5_cp_reginfo[] = {
       .access = PL1_RW, .type = ARM_CP_CONST },
     { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
       .access = PL1_RW, .type = ARM_CP_CONST },
+    { .name = "DCACHE_INVAL", .cp = 15, .opc1 = 0, .crn = 15, .crm = 5,
+      .opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP },
     REGINFO_SENTINEL
 };