| Message ID | 20170531235737.11676-6-sjg@chromium.org |
|---|---|
| State | Accepted |
| Delegated to: | Simon Glass |
| Headers | show |
At present if CONFIG_ARMV7_LPAE is defined then mmu_setup() will use
instructions which are invalid on ARMv4T. This happens on Tegra since it
has an ARMv4T boot CPU. Add a check for the architecture version to allow
the code to be built. It will not actually be executed by the boot CPU,
but needs to compile.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
Changes in v2: None
arch/arm/lib/cache-cp15.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Applied to u-boot-dm, thanks!
diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c index 0f7020a315..f293573601 100644 --- a/arch/arm/lib/cache-cp15.c +++ b/arch/arm/lib/cache-cp15.c @@ -129,7 +129,7 @@ static inline void mmu_setup(void) dram_bank_mmu_setup(i); } -#ifdef CONFIG_ARMV7_LPAE +#if defined(CONFIG_ARMV7_LPAE) && __LINUX_ARM_ARCH__ != 4 /* Set up 4 PTE entries pointing to our 4 1GB page tables */ for (i = 0; i < 4; i++) { u64 *page_table = (u64 *)(gd->arch.tlb_addr + (4096 * 4));
At present if CONFIG_ARMV7_LPAE is defined then mmu_setup() will use instructions which are invalid on ARMv4T. This happens on Tegra since it has an ARMv4T boot CPU. Add a check for the architecture version to allow the code to be built. It will not actually be executed by the boot CPU, but needs to compile. Signed-off-by: Simon Glass <sjg@chromium.org> --- Changes in v2: None arch/arm/lib/cache-cp15.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)