diff mbox

[U-Boot,4/4] x86: baytrail: Change lpe/lpss-sio/scc FSP properties to integer

Message ID 1496217855-8745-4-git-send-email-bmeng.cn@gmail.com
State Accepted
Commit f8f291b0962c795fcb025338d5c2284e2357a669
Delegated to: Bin Meng
Headers show

Commit Message

Bin Meng May 31, 2017, 8:04 a.m. UTC 
At present lpe/lpss-sio/scc FSP properties are all boolean, but in
fact for "enable-lpe" it has 3 possible options. This adds macros
for these options and change the property from a boolean type to
an integer type, and change their names to explicitly indicate what
the property is really for.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>

---

 arch/x86/cpu/baytrail/fsp_configs.c                  | 11 ++++++-----
 arch/x86/dts/bayleybay.dts                           |  6 +++---
 arch/x86/dts/baytrail_som-db5800-som-6867.dts        |  4 ++--
 arch/x86/dts/conga-qeval20-qa3-e3845.dts             |  6 +++---
 arch/x86/dts/dfi-bt700.dtsi                          |  6 +++---
 arch/x86/dts/minnowmax.dts                           |  6 +++---
 arch/x86/include/asm/arch-baytrail/fsp/fsp_configs.h | 10 ++++++++++
 arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h     |  6 +++---
 doc/device-tree-bindings/misc/intel,baytrail-fsp.txt | 12 ++++++------
 9 files changed, 39 insertions(+), 28 deletions(-)

Comments

Stefan Roese May 31, 2017, 8:41 a.m. UTC | #1 
On 31.05.2017 10:04, Bin Meng wrote:
> At present lpe/lpss-sio/scc FSP properties are all boolean, but in
> fact for "enable-lpe" it has 3 possible options. This adds macros
> for these options and change the property from a boolean type to
> an integer type, and change their names to explicitly indicate what
> the property is really for.
> 
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>

Reviewed-by: Stefan Roese <sr@denx.de>

Thanks,
Stefan
Simon Glass June 1, 2017, 3:12 a.m. UTC | #2 
On 31 May 2017 at 02:04, Bin Meng <bmeng.cn@gmail.com> wrote:
> At present lpe/lpss-sio/scc FSP properties are all boolean, but in
> fact for "enable-lpe" it has 3 possible options. This adds macros
> for these options and change the property from a boolean type to
> an integer type, and change their names to explicitly indicate what
> the property is really for.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>
> ---
>
>  arch/x86/cpu/baytrail/fsp_configs.c                  | 11 ++++++-----
>  arch/x86/dts/bayleybay.dts                           |  6 +++---
>  arch/x86/dts/baytrail_som-db5800-som-6867.dts        |  4 ++--
>  arch/x86/dts/conga-qeval20-qa3-e3845.dts             |  6 +++---
>  arch/x86/dts/dfi-bt700.dtsi                          |  6 +++---
>  arch/x86/dts/minnowmax.dts                           |  6 +++---
>  arch/x86/include/asm/arch-baytrail/fsp/fsp_configs.h | 10 ++++++++++
>  arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h     |  6 +++---
>  doc/device-tree-bindings/misc/intel,baytrail-fsp.txt | 12 ++++++------
>  9 files changed, 39 insertions(+), 28 deletions(-)

Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng June 1, 2017, 8:34 a.m. UTC | #3 
On Thu, Jun 1, 2017 at 11:12 AM, Simon Glass <sjg@chromium.org> wrote:
> On 31 May 2017 at 02:04, Bin Meng <bmeng.cn@gmail.com> wrote:
>> At present lpe/lpss-sio/scc FSP properties are all boolean, but in
>> fact for "enable-lpe" it has 3 possible options. This adds macros
>> for these options and change the property from a boolean type to
>> an integer type, and change their names to explicitly indicate what
>> the property is really for.
>>
>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>>
>> ---
>>
>>  arch/x86/cpu/baytrail/fsp_configs.c                  | 11 ++++++-----
>>  arch/x86/dts/bayleybay.dts                           |  6 +++---
>>  arch/x86/dts/baytrail_som-db5800-som-6867.dts        |  4 ++--
>>  arch/x86/dts/conga-qeval20-qa3-e3845.dts             |  6 +++---
>>  arch/x86/dts/dfi-bt700.dtsi                          |  6 +++---
>>  arch/x86/dts/minnowmax.dts                           |  6 +++---
>>  arch/x86/include/asm/arch-baytrail/fsp/fsp_configs.h | 10 ++++++++++
>>  arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h     |  6 +++---
>>  doc/device-tree-bindings/misc/intel,baytrail-fsp.txt | 12 ++++++------
>>  9 files changed, 39 insertions(+), 28 deletions(-)
>
> Reviewed-by: Simon Glass <sjg@chromium.org>

applied to u-boot-x86, thanks!
diff mbox

Patch

diff --git a/arch/x86/cpu/baytrail/fsp_configs.c b/arch/x86/cpu/baytrail/fsp_configs.c
index c48ac07..45f9bf9 100644
--- a/arch/x86/cpu/baytrail/fsp_configs.c
+++ b/arch/x86/cpu/baytrail/fsp_configs.c
@@ -175,9 +175,10 @@  void update_fsp_configs(struct fsp_config_data *config,
 	fsp_upd->enable_azalia = fdtdec_get_bool(blob, node,
 						 "fsp,enable-azalia");
 	fsp_upd->enable_xhci = fdtdec_get_bool(blob, node, "fsp,enable-xhci");
-	fsp_upd->enable_lpe = fdtdec_get_bool(blob, node, "fsp,enable-lpe");
-	fsp_upd->lpss_sio_enable_pci_mode = fdtdec_get_bool(blob, node,
-			"fsp,lpss-sio-enable-pci-mode");
+	fsp_upd->lpe_mode = fdtdec_get_int(blob, node, "fsp,lpe-mode",
+					   LPE_MODE_PCI);
+	fsp_upd->lpss_sio_mode = fdtdec_get_int(blob, node, "fsp,lpss-sio-mode",
+					   LPSS_SIO_MODE_PCI);
 	fsp_upd->enable_dma0 = fdtdec_get_bool(blob, node, "fsp,enable-dma0");
 	fsp_upd->enable_dma1 = fdtdec_get_bool(blob, node, "fsp,enable-dma1");
 	fsp_upd->enable_i2_c0 = fdtdec_get_bool(blob, node, "fsp,enable-i2c0");
@@ -199,8 +200,8 @@  void update_fsp_configs(struct fsp_config_data *config,
 	fsp_upd->mrc_debug_msg = fdtdec_get_bool(blob, node,
 						 "fsp,mrc-debug-msg");
 	fsp_upd->isp_enable = fdtdec_get_bool(blob, node, "fsp,isp-enable");
-	fsp_upd->scc_enable_pci_mode = fdtdec_get_bool(blob, node,
-			"fsp,scc-enable-pci-mode");
+	fsp_upd->scc_mode = fdtdec_get_int(blob, node, "fsp,scc-mode",
+					   SCC_MODE_PCI);
 	fsp_upd->igd_render_standby = fdtdec_get_bool(blob, node,
 						      "fsp,igd-render-standby");
 	fsp_upd->txe_uma_enable = fdtdec_get_bool(blob, node,
diff --git a/arch/x86/dts/bayleybay.dts b/arch/x86/dts/bayleybay.dts
index a577b93..0c314e0 100644
--- a/arch/x86/dts/bayleybay.dts
+++ b/arch/x86/dts/bayleybay.dts
@@ -248,8 +248,8 @@ 
 		fsp,enable-spi;
 		fsp,enable-sata;
 		fsp,sata-mode = <SATA_MODE_AHCI>;
-		fsp,enable-lpe;
-		fsp,lpss-sio-enable-pci-mode;
+		fsp,lpe-mode = <LPE_MODE_PCI>;
+		fsp,lpss-sio-mode = <LPSS_SIO_MODE_PCI>;
 		fsp,enable-dma0;
 		fsp,enable-dma1;
 		fsp,enable-i2c0;
@@ -264,7 +264,7 @@ 
 		fsp,igd-dvmt50-pre-alloc = <IGD_DVMT50_PRE_ALLOC_64MB>;
 		fsp,aperture-size = <APERTURE_SIZE_256MB>;
 		fsp,gtt-size = <GTT_SIZE_2MB>;
-		fsp,scc-enable-pci-mode;
+		fsp,scc-mode = <SCC_MODE_PCI>;
 		fsp,os-selection = <OS_SELECTION_LINUX>;
 		fsp,emmc45-ddr50-enabled;
 		fsp,emmc45-retune-timer-value = <8>;
diff --git a/arch/x86/dts/baytrail_som-db5800-som-6867.dts b/arch/x86/dts/baytrail_som-db5800-som-6867.dts
index 3fc36f1..171e7ff 100644
--- a/arch/x86/dts/baytrail_som-db5800-som-6867.dts
+++ b/arch/x86/dts/baytrail_som-db5800-som-6867.dts
@@ -268,7 +268,7 @@ 
 		fsp,enable-sata;
 		fsp,sata-mode = <SATA_MODE_AHCI>;
 		fsp,enable-azalia;
-		fsp,lpss-sio-enable-pci-mode;
+		fsp,lpss-sio-mode = <LPSS_SIO_MODE_PCI>;
 		fsp,enable-dma0;
 		fsp,enable-dma1;
 		fsp,enable-i2c0;
@@ -283,7 +283,7 @@ 
 		fsp,igd-dvmt50-pre-alloc = <IGD_DVMT50_PRE_ALLOC_64MB>;
 		fsp,aperture-size = <APERTURE_SIZE_256MB>;
 		fsp,gtt-size = <GTT_SIZE_2MB>;
-		fsp,scc-enable-pci-mode;
+		fsp,scc-mode = <SCC_MODE_PCI>;
 		fsp,os-selection = <OS_SELECTION_LINUX>;
 		fsp,enable-igd;
 	};
diff --git a/arch/x86/dts/conga-qeval20-qa3-e3845.dts b/arch/x86/dts/conga-qeval20-qa3-e3845.dts
index 369cea6..ae11ccc 100644
--- a/arch/x86/dts/conga-qeval20-qa3-e3845.dts
+++ b/arch/x86/dts/conga-qeval20-qa3-e3845.dts
@@ -258,8 +258,8 @@ 
 		fsp,enable-spi;
 		fsp,enable-sata;
 		fsp,sata-mode = <SATA_MODE_AHCI>;
-		fsp,enable-lpe;
-		fsp,lpss-sio-enable-pci-mode;
+		fsp,lpe-mode = <LPE_MODE_PCI>;
+		fsp,lpss-sio-mode = <LPSS_SIO_MODE_PCI>;
 		fsp,enable-dma0;
 		fsp,enable-dma1;
 		fsp,enable-pwm0;
@@ -267,7 +267,7 @@ 
 		fsp,igd-dvmt50-pre-alloc = <IGD_DVMT50_PRE_ALLOC_64MB>;
 		fsp,aperture-size = <APERTURE_SIZE_256MB>;
 		fsp,gtt-size = <GTT_SIZE_2MB>;
-		fsp,scc-enable-pci-mode;
+		fsp,scc-mode = <SCC_MODE_PCI>;
 		fsp,os-selection = <OS_SELECTION_LINUX>;
 		fsp,emmc45-ddr50-enabled;
 		fsp,emmc45-retune-timer-value = <8>;
diff --git a/arch/x86/dts/dfi-bt700.dtsi b/arch/x86/dts/dfi-bt700.dtsi
index 33f2a9c..04aa95a 100644
--- a/arch/x86/dts/dfi-bt700.dtsi
+++ b/arch/x86/dts/dfi-bt700.dtsi
@@ -261,8 +261,8 @@ 
 		fsp,enable-spi;
 		fsp,enable-sata;
 		fsp,sata-mode = <SATA_MODE_AHCI>;
-		fsp,enable-lpe;
-		fsp,lpss-sio-enable-pci-mode;
+		fsp,lpe-mode = <LPE_MODE_PCI>;
+		fsp,lpss-sio-mode = <LPSS_SIO_MODE_PCI>;
 		fsp,enable-dma0;
 		fsp,enable-dma1;
 		fsp,enable-i2c0;
@@ -277,7 +277,7 @@ 
 		fsp,igd-dvmt50-pre-alloc = <IGD_DVMT50_PRE_ALLOC_64MB>;
 		fsp,aperture-size = <APERTURE_SIZE_256MB>;
 		fsp,gtt-size = <GTT_SIZE_2MB>;
-		fsp,scc-enable-pci-mode;
+		fsp,scc-mode = <SCC_MODE_PCI>;
 		fsp,os-selection = <OS_SELECTION_LINUX>;
 		fsp,emmc45-ddr50-enabled;
 		fsp,emmc45-retune-timer-value = <8>;
diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts
index a4e2fa2..4c0a8fe 100644
--- a/arch/x86/dts/minnowmax.dts
+++ b/arch/x86/dts/minnowmax.dts
@@ -272,8 +272,8 @@ 
 		fsp,enable-spi;
 		fsp,enable-sata;
 		fsp,sata-mode = <SATA_MODE_AHCI>;
-		fsp,enable-lpe;
-		fsp,lpss-sio-enable-pci-mode;
+		fsp,lpe-mode = <LPE_MODE_PCI>;
+		fsp,lpss-sio-mode = <LPSS_SIO_MODE_PCI>;
 		fsp,enable-dma0;
 		fsp,enable-dma1;
 		fsp,enable-i2c0;
@@ -288,7 +288,7 @@ 
 		fsp,igd-dvmt50-pre-alloc = <IGD_DVMT50_PRE_ALLOC_64MB>;
 		fsp,aperture-size = <APERTURE_SIZE_256MB>;
 		fsp,gtt-size = <GTT_SIZE_2MB>;
-		fsp,scc-enable-pci-mode;
+		fsp,scc-mode = <SCC_MODE_PCI>;
 		fsp,os-selection = <OS_SELECTION_LINUX>;
 		fsp,emmc45-ddr50-enabled;
 		fsp,emmc45-retune-timer-value = <8>;
diff --git a/arch/x86/include/asm/arch-baytrail/fsp/fsp_configs.h b/arch/x86/include/asm/arch-baytrail/fsp/fsp_configs.h
index 382cb79..1c6c247 100644
--- a/arch/x86/include/asm/arch-baytrail/fsp/fsp_configs.h
+++ b/arch/x86/include/asm/arch-baytrail/fsp/fsp_configs.h
@@ -93,4 +93,14 @@  struct fspinit_rtbuf {
 #define DIMM_SIDES_1RANKS		0
 #define DIMM_SIDES_2RANKS		1
 
+#define LPE_MODE_DISABLED		0
+#define LPE_MODE_PCI			1
+#define LPE_MODE_ACPI			2
+
+#define LPSS_SIO_MODE_ACPI		0
+#define LPSS_SIO_MODE_PCI		1
+
+#define SCC_MODE_ACPI			0
+#define SCC_MODE_PCI			1
+
 #endif /* __FSP_CONFIGS_H__ */
diff --git a/arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h b/arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h
index b083b6e..8c07b37 100644
--- a/arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h
+++ b/arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h
@@ -47,8 +47,8 @@  struct __packed upd_region {
 	uint8_t enable_azalia;			/* Offset 0x002f */
 	uint32_t azalia_config_ptr;		/* Offset 0x0030 */
 	uint8_t enable_xhci;			/* Offset 0x0034 */
-	uint8_t enable_lpe;			/* Offset 0x0035 */
-	uint8_t lpss_sio_enable_pci_mode;	/* Offset 0x0036 */
+	uint8_t lpe_mode;			/* Offset 0x0035 */
+	uint8_t lpss_sio_mode;			/* Offset 0x0036 */
 	uint8_t enable_dma0;			/* Offset 0x0037 */
 	uint8_t enable_dma1;			/* Offset 0x0038 */
 	uint8_t enable_i2_c0;			/* Offset 0x0039 */
@@ -67,7 +67,7 @@  struct __packed upd_region {
 	uint8_t reserved2[5];			/* Offset 0x0046 */
 	uint8_t mrc_debug_msg;			/* Offset 0x004b */
 	uint8_t isp_enable;			/* Offset 0x004c */
-	uint8_t scc_enable_pci_mode;		/* Offset 0x004d */
+	uint8_t scc_mode;			/* Offset 0x004d */
 	uint8_t igd_render_standby;		/* Offset 0x004e */
 	uint8_t txe_uma_enable;			/* Offset 0x004f */
 	uint8_t os_selection;			/* Offset 0x0050 */
diff --git a/doc/device-tree-bindings/misc/intel,baytrail-fsp.txt b/doc/device-tree-bindings/misc/intel,baytrail-fsp.txt
index 691ae53..929ae88 100644
--- a/doc/device-tree-bindings/misc/intel,baytrail-fsp.txt
+++ b/doc/device-tree-bindings/misc/intel,baytrail-fsp.txt
@@ -19,8 +19,6 @@  is matched up to Intel's E3800 FSPv4 release.
 - fsp,enable-sata
 - fsp,enable-azalia
 - fsp,enable-xhci
-- fsp,enable-lpe
-- fsp,lpss-sio-enable-pci-mode
 - fsp,enable-dma0
 - fsp,enable-dma1
 - fsp,enable-i2-c0
@@ -35,7 +33,6 @@  is matched up to Intel's E3800 FSPv4 release.
 - fsp,enable-hsi
 - fsp,mrc-debug-msg
 - fsp,isp-enable
-- fsp,scc-enable-pci-mode
 - fsp,igd-render-standby
 - fsp,txe-uma-enable
 - fsp,emmc45-ddr50-enabled
@@ -57,9 +54,12 @@  discovered by the FSP and used to setup main memory.
 - fsp,mrc-init-spd-addr2
 - fsp,emmc-boot-mode
 - fsp,sata-mode
+- fsp,lpe-mode
+- fsp,lpss-sio-mode
 - fsp,igd-dvmt50-pre-alloc
 - fsp,aperture-size
 - fsp,gtt-size
+- fsp,scc-mode
 - fsp,os-selection
 - fsp,emmc45-retune-timer-value
 
@@ -110,8 +110,8 @@  Example (from MinnowMax Dual Core):
 		fsp,enable-spi;
 		fsp,enable-sata;
 		fsp,sata-mode = <SATA_MODE_AHCI>;
-		fsp,enable-lpe;
-		fsp,lpss-sio-enable-pci-mode;
+		fsp,lpe-mode = <LPE_MODE_PCI>;
+		fsp,lpss-sio-mode = <LPSS_SIO_MODE_PCI>;
 		fsp,enable-dma0;
 		fsp,enable-dma1;
 		fsp,enable-i2c0;
@@ -126,7 +126,7 @@  Example (from MinnowMax Dual Core):
 		fsp,igd-dvmt50-pre-alloc = <IGD_DVMT50_PRE_ALLOC_64MB>;
 		fsp,aperture-size = <APERTURE_SIZE_256MB>;
 		fsp,gtt-size = <GTT_SIZE_2MB>;
-		fsp,scc-enable-pci-mode;
+		fsp,scc-mode = <SCC_MODE_PCI>;
 		fsp,os-selection = <OS_SELECTION_LINUX>;
 		fsp,emmc45-ddr50-enabled;
 		fsp,emmc45-retune-timer-value = <8>;