| Message ID | 1496194635-29193-1-git-send-email-uboot@andestech.com |
|---|---|
| State | Superseded |
| Delegated to: | Andes |
| Headers | show |
On 05/31/2017 10:37 AM, Andes wrote: > From: rick <rick@andestech.com> > > Support Andestech ftsdc010 SD/MMC device tree flow > on AG101P/AE3XX platforms. > > Signed-off-by: rick <rick@andestech.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> > --- > arch/nds32/dts/ae3xx.dts | 8 ++++++++ > arch/nds32/dts/ag101p.dts | 8 ++++++++ > 2 files changed, 16 insertions(+) > > diff --git a/arch/nds32/dts/ae3xx.dts b/arch/nds32/dts/ae3xx.dts > index 4221e4b..781eabc 100644 > --- a/arch/nds32/dts/ae3xx.dts > +++ b/arch/nds32/dts/ae3xx.dts > @@ -62,6 +62,14 @@ > interrupts = <25 4>; > }; > > + mmc0: mmc@f0e00000 { > + compatible = "andestech,atsdc010"; > + clock-freq-min-max = <400000 100000000>; > + fifo-depth = <0x10>; > + reg = <0xf0e00000 0x1000>; > + interrupts = <17 4>; > + }; > + > nor@0,0 { > compatible = "cfi-flash"; > reg = <0x88000000 0x1000>; > diff --git a/arch/nds32/dts/ag101p.dts b/arch/nds32/dts/ag101p.dts > index 99cde2f..dd2bf8f 100644 > --- a/arch/nds32/dts/ag101p.dts > +++ b/arch/nds32/dts/ag101p.dts > @@ -60,4 +60,12 @@ > reg = <0x90900000 0x1000>; > interrupts = <25 4>; > }; > + > + mmc0: mmc@98e00000 { > + compatible = "andestech,atsdc010"; > + clock-freq-min-max = <400000 30000000>; > + fifo-depth = <0x10>; > + reg = <0x98e00000 0x1000>; > + interrupts = <5 4>; > + }; > }; >
diff --git a/arch/nds32/dts/ae3xx.dts b/arch/nds32/dts/ae3xx.dts index 4221e4b..781eabc 100644 --- a/arch/nds32/dts/ae3xx.dts +++ b/arch/nds32/dts/ae3xx.dts @@ -62,6 +62,14 @@ interrupts = <25 4>; }; + mmc0: mmc@f0e00000 { + compatible = "andestech,atsdc010"; + clock-freq-min-max = <400000 100000000>; + fifo-depth = <0x10>; + reg = <0xf0e00000 0x1000>; + interrupts = <17 4>; + }; + nor@0,0 { compatible = "cfi-flash"; reg = <0x88000000 0x1000>; diff --git a/arch/nds32/dts/ag101p.dts b/arch/nds32/dts/ag101p.dts index 99cde2f..dd2bf8f 100644 --- a/arch/nds32/dts/ag101p.dts +++ b/arch/nds32/dts/ag101p.dts @@ -60,4 +60,12 @@ reg = <0x90900000 0x1000>; interrupts = <25 4>; }; + + mmc0: mmc@98e00000 { + compatible = "andestech,atsdc010"; + clock-freq-min-max = <400000 30000000>; + fifo-depth = <0x10>; + reg = <0x98e00000 0x1000>; + interrupts = <5 4>; + }; };