Patchwork [U-Boot] fsl_pci: Update PCIe boot ouput

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Submitter Peter Tyser
Date Dec. 28, 2010, 11:47 p.m.
Message ID <1293580045-9994-1-git-send-email-ptyser@xes-inc.com>
Download mbox | patch
Permalink /patch/76873/
State Accepted
Commit 213ac73e2caff8b477c31f85d8132f8cc116f366
Delegated to: Kumar Gala
Headers show

Comments

Peter Tyser - Dec. 28, 2010, 11:47 p.m.
This change does the following:
- Adds printing of negotiated link width.  This information can be
  useful when debugging PCIe issues.
- Makes it optional for boards to implement board_serdes_name().
  Previously boards that did not implement it would print unsightly
  output such as "PCIE1: Connected to <NULL>..."
- Rewords the PCIe boot output to reduce line length and to make it
  clear that the "base address XYZ" value refers to the base address of
  the internal processor PCIe registers and not a standard PCI BAR
  value.
- Changes "PCIE" output to the standard "PCIe"

Before change:
PCIE1: connected to <NULL> as Root Complex (base addr ef008000)
  01:00.0     - 10b5:8518 - Bridge device
   02:01.0    - 10b5:8518 - Bridge device
   02:02.0    - 10b5:8518 - Bridge device
   02:03.0    - 10b5:8518 - Bridge device
PCIE1: Bus 00 - 05
PCIE2: connected to <NULL> as Endpoint (base addr ef009000)
PCIE2: Bus 06 - 06

After change:
PCIe1: Root Complex of PEX8518 Switch, x4, regs @ 0xef008000
  01:00.0     - 10b5:8518 - Bridge device
   02:01.0    - 10b5:8518 - Bridge device
   02:02.0    - 10b5:8518 - Bridge device
   02:03.0    - 10b5:8518 - Bridge device
PCIe1: Bus 00 - 05
PCIe2: Endpoint of VPX Fabric A, x2, regs @ 0xef009000
PCIe2: Bus 06 - 06

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
---
This applies to Kumar's u-boot-85xx.git 'dev' branch.

 arch/powerpc/include/asm/fsl_pci.h |    2 +-
 drivers/pci/fsl_pci_init.c         |   38 ++++++++++++++++++-----------------
 2 files changed, 21 insertions(+), 19 deletions(-)
Paul Gortmaker - Jan. 6, 2011, 7:17 p.m.
On Tue, Dec 28, 2010 at 6:47 PM, Peter Tyser <ptyser@xes-inc.com> wrote:
> This change does the following:
> - Adds printing of negotiated link width.  This information can be
>  useful when debugging PCIe issues.
> - Makes it optional for boards to implement board_serdes_name().
>  Previously boards that did not implement it would print unsightly
>  output such as "PCIE1: Connected to <NULL>..."
> - Rewords the PCIe boot output to reduce line length and to make it
>  clear that the "base address XYZ" value refers to the base address of
>  the internal processor PCIe registers and not a standard PCI BAR
>  value.
> - Changes "PCIE" output to the standard "PCIe"
>
> Before change:
> PCIE1: connected to <NULL> as Root Complex (base addr ef008000)
>  01:00.0     - 10b5:8518 - Bridge device
>   02:01.0    - 10b5:8518 - Bridge device
>   02:02.0    - 10b5:8518 - Bridge device
>   02:03.0    - 10b5:8518 - Bridge device
> PCIE1: Bus 00 - 05
> PCIE2: connected to <NULL> as Endpoint (base addr ef009000)
> PCIE2: Bus 06 - 06
>
> After change:
> PCIe1: Root Complex of PEX8518 Switch, x4, regs @ 0xef008000
>  01:00.0     - 10b5:8518 - Bridge device
>   02:01.0    - 10b5:8518 - Bridge device
>   02:02.0    - 10b5:8518 - Bridge device
>   02:03.0    - 10b5:8518 - Bridge device
> PCIe1: Bus 00 - 05
> PCIe2: Endpoint of VPX Fabric A, x2, regs @ 0xef009000
> PCIe2: Bus 06 - 06
>
> Signed-off-by: Peter Tyser <ptyser@xes-inc.com>

Tested-by: Paul Gortmaker <paul.gortmaker@windriver.com>

The sbc8641d had the same <NULL> issue; I've put the before and after
below for reference.

Paul.

---------------------------
Board: Wind River SBC8641D
I2C:   ready
DRAM:      DDR: 512 MiB
FLASH: 16 MiB
PCIE1: connected to <NULL> as Root Complex (base addr f8008000)
  01:00.0     - 1148:9e00 - Network controller
PCIE1: Bus 00 - 01
PCIE2: connected to <NULL> as Root Complex (base addr f8009000)
PCIE2: Bus 02 - 02
In:    serial
Out:   serial
Err:   serial
Net:   eTSEC1, eTSEC2, eTSEC3, eTSEC4
-----------------------------
Board: Wind River SBC8641D
I2C:   ready
DRAM:      DDR: 512 MiB
FLASH: 16 MiB
PCIe1: Root Complex, x1, regs @ 0xf8008000
  01:00.0     - 1148:9e00 - Network controller
PCIe1: Bus 00 - 01
PCIe2: Root Complex, no link, regs @ 0xf8009000
PCIe2: Bus 02 - 02
In:    serial
Out:   serial
Err:   serial
Net:   eTSEC1, eTSEC2, eTSEC3, eTSEC4
------------------------
Kumar Gala - Jan. 9, 2011, 8:42 p.m.
On Dec 28, 2010, at 5:47 PM, Peter Tyser wrote:

> This change does the following:
> - Adds printing of negotiated link width.  This information can be
>  useful when debugging PCIe issues.
> - Makes it optional for boards to implement board_serdes_name().
>  Previously boards that did not implement it would print unsightly
>  output such as "PCIE1: Connected to <NULL>..."
> - Rewords the PCIe boot output to reduce line length and to make it
>  clear that the "base address XYZ" value refers to the base address of
>  the internal processor PCIe registers and not a standard PCI BAR
>  value.
> - Changes "PCIE" output to the standard "PCIe"
> 
> Before change:
> PCIE1: connected to <NULL> as Root Complex (base addr ef008000)
>  01:00.0     - 10b5:8518 - Bridge device
>   02:01.0    - 10b5:8518 - Bridge device
>   02:02.0    - 10b5:8518 - Bridge device
>   02:03.0    - 10b5:8518 - Bridge device
> PCIE1: Bus 00 - 05
> PCIE2: connected to <NULL> as Endpoint (base addr ef009000)
> PCIE2: Bus 06 - 06
> 
> After change:
> PCIe1: Root Complex of PEX8518 Switch, x4, regs @ 0xef008000
>  01:00.0     - 10b5:8518 - Bridge device
>   02:01.0    - 10b5:8518 - Bridge device
>   02:02.0    - 10b5:8518 - Bridge device
>   02:03.0    - 10b5:8518 - Bridge device
> PCIe1: Bus 00 - 05
> PCIe2: Endpoint of VPX Fabric A, x2, regs @ 0xef009000
> PCIe2: Bus 06 - 06
> 
> Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
> ---
> This applies to Kumar's u-boot-85xx.git 'dev' branch.

applied to 85xx

- k

Patch

diff --git a/arch/powerpc/include/asm/fsl_pci.h b/arch/powerpc/include/asm/fsl_pci.h
index 15ab50d..0a98bde 100644
--- a/arch/powerpc/include/asm/fsl_pci.h
+++ b/arch/powerpc/include/asm/fsl_pci.h
@@ -27,7 +27,6 @@ 
 
 int fsl_setup_hose(struct pci_controller *hose, unsigned long addr);
 int fsl_is_pci_agent(struct pci_controller *hose);
-void fsl_pci_init(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data);
 void fsl_pci_config_unlock(struct pci_controller *hose);
 void ft_fsl_pci_setup(void *blob, const char *compat, unsigned long ctrl_addr);
 
@@ -172,6 +171,7 @@  struct fsl_pci_info {
 	int pci_num;
 };
 
+void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info);
 int fsl_pci_init_port(struct fsl_pci_info *pci_info,
 				struct pci_controller *hose, int busno);
 int fsl_pcie_init_ctrl(int busno, u32 devdisr, enum srds_prtcl dev,
diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c
index 64c0198..fa23992 100644
--- a/drivers/pci/fsl_pci_init.c
+++ b/drivers/pci/fsl_pci_init.c
@@ -217,8 +217,10 @@  static int fsl_pci_setup_inbound_windows(struct pci_controller *hose,
 	return 1;
 }
 
-void fsl_pci_init(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data)
+void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info)
 {
+	u32 cfg_addr = (u32)&((ccsr_fsl_pci_t *)pci_info->regs)->cfg_addr;
+	u32 cfg_data = (u32)&((ccsr_fsl_pci_t *)pci_info->regs)->cfg_data;
 	u16 temp16;
 	u32 temp32;
 	int enabled, r, inbound = 0;
@@ -235,10 +237,6 @@  void fsl_pci_init(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data)
 	u64 out_hi = 0, out_lo = -1ULL;
 	u32 pcicsrbar, pcicsrbar_sz;
 
-#ifdef DEBUG
-	int neg_link_w;
-#endif
-
 	pci_setup_indirect(hose, cfg_addr, cfg_data);
 
 	/* Handle setup of outbound windows first */
@@ -354,20 +352,20 @@  void fsl_pci_init(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data)
 #endif
 
 		if (!enabled) {
-			debug("....PCIE link error.  Skipping scan."
-			      "LTSSM=0x%02x\n", ltssm);
+			/* Let the user know there's no PCIe link */
+			printf("no link, regs @ 0x%lx\n", pci_info->regs);
 			hose->last_busno = hose->first_busno;
 			return;
 		}
 
 		out_be32(&pci->pme_msg_det, 0xffffffff);
 		out_be32(&pci->pme_msg_int_en, 0xffffffff);
-#ifdef DEBUG
+
+		/* Print the negotiated PCIe link width */
 		pci_hose_read_config_word(hose, dev, PCI_LSR, &temp16);
-		neg_link_w = (temp16 & 0x3f0 ) >> 4;
-		printf("...PCIE LTSSM=0x%x, Negotiated link width=%d\n",
-		      ltssm, neg_link_w);
-#endif
+		printf("x%d, regs @ 0x%lx\n", (temp16 & 0x3f0 ) >> 4,
+			pci_info->regs);
+
 		hose->current_busno++; /* Start scan with secondary */
 		pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);
 	}
@@ -476,7 +474,7 @@  int fsl_pci_init_port(struct fsl_pci_info *pci_info,
 	hose->region_count = r - hose->regions;
 	hose->first_busno = busno;
 
-	fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
+	fsl_pci_init(hose, pci_info);
 
 	if (fsl_is_pci_agent(hose)) {
 		fsl_pci_config_unlock(hose);
@@ -485,7 +483,7 @@  int fsl_pci_init_port(struct fsl_pci_info *pci_info,
 
 	pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap);
 	printf("PCI%s%x: Bus %02x - %02x\n", pcie_cap == PCI_CAP_ID_EXP ?
-		"E" : "", pci_info->pci_num,
+		"e" : "", pci_info->pci_num,
 		hose->first_busno, hose->last_busno);
 
 	return(hose->last_busno + 1);
@@ -525,10 +523,14 @@  int fsl_configure_pcie(struct fsl_pci_info *info,
 
 	set_next_law(info->mem_phys, law_size_bits(info->mem_size), info->law);
 	set_next_law(info->io_phys, law_size_bits(info->io_size), info->law);
+
 	is_endpoint = fsl_setup_hose(hose, info->regs);
-	printf("PCIE%u: connected to %s as %s (base addr %lx)\n",
-	       info->pci_num, connected,
-	       is_endpoint ? "Endpoint" : "Root Complex", info->regs);
+	printf("PCIe%u: %s", info->pci_num,
+		is_endpoint ? "Endpoint" : "Root Complex");
+	if (connected)
+		printf(" of %s", connected);
+	puts(", ");
+
 	return fsl_pci_init_port(info, hose, busno);
 }
 
@@ -585,7 +587,7 @@  int fsl_pcie_init_ctrl(int busno, u32 devdisr, enum srds_prtcl dev,
 		busno = fsl_configure_pcie(pci_info, hose,
 				board_serdes_name(dev), busno);
 	} else {
-		printf("PCIE%d: disabled\n", num + 1);
+		printf("PCIe%d: disabled\n", num + 1);
 	}
 
 	return busno;