From patchwork Tue Dec 28 00:47:04 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Rigby X-Patchwork-Id: 76807 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 98FC5B70B3 for ; Tue, 28 Dec 2010 11:48:26 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 439C82813F; Tue, 28 Dec 2010 01:48:13 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Fu5k6COM6O3I; Tue, 28 Dec 2010 01:48:13 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 916B028100; Tue, 28 Dec 2010 01:47:50 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id CB268280F3 for ; Tue, 28 Dec 2010 01:47:46 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id kHN7I5N8jN1W for ; Tue, 28 Dec 2010 01:47:45 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-pw0-f44.google.com (mail-pw0-f44.google.com [209.85.160.44]) by theia.denx.de (Postfix) with ESMTP id E6983280D4 for ; Tue, 28 Dec 2010 01:47:38 +0100 (CET) Received: by pwi7 with SMTP id 7so977555pwi.3 for ; Mon, 27 Dec 2010 16:47:37 -0800 (PST) Received: by 10.142.113.6 with SMTP id l6mr5372747wfc.99.1293497257546; Mon, 27 Dec 2010 16:47:37 -0800 (PST) Received: from localhost.localdomain (c-98-202-243-83.hsd1.ut.comcast.net [98.202.243.83]) by mx.google.com with ESMTPS id b11sm18438929wff.9.2010.12.27.16.47.35 (version=TLSv1/SSLv3 cipher=RC4-MD5); Mon, 27 Dec 2010 16:47:37 -0800 (PST) From: John Rigby To: u-boot@lists.denx.de Date: Mon, 27 Dec 2010 17:47:04 -0700 Message-Id: <1293497228-15911-5-git-send-email-john.rigby@linaro.org> X-Mailer: git-send-email 1.7.3.1.120.g38a18 In-Reply-To: <1293497228-15911-1-git-send-email-john.rigby@linaro.org> References: <1293497228-15911-1-git-send-email-john.rigby@linaro.org> Cc: steve@sakoman.com Subject: [U-Boot] [RFC PATCH 4/8] OMAP3: add dram timing constants from x-loader X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.9 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Signed-off-by: John Rigby --- arch/arm/include/asm/arch-omap3/mem.h | 45 +++++++++++++++++++++++++++++++++ 1 files changed, 45 insertions(+), 0 deletions(-) diff --git a/arch/arm/include/asm/arch-omap3/mem.h b/arch/arm/include/asm/arch-omap3/mem.h index f165949..970e8b4 100644 --- a/arch/arm/include/asm/arch-omap3/mem.h +++ b/arch/arm/include/asm/arch-omap3/mem.h @@ -54,6 +54,29 @@ enum { #define SDP_SDRC_DLLAB_CTRL ((DLL_ENADLL << 3) | \ (DLL_LOCKDLL << 2) | (DLL_DLLPHASE_90 << 1)) +#define SDP_3430_SDRC_RFR_CTRL_165MHz 0x0004e201 /* 7.8us/6ns - 50=0x4e2 */ +#define SDP_3430_SDRC_RFR_CTRL_200MHz 0x0005e601 /* 7.8us/5ns - 50=0x5e6 */ + +/* set the 343x-SDRC incoming address convention */ +#if defined(SDRC_B_R_C) +#define B_ALL (0 << 6) /* bank-row-column */ +#elif defined(SDRC_B1_R_B0_C) +#define B_ALL (1 << 6) /* bank1-row-bank0-column */ +#elif defined(SDRC_R_B_C) +#define B_ALL (2 << 6) /* row-bank-column */ +#endif + + +#define SDP_SDRC_MDCFG_0_DDR (0x02584019|B_ALL) +#define SDP_SDRC_MDCFG_0_DDR_MICRON_XM (0x03588019|B_ALL) +#define SDP_SDRC_MDCFG_0_DDR_NUMONYX_XM (0x04590019|B_ALL) + +#define SDP_SDRC_MR_0_DDR 0x00000032 +/* Diabling power down mode using CKE pin */ +#define SDP_SDRC_POWER_POP 0x00000081 + + + /* Infineon part of 3430SDP (165MHz optimized) 6.06ns * ACTIMA * TDAL = Twr/Tck + Trp/tck = 15/6 + 18/6 = 2.5 + 3 = 5.5 -> 6 @@ -167,6 +190,28 @@ enum { (NUMONYX_XSR_165 << 0) | (NUMONYX_TXP_165 << 8) | \ (NUMONYX_TWTR_165 << 16)) +/* Micron part (200MHz optimized) 5 ns + */ +#define MICRON_TDAL_200 6 +#define MICRON_TDPL_200 3 +#define MICRON_TRRD_200 2 +#define MICRON_TRCD_200 3 +#define MICRON_TRP_200 3 +#define MICRON_TRAS_200 8 +#define MICRON_TRC_200 11 +#define MICRON_TRFC_200 15 +#define MICRON_V_ACTIMA_200 ((MICRON_TRFC_200 << 27) | (MICRON_TRC_200 << 22) | (MICRON_TRAS_200 << 18) \ + | (MICRON_TRP_200 << 15) | (MICRON_TRCD_200 << 12) |(MICRON_TRRD_200 << 9) | \ + (MICRON_TDPL_200 << 6) | (MICRON_TDAL_200)) + +#define MICRON_TWTR_200 2 +#define MICRON_TCKE_200 4 +#define MICRON_TXP_200 2 +#define MICRON_XSR_200 23 +#define MICRON_V_ACTIMB_200 ((MICRON_TCKE_200 << 12) | (MICRON_XSR_200 << 0)) | \ + (MICRON_TXP_200 << 8) | (MICRON_TWTR_200 << 16) + + #ifdef CONFIG_OMAP3_INFINEON_DDR #define V_ACTIMA_165 INFINEON_V_ACTIMA_165 #define V_ACTIMB_165 INFINEON_V_ACTIMB_165