From patchwork Fri May 26 01:53:06 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gavin Shan X-Patchwork-Id: 767197 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3wYq2D4g1vz9s86 for ; Fri, 26 May 2017 11:54:44 +1000 (AEST) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3wYq2D3s5tzDqnK for ; Fri, 26 May 2017 11:54:44 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3wYq1k5BYJzDqkw for ; Fri, 26 May 2017 11:54:18 +1000 (AEST) Received: from pps.filterd (m0098394.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.20/8.16.0.20) with SMTP id v4Q1rSDW034183 for ; Thu, 25 May 2017 21:54:15 -0400 Received: from e23smtp03.au.ibm.com (e23smtp03.au.ibm.com [202.81.31.145]) by mx0a-001b2d01.pphosted.com with ESMTP id 2ap9rdat47-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Thu, 25 May 2017 21:54:14 -0400 Received: from localhost by e23smtp03.au.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Fri, 26 May 2017 11:54:08 +1000 Received: from d23av06.au.ibm.com (d23av06.au.ibm.com [9.190.235.151]) by d23relay07.au.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id v4Q1rxxv64225420 for ; Fri, 26 May 2017 11:54:07 +1000 Received: from d23av06.au.ibm.com (localhost [127.0.0.1]) by d23av06.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id v4Q1rZXf021810 for ; Fri, 26 May 2017 11:53:35 +1000 Received: from ozlabs.au.ibm.com (ozlabs.au.ibm.com [9.192.253.14]) by d23av06.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id v4Q1rY57021329; Fri, 26 May 2017 11:53:35 +1000 Received: from bran.ozlabs.ibm.com (haven.au.ibm.com [9.192.254.114]) by ozlabs.au.ibm.com (Postfix) with ESMTP id 14E58A025A; Fri, 26 May 2017 11:53:10 +1000 (AEST) Received: from gwshan.ozlabs.ibm.com (shangw.ozlabs.ibm.com [10.61.2.199]) by bran.ozlabs.ibm.com (Postfix) with ESMTP id 083F1E3881; Fri, 26 May 2017 11:53:10 +1000 (AEST) Received: by gwshan.ozlabs.ibm.com (Postfix, from userid 1000) id F16BFAC264B; Fri, 26 May 2017 11:53:09 +1000 (AEST) From: Gavin Shan To: skiboot@lists.ozlabs.org Date: Fri, 26 May 2017 11:53:06 +1000 X-Mailer: git-send-email 2.7.4 In-Reply-To: <1495763586-27238-1-git-send-email-gwshan@linux.vnet.ibm.com> References: <1495763586-27238-1-git-send-email-gwshan@linux.vnet.ibm.com> X-TM-AS-MML: disable x-cbid: 17052601-0008-0000-0000-00000131B3A7 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 17052601-0009-0000-0000-00000960A0AC Message-Id: <1495763586-27238-3-git-send-email-gwshan@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-05-26_01:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=1 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1703280000 definitions=main-1705260033 Subject: [Skiboot] [PATCH 3/3] core/pci: Fix access non-existing registers on disabling cmpl timeout X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" The PCIe transaction timeout is disabled if the capability is claimed in register PCIECAP_EXP_DCAP2, meaning we read it unconditionally. However, the reigster can be invalid if PCIe capability version isn't bigger than 1. It potentially causes pending (hanged) PCIe transaction. This fixes the issue by check the cached PCIe capability version. We won't touch register PCIECAP_EXP_DCAP2 and PCICAP_EXP_DCTL2 if PCIe capability version isn't bigger than 1. The limitation isn't applied to P7/P8/P9's root port as we clearly know those registers are valid there. Signed-off-by: Gavin Shan --- core/pci.c | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/core/pci.c b/core/pci.c index 29c3df6..f173cc2 100644 --- a/core/pci.c +++ b/core/pci.c @@ -162,8 +162,6 @@ static void pci_init_pcie_cap(struct phb *phb, struct pci_device *pd) return; } - pci_set_cap(pd, PCI_CFG_CAP_ID_EXP, ecap, 0ul, false); - /* * XXX We observe a problem on some PLX switches where one * of the downstream ports appears as an upstream port, we @@ -174,9 +172,15 @@ static void pci_init_pcie_cap(struct phb *phb, struct pci_device *pd) if (pd->parent && pd->parent->dev_type == PCIE_TYPE_SWITCH_UPPORT && pd->vdid == 0x874810b5 && pd->dev_type == PCIE_TYPE_SWITCH_UPPORT) { PCIDBG(phb, pd->bdfn, "Fixing up bad PLX downstream port !\n"); + + reg &= ~PCICAP_EXP_CAP_TYPE; + reg |= PCIE_TYPE_SWITCH_DNPORT; pd->dev_type = PCIE_TYPE_SWITCH_DNPORT; } + /* Set PCIe capability */ + pci_set_cap(pd, PCI_CFG_CAP_ID_EXP, ecap, reg, false); + /* XXX Handle ARI */ if (pd->dev_type == PCIE_TYPE_SWITCH_DNPORT || pd->dev_type == PCIE_TYPE_ROOT_PORT) @@ -833,11 +837,13 @@ static int pci_configure_mps(struct phb *phb, static void pci_disable_completion_timeout(struct phb *phb, struct pci_device *pd) { - uint32_t ecap; - uint32_t val; + uint32_t ecap, val; + uint16_t ecap_data; /* PCIE capability required */ - if (!pci_has_cap(pd, PCI_CFG_CAP_ID_EXP, false)) + ecap_data = (uint16_t)pci_cap_data(pd, PCI_CFG_CAP_ID_EXP, false); + if (!pci_has_cap(pd, PCI_CFG_CAP_ID_EXP, false) || + (ecap_data & PCICAP_EXP_CAP_VERSION) <= 1) return; /* Check if it has capability to disable completion timeout */