diff mbox

[U-Boot,06/12] arm: Disable LPAE if not enabled

Message ID 20170522111732.11265-7-sjg@chromium.org
State Accepted
Commit 50a4886b3b8579a5d3dad337906de9b5a3fef6d1
Delegated to: Tom Warren
Headers show

Commit Message

Simon Glass May 22, 2017, 11:17 a.m. UTC
If CONFIG_ARMV7_LPAE is not defined we should make sure that the feature
is disabled. This can happen if U-Boot is chain-loaded from another boot
loader which does enable LPAE.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

 arch/arm/lib/cache-cp15.c | 9 +++++++++
 1 file changed, 9 insertions(+)

Comments

Tom Rini May 23, 2017, 1:15 a.m. UTC | #1
On Mon, May 22, 2017 at 05:17:26AM -0600, Simon Glass wrote:

> If CONFIG_ARMV7_LPAE is not defined we should make sure that the feature
> is disabled. This can happen if U-Boot is chain-loaded from another boot
> loader which does enable LPAE.
> 
> Signed-off-by: Simon Glass <sjg@chromium.org>

Reviewed-by: Tom Rini <trini@konsulko.com>
diff mbox

Patch

diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c
index f293573601..cf852c061b 100644
--- a/arch/arm/lib/cache-cp15.c
+++ b/arch/arm/lib/cache-cp15.c
@@ -172,6 +172,15 @@  static inline void mmu_setup(void)
 			: : "r" (MEMORY_ATTRIBUTES) : "memory");
 	}
 #elif defined(CONFIG_CPU_V7)
+	if (is_hyp()) {
+		/* Set HTCR to disable LPAE */
+		asm volatile("mcr p15, 4, %0, c2, c0, 2"
+			: : "r" (0) : "memory");
+	} else {
+		/* Set TTBCR to disable LPAE */
+		asm volatile("mcr p15, 0, %0, c2, c0, 2"
+			: : "r" (0) : "memory");
+	}
 	/* Set TTBR0 */
 	reg = gd->arch.tlb_addr & TTBR0_BASE_ADDR_MASK;
 #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)