From patchwork Fri May 19 07:05:42 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dong Aisheng X-Patchwork-Id: 764456 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3wTfGx3K3nz9s5L for ; Fri, 19 May 2017 17:06:17 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754058AbdESHGP (ORCPT ); Fri, 19 May 2017 03:06:15 -0400 Received: from mail-by2nam03on0041.outbound.protection.outlook.com ([104.47.42.41]:58640 "EHLO NAM03-BY2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1752069AbdESHFv (ORCPT ); Fri, 19 May 2017 03:05:51 -0400 Received: from BN6PR03CA0091.namprd03.prod.outlook.com (10.164.122.157) by BLUPR03MB168.namprd03.prod.outlook.com (10.255.212.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1084.16; Fri, 19 May 2017 07:05:49 +0000 Received: from BN1BFFO11FD029.protection.gbl (2a01:111:f400:7c10::1:175) by BN6PR03CA0091.outlook.office365.com (2603:10b6:405:6f::29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1101.14 via Frontend Transport; Fri, 19 May 2017 07:05:49 +0000 Authentication-Results: spf=fail (sender IP is 192.88.158.2) smtp.mailfrom=nxp.com; nxp.com; dkim=none (message not signed) header.d=none;nxp.com; dmarc=fail action=none header.from=nxp.com; Received-SPF: Fail (protection.outlook.com: domain of nxp.com does not designate 192.88.158.2 as permitted sender) receiver=protection.outlook.com; client-ip=192.88.158.2; helo=az84smr01.freescale.net; Received: from az84smr01.freescale.net (192.88.158.2) by BN1BFFO11FD029.mail.protection.outlook.com (10.58.144.92) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1075.5 via Frontend Transport; Fri, 19 May 2017 07:05:48 +0000 Received: from b29396-OptiPlex-7040.ap.freescale.net (b29396-OptiPlex-7040.ap.freescale.net [10.192.242.182]) by az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id v4J75bFl023171; Fri, 19 May 2017 00:05:45 -0700 From: Dong Aisheng To: CC: , , , , , , , Dong Aisheng Subject: [PATCH V2 2/5] pinctrl: imx: add generic pin config core support Date: Fri, 19 May 2017 15:05:42 +0800 Message-ID: <1495177545-23006-3-git-send-email-aisheng.dong@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1495177545-23006-1-git-send-email-aisheng.dong@nxp.com> References: <1495177545-23006-1-git-send-email-aisheng.dong@nxp.com> X-EOPAttributedMessage: 0 X-Matching-Connectors: 131396511490886749; (91ab9b29-cfa4-454e-5278-08d120cd25b8); () X-Forefront-Antispam-Report: CIP:192.88.158.2; IPV:NLI; CTRY:US; EFV:NLI; SFV:NSPM; SFS:(10009020)(6009001)(336005)(39380400002)(39850400002)(39400400002)(39410400002)(39860400002)(39840400002)(39450400003)(2980300002)(1110001)(1109001)(339900001)(54534003)(199003)(189002)(9170700003)(498600001)(106466001)(2351001)(5660300001)(33646002)(4326008)(189998001)(105606002)(356003)(47776003)(305945005)(50986999)(76176999)(85426001)(50466002)(8656002)(48376002)(110136004)(53936002)(54906002)(38730400002)(77096006)(86362001)(104016004)(2950100002)(8936002)(36756003)(6666003)(6916009)(81166006)(8676002)(50226002)(2906002)(5003940100001)(41533002); DIR:OUT; SFP:1101; SCL:1; SRVR:BLUPR03MB168; H:az84smr01.freescale.net; FPR:; SPF:Fail; MLV:ovrnspm; A:1; MX:1; PTR:InfoDomainNonexistent; LANG:en; X-Microsoft-Exchange-Diagnostics: 1; BN1BFFO11FD029; 1:1CbZGJCu71hdq18zmWuAu7Z2nO1XvV58iPZZ7GuorlvcsDjyMfw/PFza/sSiR6iaTHl7WBxit41R8H9YXKT5HTM+RXe0gHDFigp98alK6DYumn6nlCS/YdWx4KYaWSwpqp3DkgHqwQ/pLHaLrWcxH+qqGpGJMGjpOsOmTglBf2HWQKZWtACyieWPqMMd+E33GgbPJ8fKXYLvEOZGbG6Ye4whztVOV/9KMy93VGSVkVa7RUUeN6o/vNQEZu1CX309H0FMIU5xI04uybSCMj8CVTqLp8U7sGdch3J2klX04ZgHLvbvLfe8swiCGDoghPkY8mB7SEjLns6R/Fqe5N7rFaJTsrjkv5yKHsN3Zg+14QpV9qGJJMIK79KfZbpWy7AoP/3yg5Bx2/7zqfr7vOKsXNSWbHfn12/zypKKh4FyZtsuJ8lrLZazF+pmjg5a5TE18Y2sq63UhyV38au+gkh77OSP/kaeI9NpDJzLaaWvoKL+SKL3fTRSi7HqknyUjqn+e6JKtrk8lsAIB5FgMwEWy2XeW8WkxbwNDMzRgzIy3yIXeuzlyRaLPSWqG0liVDyouV74pki2fOaY82IvLIIHiIzxEAvE1di3t1bDmWrEDf/r6x+KWvCdBYO+MJgE+NvCzEwONeFLUznc+AHDFSPVXxnaP0kXAo3/qsxAw7SL+zd7RUzHkAhlFVz30W4bUg/dj7sY18o3tGVHKBNJb23tVUtUFtiLsjk7FXc9UwCdAwM= MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: cba27d60-69e0-4d61-09a3-08d49e857a96 X-Microsoft-Antispam: UriScan:; BCL:0; PCL:0; RULEID:(22001)(201703131430075)(201703131517081); SRVR:BLUPR03MB168; X-Microsoft-Exchange-Diagnostics: 1; BLUPR03MB168; 3:eaoO444v8KmF94un0CPfGjw7hgSKEyBpVb4Zu3EWNuvtYFk7e6ULRVA66h4GoJ824qMUiQ8vNSYsX4Womu9JjxUMfUizGzHrbC6o1Iar6kP0R5J6jwmurEh98gSmLd4TE+FCODh89CFJTqYtcb7cdlS9crc27zLdaKvpG67Ih23b9uWw03nXjyuRpjZY7EQ/sOrOO0WGHNk0dGMrU20Rrj7x6/1CNsxPNYaG75r+wKgbTz0lR9Yp9DQVhtCNds9rdtzllEwfttysR0Y4/uL1VBASeVaNDOSfyaxDKpC0BGsRwAUF5lCwnCga26IpDssG2K4A6QQvoB5kyQN34JsC1lB4tAsbo7ivu16iSkoTfpWuo53z6a2oCtlGx9Li6gtH+ha8Z7LtyhcNK9Enf7XPX3cl60IUa6XY7ayuVdWPGExJ1y9Apb1rjezAI13OijSb; 25:2pWY7SL7xC9XeFwxeDD3VqTZdTwTinHAprQbWpsE9WxVmq2RS0eEOBBieMrNkRo1jfuuafa49Rr9HjdYnZw2Hr1Fp8mcN2Jt+YDUtO0vEhNzGhxwaVqAZYSRghJfKny6qX0XdhjAIG409qcT/Seo3XXcy72WgvJuNtj3UpN5Q+gXBUigcS6fFcUpkJPnunr27M2VeNB/ImDO82QSy2sxJdVeUWSNpIiy09KSLKjpCPYfolldaTP/DB+tvgr1syl4ugS0BLeom+PEf8yor7boheCoQ/60u08DOguD/3c4kfu7gmLxntUrKcSjvFbWEeASmlMCWioUVt/0S4BHUsYYymoSf3P9Ld27dIGXB60e5ePYf/aoIaiYbVsmptvjac1hDhz6ZFBqgKHwpWzPl4A8eMmRRaUC37gi1MWXcSBldrkKdRGwu9B3G0AxkcIzZA8sSWi6DNX5Av2hEn8DBbDlAQ== X-Microsoft-Exchange-Diagnostics: 1; BLUPR03MB168; 31:GfqNizlDlnrYZBuA6FeCrpr1LXkHSEMWzHRj6+O0VBiOm8P7t3WnKBE3uYC1Hd+NWTyJQt4f0WRGWeyVQ7gy5SLAkaZrv7qaq/NyWHwdbYdt4v8jfa8ds0zKlVHFm0xIwuC/49ZUUQRx+KZrH2AcOQFvk0Pk6tkADKlOM2nzCRzAu3CwNeR7ND2b43HgySttOsbWIMQAVCskBnlbsOkj0IOIUd6K0cejIDGqrxFzqxhhJ5r2uzswMbsLpdkokvYOPoqWdnpeA2nIHtbJKWC73w== X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:(185117386973197); X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(6095135)(601004)(2401047)(13024025)(13023025)(8121501046)(13018025)(5005006)(13017025)(13015025)(3002001)(10201501046)(93006095)(93001095)(6055026)(6096035)(20161123565025)(201703131430075)(201703131441075)(201703131448075)(201703131433075)(201703161259150)(20161123559100)(20161123563025)(20161123561025)(20161123556025); SRVR:BLUPR03MB168; BCL:0; PCL:0; RULEID:(400006); SRVR:BLUPR03MB168; X-Microsoft-Exchange-Diagnostics: =?us-ascii?Q?1; BLUPR03MB168; 4:qnQa2tHk27VcdfumqfRAoaKrIGSrDKex6LqkCKA28xV?= =?us-ascii?Q?5K7N1mdjMlXEOwPv/9btt5hUCOTxSU9hXWu9MWKHzvLJiLGpunCyK0y1fM1w?= =?us-ascii?Q?tJfaQ7tPyuqwd428djBzcQcmYMFdeCwiwcRHjoHgDG8EHrFHxrEVniodl8H/?= =?us-ascii?Q?nVnV6B7cvwoGjlrqxeXMQSczQiazLCMT4dAKapum6OOtvkWlmE5Rwl/9C5sN?= =?us-ascii?Q?NRxzQdchARqwAtghmCXIBWAwfiurZS5IkGk+Lq5l1njbcgSINYNyCRATCgGk?= =?us-ascii?Q?++LNNnsw5bxjsWeZ4HrU0aCLd8sCkIWe0No6NsdwA+mKjfULK8ws0U/4ARMN?= =?us-ascii?Q?GLE9KegKEZm8dJH4YD7oBu4f/U3HQOWHQhm665jazChSqcgQ/EBjilR3kyre?= =?us-ascii?Q?zr/p5DOdVLFRZ9FX/el2xpGyW69vgSA5qR3CAl/Gc2P6B+v8zhXMMQvCQWeL?= =?us-ascii?Q?Oz/iBtiX8AZXca4i1bnrL8R+0s2yy/x49fvu8Nbj6A8BCvENmd5gHzmwz5QZ?= =?us-ascii?Q?SKCeqrv31AVaEwXMD7/RaYKABhrU1bYsoF6xORmyZo/+pSuhanZOQW+PtAgs?= =?us-ascii?Q?TsW8m/jhliKwYoQmjVexfwzTCXxxHuZ+2j3JbImZQS1LCAEZh1IhIx19bVen?= =?us-ascii?Q?Cj9J7x5Gtxm62uObK9mX9KSytQwhap9W6O3WQO1mJOT+Sl2iwUekaDVSGDxr?= =?us-ascii?Q?UBKDDOrqziPh47J9yMTFJAYVTdklg3vqUWTzc5t54EFq0Lap8bfpX73IIW7j?= =?us-ascii?Q?WL/Hk7uDEXyUXcYXx/O0rKm/splqG77Q/LDPs0VnMpYUDHqRv3PeZXZQa08Z?= =?us-ascii?Q?AUeo8WRwk4fzeVdts1C6o5H5a3Jxgq93RzV2JUCTTxMo4n00p+vfRuubdcRs?= =?us-ascii?Q?YYF3UhYU1USu/yRafDs53Nv7DHVOinfmz85xKz9W9BI54KJBbT1RhpTDiWjY?= =?us-ascii?Q?Swj8fBdKs1wJKqypL9XYzR4BkI6mnRqot3lJ75g=3D=3D?= X-Forefront-PRVS: 031257FE13 X-Microsoft-Exchange-Diagnostics: =?us-ascii?Q?1; BLUPR03MB168; 23:op359Uxe10b+21/QstMEkvdZoBUb/POcpXxYCpWfKv?= =?us-ascii?Q?x9ka7nf6ti0P3TDz5wegOX3JV6penaCmrNOW/exzXkHZTbj7lO2IdnaFEX0u?= =?us-ascii?Q?n9ASeI12v2RrdoIDFDk+jcRt0u4h7bqO5ZhdA7GbnAokYgSfKCBweZf9eev4?= =?us-ascii?Q?KT5roa9QF8ipy8JFZWt4KM/GZgPBAqZ7WJ52VXobLNuVuCtRsqtMpWrG/J8R?= =?us-ascii?Q?6qYnx9do7QrVMPn+xUiD0fYdigEJitQJWXIT1YiNne5SZ7IMyi5XOcpZN1jI?= =?us-ascii?Q?43xAh99ROWlvV5ebQx4vNaDVmW8MXfhVio3oh4UmK+W9tWiP4IANz/DTR/rZ?= =?us-ascii?Q?xoqLQlQdTXxVvfkBJmFQR6iOFoh+ePb+QPOZfjtyYytBMdkrvLyYq11mELMd?= =?us-ascii?Q?frXp0TuaTcVcrpJJOaWNYPiZ++lD2dLr87hNYRihd6mPuxs7Qq0UTKNr8eXB?= =?us-ascii?Q?wD2sZycbtKxb9Siq6TIABEyEitN0q1yLI6enustoEHBRSzlGbnRyQkIq4Czk?= =?us-ascii?Q?9sxk0DfaMPjuGdlb9+pDAavSCsiTnszG2t9ON7ij1j0VM2chWdwwTubkJBWz?= =?us-ascii?Q?20WRhErZTWj5OTLOj6VtrDHqUgKuJcLlFx0OU53fpP91a8Dy/ftxMDrjkpWx?= =?us-ascii?Q?o3BGMO3/QUE2rK2gzfAg+BRaK3jTwbZCRTLFIpthh6VA8Thc+gNyAstyFOJU?= =?us-ascii?Q?KdgVjyyS8cfmhL7gGJy+NPiQW8NNsuQZqC1C7raYq3MSQ1jIsx0jobsAp6BM?= =?us-ascii?Q?hbO0kS3YWXxnm3K51vmpRjXUOvW4pLc6eDuaIPcfR7vzPwRFmIPhHlrpiAcu?= =?us-ascii?Q?/EugX7MRx8wLNaf8UGz4z12CUerYjVAlJlpXdjVfqkJUX0DohZFlCd/FBpUe?= =?us-ascii?Q?gTQk3R3s7pspUiI/E1Ac+ATQ0RMk1GQtfksQLPOYfuMNvS+gYUJqs4zs8DJ/?= =?us-ascii?Q?I8x2Mw2RMC7H/KGmVFo46DnVZy9IcT3S0NY0d2IUVUxB3HdcoPslYkNbS4BT?= =?us-ascii?Q?3ycxJon5iiM/P5GXjS6z7Q2ALwVLZNRaVzyrotNRRTVtyuOOgUADhRiaj44+?= =?us-ascii?Q?gZIGipMWvjX6ec/G9lD9J9npv1S1fUKDdR8ALguIVjHseld9BUWrJZ9JPzLX?= =?us-ascii?Q?Jv5zWVo+5IUW7CAd9A87tu9LLg96uUTwzzVfWvvX1+a/SKTEv/HrFREW/JpY?= =?us-ascii?Q?Tn4NIy7p6q31FMH/p2Brme0n/Mhcl2ZW9VP38vY1yWbpkpKEZj5e2NMxxXWL?= =?us-ascii?Q?rx9CKoGwmzkx3Y+9QCRiXA3tTBlzg2Be3BctgDZvdLTIt17MkVgpBXO8lMRA?= =?us-ascii?Q?=3D=3D?= X-Microsoft-Exchange-Diagnostics: 1; BLUPR03MB168; 6:+YQivuBS+iYZsLokSI3PFqxJ5hWrtRszW43DKZex05VPSdE71oiVUP71jj60kLCm/Vx7rB1BHL5NT1mxzbelw0xbaRGbQqaM4EEcm99zFowMdQ16V9iZ2NMja6zryL4vAK6HT/VzEBVHydJFAF/hMb2/yb4jpURGPcFhfGIEZ86Nz49uXS832DS6VGVrHL+3PrWCHgINH7LKnOlfcof5p9RSHoGuLOQS+UKzLSdX9whNmw+pJbrITCTl6Ma6RKikw/19UdjdSVa2UlwiGSkStVM/4WAbkK5pqM75aEBg/SYDxzUbeuiw1Ddld4jP6u1YIjDvnc/RnjBFNNeKmEn/kADj2nGKXrQO3heAbo//wW5Dqti3vCRhMBPyyTAL068OE+rk6YTKqtPBh2T+t/4rW9J928tr13u73cMchUxhTea+FaIUqFkNSgSblTPb4zyJ1qOzmNQ3T5WFbwNO/PKjZfoO79mbtcB5iraTEXCO+Gs2aQ4fWVurvp4utLl5suJbM6ZSsry4pdkCCippvyvDLw==; 5:mSrGR+gbzxsfRz9q8Pgg/goZ5FDC9b7kX3nSF5+hj7revwcvU2kWLRWnv8hFampkPz1fUzzpkptggwBBqwpoUnuOu7GGsXcZ9Xe1FVhAQdIaLNWbzXJtDA4pMNNnTw0Xjb+XqjRyNTkK+5btC12YJ3992WgaPU9o0MJrFoFENwh7hLXkTUK8A+rDw6KNuUCq; 24:Ob3x3RwuXckeI/yOMiRWUUGzOqPkA4ajoMCjLcmJs76bXeoTzrvAlHnwyZ+R9W5rMtjiNROpgWAIcHPBzqpdoEXidwD73W4RAb5xJb4MjGg= SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-Microsoft-Exchange-Diagnostics: 1; BLUPR03MB168; 7:4IirjKI8YFoHqNtlTH/drdV3cehjS8tk52yOdUETAqYIvcQvRoYqyOuPHd3WED3WUIqyYlj4IxuRXE0eKaT6ZJzlGSl4EvDkpilEaqWaniVJfCAtdtNCTzKLAijLTT2AIiC6QuO0G7GWEkZdI/p9/dW2DEpKT5l8AxjuU40DYVBsTRUKY/Pc4YF1ei2lWTJIFgXoEWl0pyhqplxJUfsojNPpgS43e+8XoiiRfEW/lfOQLKTmNF6jUAEJHeQdT5f3P2CIhEUUZkjwyOd/2vpRGiHEoOy8m5F3QtZ18L/BQDw7exWPS8wKVd1HmsRXkWeRP9ZZTo4a8ZUIlKce3cYQcQ== X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 May 2017 07:05:48.7766 (UTC) X-MS-Exchange-CrossTenant-Id: 5afe0b00-7697-4969-b663-5eab37d5f47e X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=5afe0b00-7697-4969-b663-5eab37d5f47e; Ip=[192.88.158.2]; Helo=[az84smr01.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BLUPR03MB168 Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org The design is based on the exist architecture that the core will provide a uniformed way to decode the generic pin config into platform config register raw data according to the imx_cfg_params_decode maps registered by platform. Two useful macros, IMX_CFG_PARAMS_DECODE and IMX_CFG_PARAMS_DECODE_INVERT, are created for platform to register decode map conveniently. In order to cope with some special case, a platform specific fixup() function is also available to use. Note that rather than fully utilizing the generic pinconf support provided by pinctrl core, IMX only adopts the device tree bindings of generic pinconf. The config used in .pin_config_get[set] are raw register data instead of generic one which makes us align the exist using. And that's also why we cannot set pinconf_ops.is_generic. Cc: Linus Walleij Cc: Shawn Guo Cc: Bai Ping Signed-off-by: Dong Aisheng Acked-by: Shawn Guo --- ChangeLog: v1->v2: Minor changes including: * rename 'offset' field to 'shift' in structure imx_cfg_params_decode * comments improvement * add more clearer information about imx generic pin config in commmit message. --- drivers/pinctrl/freescale/Kconfig | 2 +- drivers/pinctrl/freescale/pinctrl-imx.c | 108 +++++++++++++++++++++++++++++--- drivers/pinctrl/freescale/pinctrl-imx.h | 25 ++++++++ 3 files changed, 124 insertions(+), 11 deletions(-) diff --git a/drivers/pinctrl/freescale/Kconfig b/drivers/pinctrl/freescale/Kconfig index cae05e7..0b266b2 100644 --- a/drivers/pinctrl/freescale/Kconfig +++ b/drivers/pinctrl/freescale/Kconfig @@ -2,7 +2,7 @@ config PINCTRL_IMX bool select GENERIC_PINCTRL_GROUPS select GENERIC_PINMUX_FUNCTIONS - select PINCONF + select GENERIC_PINCONF select REGMAP config PINCTRL_IMX1_CORE diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c b/drivers/pinctrl/freescale/pinctrl-imx.c index 6882644..6d5a517 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx.c +++ b/drivers/pinctrl/freescale/pinctrl-imx.c @@ -27,6 +27,7 @@ #include #include "../core.h" +#include "../pinconf.h" #include "../pinmux.h" #include "pinctrl-imx.h" @@ -361,6 +362,62 @@ static const struct pinmux_ops imx_pmx_ops = { .gpio_set_direction = imx_pmx_gpio_set_direction, }; +/* decode generic config into raw register values */ +static u32 imx_pinconf_decode_generic_config(struct imx_pinctrl *ipctl, + unsigned long *configs, + unsigned int num_configs) +{ + struct imx_pinctrl_soc_info *info = ipctl->info; + struct imx_cfg_params_decode *decode; + enum pin_config_param param; + u32 raw_config = 0; + u32 param_val; + int i, j; + + WARN_ON(num_configs > info->num_decodes); + + for (i = 0; i < num_configs; i++) { + param = pinconf_to_config_param(configs[i]); + param_val = pinconf_to_config_argument(configs[i]); + decode = info->decodes; + for (j = 0; j < info->num_decodes; j++) { + if (param == decode->param) { + if (decode->invert) + param_val = !param_val; + raw_config |= (param_val << decode->shift) + & decode->mask; + break; + } + decode++; + } + } + + if (info->fixup) + info->fixup(configs, num_configs, &raw_config); + + return raw_config; +} + +static u32 imx_pinconf_parse_generic_config(struct device_node *np, + struct imx_pinctrl *ipctl) +{ + struct imx_pinctrl_soc_info *info = ipctl->info; + struct pinctrl_dev *pctl = ipctl->pctl; + unsigned int num_configs; + unsigned long *configs; + int ret; + + if (!info->generic_pinconf) + return 0; + + ret = pinconf_generic_parse_dt_config(np, pctl, &configs, + &num_configs); + if (ret) + return 0; + + return imx_pinconf_decode_generic_config(ipctl, configs, num_configs); +} + static int imx_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin_id, unsigned long *config) { @@ -479,9 +536,10 @@ static const struct pinconf_ops imx_pinconf_ops = { static int imx_pinctrl_parse_groups(struct device_node *np, struct group_desc *grp, - struct imx_pinctrl_soc_info *info, + struct imx_pinctrl *ipctl, u32 index) { + struct imx_pinctrl_soc_info *info = ipctl->info; int size, pin_size; const __be32 *list; int i; @@ -493,25 +551,44 @@ static int imx_pinctrl_parse_groups(struct device_node *np, pin_size = SHARE_FSL_PIN_SIZE; else pin_size = FSL_PIN_SIZE; + + if (info->generic_pinconf) + pin_size -= 4; + /* Initialise group */ grp->name = np->name; /* * the binding format is fsl,pins = , * do sanity check and calculate pins number + * + * First try legacy 'fsl,pins' property, then fall back to the + * generic 'pins'. + * + * Note: for generic 'pins' case, there's no CONFIG part in + * the binding format. */ list = of_get_property(np, "fsl,pins", &size); if (!list) { - dev_err(info->dev, "no fsl,pins property in node %s\n", np->full_name); - return -EINVAL; + list = of_get_property(np, "pins", &size); + if (!list) { + dev_err(info->dev, + "no fsl,pins and pins property in node %s\n", + np->full_name); + return -EINVAL; + } } /* we do not check return since it's safe node passed down */ if (!size || size % pin_size) { - dev_err(info->dev, "Invalid fsl,pins property in node %s\n", np->full_name); + dev_err(info->dev, "Invalid fsl,pins or pins property in node %s\n", + np->full_name); return -EINVAL; } + /* first try to parse the generic pin config */ + config = imx_pinconf_parse_generic_config(np, ipctl); + grp->num_pins = size / pin_size; grp->data = devm_kzalloc(info->dev, grp->num_pins * sizeof(struct imx_pin), GFP_KERNEL); @@ -548,11 +625,18 @@ static int imx_pinctrl_parse_groups(struct device_node *np, pin->mux_mode = be32_to_cpu(*list++); pin->input_val = be32_to_cpu(*list++); - /* SION bit is in mux register */ - config = be32_to_cpu(*list++); - if (config & IMX_PAD_SION) - pin->mux_mode |= IOMUXC_CONFIG_SION; - pin->config = config & ~IMX_PAD_SION; + if (info->generic_pinconf) { + /* generic pin config decoded */ + pin->config = config; + } else { + /* legacy pin config read from devicetree */ + config = be32_to_cpu(*list++); + + /* SION bit is in mux register */ + if (config & IMX_PAD_SION) + pin->mux_mode |= IOMUXC_CONFIG_SION; + pin->config = config & ~IMX_PAD_SION; + } dev_dbg(info->dev, "%s: 0x%x 0x%08lx", info->pins[pin_id].name, pin->mux_mode, pin->config); @@ -602,7 +686,7 @@ static int imx_pinctrl_parse_functions(struct device_node *np, info->group_index++, grp); mutex_unlock(&info->mutex); - imx_pinctrl_parse_groups(child, grp, info, i++); + imx_pinctrl_parse_groups(child, grp, ipctl, i++); } return 0; @@ -773,6 +857,10 @@ int imx_pinctrl_probe(struct platform_device *pdev, imx_pinctrl_desc->confops = &imx_pinconf_ops; imx_pinctrl_desc->owner = THIS_MODULE; + /* for generic pinconf */ + imx_pinctrl_desc->custom_params = info->custom_params; + imx_pinctrl_desc->num_custom_params = info->num_custom_params; + mutex_init(&info->mutex); ipctl->info = info; diff --git a/drivers/pinctrl/freescale/pinctrl-imx.h b/drivers/pinctrl/freescale/pinctrl-imx.h index ff2d3e5..38aa53c 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx.h +++ b/drivers/pinctrl/freescale/pinctrl-imx.h @@ -15,6 +15,8 @@ #ifndef __DRIVERS_PINCTRL_IMX_H #define __DRIVERS_PINCTRL_IMX_H +#include + struct platform_device; /** @@ -44,6 +46,14 @@ struct imx_pin_reg { s16 conf_reg; }; +/* decode a generic config into raw register value */ +struct imx_cfg_params_decode { + enum pin_config_param param; + u32 mask; + u8 shift; + bool invert; +}; + struct imx_pinctrl_soc_info { struct device *dev; const struct pinctrl_pin_desc *pins; @@ -53,8 +63,23 @@ struct imx_pinctrl_soc_info { unsigned int flags; const char *gpr_compatible; struct mutex mutex; + + /* generic pinconf */ + bool generic_pinconf; + const struct pinconf_generic_params *custom_params; + unsigned int num_custom_params; + struct imx_cfg_params_decode *decodes; + unsigned int num_decodes; + void (*fixup)(unsigned long *configs, unsigned int num_configs, + u32 *raw_config); }; +#define IMX_CFG_PARAMS_DECODE(p, m, o) \ + { .param = p, .mask = m, .shift = o, .invert = false, } + +#define IMX_CFG_PARAMS_DECODE_INVERT(p, m, o) \ + { .param = p, .mask = m, .shift = o, .invert = true, } + #define SHARE_MUX_CONF_REG 0x1 #define ZERO_OFFSET_VALID 0x2