From patchwork Wed Dec 22 11:54:55 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aneesh V X-Patchwork-Id: 76393 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 3C450B7063 for ; Wed, 22 Dec 2010 22:56:55 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id E36062812A; Wed, 22 Dec 2010 12:56:15 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Ntw5dKbSPAqe; Wed, 22 Dec 2010 12:56:15 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 10EBD280E2; Wed, 22 Dec 2010 12:55:39 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 93B39280E8 for ; Wed, 22 Dec 2010 12:55:30 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id YinAnEJmtfHB for ; Wed, 22 Dec 2010 12:55:29 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from comal.ext.ti.com (comal.ext.ti.com [198.47.26.152]) by theia.denx.de (Postfix) with ESMTPS id 03230280EF for ; Wed, 22 Dec 2010 12:55:23 +0100 (CET) Received: from dbdp31.itg.ti.com ([172.24.170.98]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id oBMBtIEK027656 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Wed, 22 Dec 2010 05:55:20 -0600 Received: from localhost (localhost [127.0.0.1]) by dbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id oBMBtIH2016326; Wed, 22 Dec 2010 17:25:18 +0530 (IST) From: Aneesh V To: u-boot@lists.denx.de Date: Wed, 22 Dec 2010 17:24:55 +0530 Message-Id: <1293018898-13253-6-git-send-email-aneesh@ti.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1293018898-13253-1-git-send-email-aneesh@ti.com> References: <1293018898-13253-1-git-send-email-aneesh@ti.com> Cc: loic.minier@linaro.org, paul.mckenney@linaro.org, steve@sakoman.com Subject: [U-Boot] [PATCH 5/8] armv7: add PL310 support to u-boot X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.9 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Add support for some of the key maintenance operations - Invalidate all - Invalidate range - Flush(clean & invalidate) all - Flush range Signed-off-by: Aneesh V --- arch/arm/include/asm/pl310.h | 49 ++++++++++++++++++ arch/arm/lib/Makefile | 1 + arch/arm/lib/cache-pl310.c | 114 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 164 insertions(+), 0 deletions(-) create mode 100644 arch/arm/include/asm/pl310.h create mode 100644 arch/arm/lib/cache-pl310.c diff --git a/arch/arm/include/asm/pl310.h b/arch/arm/include/asm/pl310.h new file mode 100644 index 0000000..8f5b33e --- /dev/null +++ b/arch/arm/include/asm/pl310.h @@ -0,0 +1,49 @@ +/* + * (C) Copyright 2010 + * Texas Instruments Incorporated - http://www.ti.com/ + * + * Aneesh V + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef PL310_H +#define PL310_H + +#include + +/* Register offsets */ +#define PL310_CACHE_TYPE 0x004 +#define PL310_AUX_CTRL 0x104 + +#define PL310_CACHE_SYNC 0x730 +#define PL310_INVAL_LINE_PA 0x770 +#define PL310_INVAL_WAY 0x77C +#define PL310_CLEAN_LINE_PA 0x7B0 +#define PL310_CLEAN_INVAL_WAY 0x7FC +#define PL310_CLEAN_INVAL_LINE_PA 0x7F0 + +/* Register bit fields */ +#define PL310_AUX_CTRL_ASSOCIATIVITY_MASK (1 << 16) + +void pl310_inval_all(void); +void pl310_clean_inval_all(void); +void pl310_inval_range(u32 start, u32 end); +void pl310_clean_inval_range(u32 start, u32 end); + +#endif diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile index 454440c..dc108a6 100644 --- a/arch/arm/lib/Makefile +++ b/arch/arm/lib/Makefile @@ -42,6 +42,7 @@ COBJS-y += cache.o ifndef CONFIG_SYS_NO_CP15_CACHE COBJS-y += cache-cp15.o endif +COBJS-$(CONFIG_SYS_USE_PL310) += cache-pl310.o COBJS-y += interrupts.o COBJS-y += reset.o diff --git a/arch/arm/lib/cache-pl310.c b/arch/arm/lib/cache-pl310.c new file mode 100644 index 0000000..4f062f8 --- /dev/null +++ b/arch/arm/lib/cache-pl310.c @@ -0,0 +1,114 @@ +/* + * (C) Copyright 2010 + * Texas Instruments Incorporated - http://www.ti.com/ + * + * Aneesh V + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include +#include +#include +#include +#include + +static void pl310_cache_sync(void) +{ + __raw_writel(0, CONFIG_SYS_PL310_BASE + PL310_CACHE_SYNC); +} + +static void pl310_background_op_all_ways(u32 op_reg_offset) +{ + u32 assoc_16, associativity, way_mask; + assoc_16 = __raw_readl(CONFIG_SYS_PL310_BASE + PL310_AUX_CTRL) & + PL310_AUX_CTRL_ASSOCIATIVITY_MASK; + + if (assoc_16) + associativity = 16; + else + associativity = 8; + + way_mask = (1 << associativity) - 1; + /* Invalidate all ways */ + __raw_writel(way_mask, CONFIG_SYS_PL310_BASE + op_reg_offset); + /* Wait for all ways to be invalidated */ + while (__raw_readl(CONFIG_SYS_PL310_BASE + op_reg_offset) && way_mask) + ; + pl310_cache_sync(); +} + +void pl310_inval_all(void) +{ + pl310_background_op_all_ways(PL310_INVAL_WAY); +} + +void pl310_clean_inval_all(void) +{ + pl310_background_op_all_ways(PL310_CLEAN_INVAL_WAY); +} + +/* Flush(clean invalidate) memory from start to stop-1 */ +void pl310_clean_inval_range(u32 start, u32 stop) +{ + /* PL310 currently supports only 32 bytes cache line */ + u32 pa, line_size = 32; + + /* + * Align to the beginning of cache-line - this ensures that + * the first 5 bits are 0 as required by PL310 TRM + */ + start &= ~(line_size - 1); + + for (pa = start; pa < stop; pa = pa + line_size) + __raw_writel(pa, CONFIG_SYS_PL310_BASE + + PL310_CLEAN_INVAL_LINE_PA); + pl310_cache_sync(); +} + +/* invalidate memory from start to stop-1 */ +void pl310_inval_range(u32 start, u32 stop) +{ + /* PL310 currently supports only 32 bytes cache line */ + u32 pa, line_size = 32; + + /* + * If start address is not aligned to cache-line flush the first + * line to prevent affecting somebody else's buffer + */ + if (start & (line_size - 1)) { + pl310_clean_inval_range(start, start + 1); + /* move to next cache line */ + start = (start + line_size - 1) & ~(line_size - 1); + } + + /* + * If stop address is not aligned to cache-line flush the last + * line to prevent affecting somebody else's buffer + */ + if (stop & (line_size - 1)) { + pl310_clean_inval_range(stop, stop + 1); + /* align to the beginning of this cache line */ + stop &= ~(line_size - 1); + } + + for (pa = start; pa < stop; pa = pa + line_size) + __raw_writel(pa, CONFIG_SYS_PL310_BASE + + PL310_INVAL_LINE_PA); + pl310_cache_sync(); +}