Patchwork [U-Boot,5/8] armv7: add PL310 support to u-boot

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Submitter Aneesh V
Date Dec. 22, 2010, 11:54 a.m.
Message ID <1293018898-13253-6-git-send-email-aneesh@ti.com>
Download mbox | patch
Permalink /patch/76393/
State Changes Requested
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Comments

Aneesh V - Dec. 22, 2010, 11:54 a.m.
Add support for some of the key maintenance operations
	- Invalidate all
	- Invalidate range
	- Flush(clean & invalidate) all
	- Flush range

Signed-off-by: Aneesh V <aneesh@ti.com>
---
 arch/arm/include/asm/pl310.h |   49 ++++++++++++++++++
 arch/arm/lib/Makefile        |    1 +
 arch/arm/lib/cache-pl310.c   |  114 ++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 164 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/include/asm/pl310.h
 create mode 100644 arch/arm/lib/cache-pl310.c
Wolfgang Denk - Jan. 9, 2011, 10:48 p.m.
Dear Aneesh V,

In message <1293018898-13253-6-git-send-email-aneesh@ti.com> you wrote:
> Add support for some of the key maintenance operations
> 	- Invalidate all
> 	- Invalidate range
> 	- Flush(clean & invalidate) all
> 	- Flush range

Can you please use a more descriptive subject, and commit message?

I have no idea what a "PL310" might be - is this a new board? Or a new
SoC? or a new Ethernet controller?


And what exactly are "key maintenance operations"?  Looks as if you
were talking about basic cache operations?

> --- /dev/null
> +++ b/arch/arm/include/asm/pl310.h
...
> +/* Register offsets */
> +#define PL310_CACHE_TYPE		0x004
> +#define PL310_AUX_CTRL			0x104
> +
> +#define PL310_CACHE_SYNC		0x730
> +#define PL310_INVAL_LINE_PA		0x770
> +#define PL310_INVAL_WAY			0x77C
> +#define PL310_CLEAN_LINE_PA		0x7B0
> +#define PL310_CLEAN_INVAL_WAY		0x7FC
> +#define PL310_CLEAN_INVAL_LINE_PA	0x7F0

NAK.  Please use a C struct instead.


> --- a/arch/arm/lib/Makefile
> +++ b/arch/arm/lib/Makefile
> @@ -42,6 +42,7 @@ COBJS-y	+= cache.o
>  ifndef CONFIG_SYS_NO_CP15_CACHE
>  COBJS-y	+= cache-cp15.o
>  endif
> +COBJS-$(CONFIG_SYS_USE_PL310) += cache-pl310.o
>  COBJS-y	+= interrupts.o
>  COBJS-y	+= reset.o

There is no documentation for CONFIG_SYS_USE_PL310, and there is no
use of this variable.

Also, it seems CONFIG_SYS_PL310 would be more appropriate.

...
> +static void pl310_cache_sync(void)
> +{
> +	__raw_writel(0, CONFIG_SYS_PL310_BASE + PL310_CACHE_SYNC);
> +}

Please use a proper C struct instead of base address plus offset.
Please fix globally.

...
> +	for (pa = start; pa < stop; pa = pa + line_size)
> +		__raw_writel(pa, CONFIG_SYS_PL310_BASE +
> +			     PL310_CLEAN_INVAL_LINE_PA);

Please use braces for multiline statements.


Best regards,

Wolfgang Denk
Aneesh V - Jan. 10, 2011, 1:41 p.m.
Dear Wolfgang,

On Monday 10 January 2011 04:18 AM, Wolfgang Denk wrote:
> Dear Aneesh V,
>
> In message<1293018898-13253-6-git-send-email-aneesh@ti.com>  you wrote:
>> Add support for some of the key maintenance operations
>> 	- Invalidate all
>> 	- Invalidate range
>> 	- Flush(clean&  invalidate) all
>> 	- Flush range
>
> Can you please use a more descriptive subject, and commit message?
>
> I have no idea what a "PL310" might be - is this a new board? Or a new
> SoC? or a new Ethernet controller?

Sure. I will add a more descriptive message.
PL310 is an L2 cache controller from ARM.

>
>
> And what exactly are "key maintenance operations"?  Looks as if you
> were talking about basic cache operations?

Yes. I was talking about basic cache operations. In ARM terminology the
cache operations are called "cache maintenance operations".

>
>> --- /dev/null
>> +++ b/arch/arm/include/asm/pl310.h
> ...
>> +/* Register offsets */
>> +#define PL310_CACHE_TYPE		0x004
>> +#define PL310_AUX_CTRL			0x104
>> +
>> +#define PL310_CACHE_SYNC		0x730
>> +#define PL310_INVAL_LINE_PA		0x770
>> +#define PL310_INVAL_WAY			0x77C
>> +#define PL310_CLEAN_LINE_PA		0x7B0
>> +#define PL310_CLEAN_INVAL_WAY		0x7FC
>> +#define PL310_CLEAN_INVAL_LINE_PA	0x7F0
>
> NAK.  Please use a C struct instead.

Ok.

>
>
>> --- a/arch/arm/lib/Makefile
>> +++ b/arch/arm/lib/Makefile
>> @@ -42,6 +42,7 @@ COBJS-y	+= cache.o
>>   ifndef CONFIG_SYS_NO_CP15_CACHE
>>   COBJS-y	+= cache-cp15.o
>>   endif
>> +COBJS-$(CONFIG_SYS_USE_PL310) += cache-pl310.o
>>   COBJS-y	+= interrupts.o
>>   COBJS-y	+= reset.o
>
> There is no documentation for CONFIG_SYS_USE_PL310, and there is no
> use of this variable.
>
> Also, it seems CONFIG_SYS_PL310 would be more appropriate.

I shall make it CONFIG_SYS_PL310 and add documentation.

>
> ...
>> +static void pl310_cache_sync(void)
>> +{
>> +	__raw_writel(0, CONFIG_SYS_PL310_BASE + PL310_CACHE_SYNC);
>> +}
>
> Please use a proper C struct instead of base address plus offset.
> Please fix globally.
>
> ...
>> +	for (pa = start; pa<  stop; pa = pa + line_size)
>> +		__raw_writel(pa, CONFIG_SYS_PL310_BASE +
>> +			     PL310_CLEAN_INVAL_LINE_PA);
>
> Please use braces for multiline statements.

ok.

>
>
> Best regards,
>
> Wolfgang Denk
>

Best regards,
Aneesh

Patch

diff --git a/arch/arm/include/asm/pl310.h b/arch/arm/include/asm/pl310.h
new file mode 100644
index 0000000..8f5b33e
--- /dev/null
+++ b/arch/arm/include/asm/pl310.h
@@ -0,0 +1,49 @@ 
+/*
+ * (C) Copyright 2010
+ * Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Aneesh V <aneesh@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef PL310_H
+#define PL310_H
+
+#include <linux/types.h>
+
+/* Register offsets */
+#define PL310_CACHE_TYPE		0x004
+#define PL310_AUX_CTRL			0x104
+
+#define PL310_CACHE_SYNC		0x730
+#define PL310_INVAL_LINE_PA		0x770
+#define PL310_INVAL_WAY			0x77C
+#define PL310_CLEAN_LINE_PA		0x7B0
+#define PL310_CLEAN_INVAL_WAY		0x7FC
+#define PL310_CLEAN_INVAL_LINE_PA	0x7F0
+
+/* Register bit fields */
+#define PL310_AUX_CTRL_ASSOCIATIVITY_MASK	(1 << 16)
+
+void pl310_inval_all(void);
+void pl310_clean_inval_all(void);
+void pl310_inval_range(u32 start, u32 end);
+void pl310_clean_inval_range(u32 start, u32 end);
+
+#endif
diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
index 454440c..dc108a6 100644
--- a/arch/arm/lib/Makefile
+++ b/arch/arm/lib/Makefile
@@ -42,6 +42,7 @@  COBJS-y	+= cache.o
 ifndef CONFIG_SYS_NO_CP15_CACHE
 COBJS-y	+= cache-cp15.o
 endif
+COBJS-$(CONFIG_SYS_USE_PL310) += cache-pl310.o
 COBJS-y	+= interrupts.o
 COBJS-y	+= reset.o
 
diff --git a/arch/arm/lib/cache-pl310.c b/arch/arm/lib/cache-pl310.c
new file mode 100644
index 0000000..4f062f8
--- /dev/null
+++ b/arch/arm/lib/cache-pl310.c
@@ -0,0 +1,114 @@ 
+/*
+ * (C) Copyright 2010
+ * Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Aneesh V <aneesh@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <linux/types.h>
+#include <asm/io.h>
+#include <asm/armv7.h>
+#include <asm/pl310.h>
+#include <config.h>
+
+static void pl310_cache_sync(void)
+{
+	__raw_writel(0, CONFIG_SYS_PL310_BASE + PL310_CACHE_SYNC);
+}
+
+static void pl310_background_op_all_ways(u32 op_reg_offset)
+{
+	u32 assoc_16, associativity, way_mask;
+	assoc_16 = __raw_readl(CONFIG_SYS_PL310_BASE + PL310_AUX_CTRL) &
+		   PL310_AUX_CTRL_ASSOCIATIVITY_MASK;
+
+	if (assoc_16)
+		associativity = 16;
+	else
+		associativity = 8;
+
+	way_mask = (1 << associativity) - 1;
+	/* Invalidate all ways */
+	__raw_writel(way_mask, CONFIG_SYS_PL310_BASE + op_reg_offset);
+	/* Wait for all ways to be invalidated */
+	while (__raw_readl(CONFIG_SYS_PL310_BASE + op_reg_offset) && way_mask)
+		;
+	pl310_cache_sync();
+}
+
+void pl310_inval_all(void)
+{
+	pl310_background_op_all_ways(PL310_INVAL_WAY);
+}
+
+void pl310_clean_inval_all(void)
+{
+	pl310_background_op_all_ways(PL310_CLEAN_INVAL_WAY);
+}
+
+/* Flush(clean invalidate) memory from start to stop-1 */
+void pl310_clean_inval_range(u32 start, u32 stop)
+{
+	/* PL310 currently supports only 32 bytes cache line */
+	u32 pa, line_size = 32;
+
+	/*
+	 * Align to the beginning of cache-line - this ensures that
+	 * the first 5 bits are 0 as required by PL310 TRM
+	 */
+	start &= ~(line_size - 1);
+
+	for (pa = start; pa < stop; pa = pa + line_size)
+		__raw_writel(pa, CONFIG_SYS_PL310_BASE +
+			     PL310_CLEAN_INVAL_LINE_PA);
+	pl310_cache_sync();
+}
+
+/* invalidate memory from start to stop-1 */
+void pl310_inval_range(u32 start, u32 stop)
+{
+	/* PL310 currently supports only 32 bytes cache line */
+	u32 pa, line_size = 32;
+
+	/*
+	 * If start address is not aligned to cache-line flush the first
+	 * line to prevent affecting somebody else's buffer
+	 */
+	if (start & (line_size - 1)) {
+		pl310_clean_inval_range(start, start + 1);
+		/* move to next cache line */
+		start = (start + line_size - 1) & ~(line_size - 1);
+	}
+
+	/*
+	 * If stop address is not aligned to cache-line flush the last
+	 * line to prevent affecting somebody else's buffer
+	 */
+	if (stop & (line_size - 1)) {
+		pl310_clean_inval_range(stop, stop + 1);
+		/* align to the beginning of this cache line */
+		stop &= ~(line_size - 1);
+	}
+
+	for (pa = start; pa < stop; pa = pa + line_size)
+		__raw_writel(pa, CONFIG_SYS_PL310_BASE +
+			     PL310_INVAL_LINE_PA);
+	pl310_cache_sync();
+}