Patchwork [U-Boot,8/8] armv7: adapt s5pc1xx to the new cache maintenance framework

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Submitter Aneesh V
Date Dec. 22, 2010, 11:54 a.m.
Message ID <1293018898-13253-9-git-send-email-aneesh@ti.com>
Download mbox | patch
Permalink /patch/76389/
State Changes Requested
Headers show

Comments

Aneesh V - Dec. 22, 2010, 11:54 a.m.
adapt s5pc1xx to the new layered cache maintenance framework

Signed-off-by: Aneesh V <aneesh@ti.com>
---
 arch/arm/cpu/armv7/s5pc1xx/cache.S            |   86 +-----------------------
 arch/arm/cpu/armv7/s5pc1xx/clock.c            |   12 ++++
 arch/arm/include/asm/arch-s5pc1xx/sys_proto.h |    4 +-
 3 files changed, 18 insertions(+), 84 deletions(-)
Minkyu Kang - Dec. 27, 2010, 7:25 a.m.
Dear Aneesh V,

On 22 December 2010 20:54, Aneesh V <aneesh@ti.com> wrote:
> adapt s5pc1xx to the new layered cache maintenance framework
>
> Signed-off-by: Aneesh V <aneesh@ti.com>
> ---
>  arch/arm/cpu/armv7/s5pc1xx/cache.S            |   86 +-----------------------
>  arch/arm/cpu/armv7/s5pc1xx/clock.c            |   12 ++++
>  arch/arm/include/asm/arch-s5pc1xx/sys_proto.h |    4 +-
>  3 files changed, 18 insertions(+), 84 deletions(-)
>
> diff --git a/arch/arm/cpu/armv7/s5pc1xx/clock.c b/arch/arm/cpu/armv7/s5pc1xx/clock.c
> index 98a27e5..da8b2d7 100644
> --- a/arch/arm/cpu/armv7/s5pc1xx/clock.c
> +++ b/arch/arm/cpu/armv7/s5pc1xx/clock.c
> @@ -26,6 +26,8 @@
>  #include <asm/io.h>
>  #include <asm/arch/clock.h>
>  #include <asm/arch/clk.h>
> +#include <asm/arch/sys_proto.h>
> +#include <asm/armv7.h>
>
>  #define CLK_M  0
>  #define CLK_D  1
> @@ -328,3 +330,13 @@ void s5p_clock_init(void)
>        get_uart_clk = s5pc1xx_get_uart_clk;
>        get_pwm_clk = s5pc1xx_get_pwm_clk;
>  }
> +
> +#ifndef CONFIG_SYS_NO_DCACHE
> +void v7_setup_outer_cache_ops(void)
> +{
> +#ifndef CONFIG_L2_OFF
> +       v7_outer_cache.enable = ca8_l2_cache_enable;
> +       v7_outer_cache.disable = ca8_l2_cache_disable;
> +#endif
> +}
> +#endif

I don't agree with add this function at clock.c.
If need we can make new file as omap3/4 case.

Thanks
Minkyu Kang
Aneesh V - Dec. 27, 2010, 11:22 a.m.
Dear Minkyu Kang,

On Monday 27 December 2010 12:55 PM, Minkyu Kang wrote:
< snip >
>> +
>> +#ifndef CONFIG_SYS_NO_DCACHE
>> +void v7_setup_outer_cache_ops(void)
>> +{
>> +#ifndef CONFIG_L2_OFF
>> +       v7_outer_cache.enable = ca8_l2_cache_enable;
>> +       v7_outer_cache.disable = ca8_l2_cache_disable;
>> +#endif
>> +}
>> +#endif
>
> I don't agree with add this function at clock.c.
> If need we can make new file as omap3/4 case.

I didn't want to add a new file just for this small function. But no
problem, I will do that in the next revision.

Best regards,
Aneesh
Minkyu Kang - Jan. 7, 2011, 5:27 a.m.
Dear Aneesh V,

On 27 December 2010 20:22, Aneesh V <aneesh@ti.com> wrote:
> Dear Minkyu Kang,
>
> On Monday 27 December 2010 12:55 PM, Minkyu Kang wrote:
> < snip >
>>>
>>> +
>>> +#ifndef CONFIG_SYS_NO_DCACHE
>>> +void v7_setup_outer_cache_ops(void)
>>> +{
>>> +#ifndef CONFIG_L2_OFF
>>> +       v7_outer_cache.enable = ca8_l2_cache_enable;
>>> +       v7_outer_cache.disable = ca8_l2_cache_disable;
>>> +#endif
>>> +}
>>> +#endif
>>
>> I don't agree with add this function at clock.c.
>> If need we can make new file as omap3/4 case.
>
> I didn't want to add a new file just for this small function. But no
> problem, I will do that in the next revision.
>

OK, please make soc.c.
I have plan to move reset.S to this file.

Thanks.
Minkyu Kang

Patch

diff --git a/arch/arm/cpu/armv7/s5pc1xx/cache.S b/arch/arm/cpu/armv7/s5pc1xx/cache.S
index 7734b32..e62ad75 100644
--- a/arch/arm/cpu/armv7/s5pc1xx/cache.S
+++ b/arch/arm/cpu/armv7/s5pc1xx/cache.S
@@ -23,96 +23,18 @@ 
  * MA 02111-1307 USA
  */
 
-#include <asm/arch/cpu.h>
-
 .align 5
-.global invalidate_dcache
-.global l2_cache_enable
-.global l2_cache_disable
-
-/*
- * invalidate_dcache()
- * Invalidate the whole D-cache.
- *
- * Corrupted registers: r0-r5, r7, r9-r11
- */
-invalidate_dcache:
-	stmfd	r13!, {r0 - r5, r7, r9 - r12, r14}
-
-	cmp	r0, #0xC100			@ check if the cpu is s5pc100
-
-	beq	finished_inval			@ s5pc100 doesn't need this
-						@ routine
-	mrc	p15, 1, r0, c0, c0, 1		@ read clidr
-	ands	r3, r0, #0x7000000		@ extract loc from clidr
-	mov	r3, r3, lsr #23			@ left align loc bit field
-	beq	finished_inval			@ if loc is 0, then no need to
-						@ clean
-	mov	r10, #0				@ start clean at cache level 0
-inval_loop1:
-	add	r2, r10, r10, lsr #1		@ work out 3x current cache
-						@ level
-	mov	r1, r0, lsr r2			@ extract cache type bits from
-						@ clidr
-	and	r1, r1, #7			@ mask of the bits for current
-						@ cache only
-	cmp	r1, #2				@ see what cache we have at
-						@ this level
-	blt	skip_inval			@ skip if no cache, or just
-						@ i-cache
-	mcr	p15, 2, r10, c0, c0, 0		@ select current cache level
-						@ in cssr
-	mov	r2, #0				@ operand for mcr SBZ
-	mcr	p15, 0, r2, c7, c5, 4		@ flush prefetch buffer to
-						@ sych the new cssr&csidr,
-						@ with armv7 this is 'isb',
-						@ but we compile with armv5
-	mrc	p15, 1, r1, c0, c0, 0		@ read the new csidr
-	and	r2, r1, #7			@ extract the length of the
-						@ cache lines
-	add	r2, r2, #4			@ add 4 (line length offset)
-	ldr	r4, =0x3ff
-	ands	r4, r4, r1, lsr #3		@ find maximum number on the
-						@ way size
-	clz	r5, r4				@ find bit position of way
-						@ size increment
-	ldr	r7, =0x7fff
-	ands	r7, r7, r1, lsr #13		@ extract max number of the
-						@ index size
-inval_loop2:
-	mov	r9, r4				@ create working copy of max
-						@ way size
-inval_loop3:
-	orr	r11, r10, r9, lsl r5		@ factor way and cache number
-						@ into r11
-	orr	r11, r11, r7, lsl r2		@ factor index number into r11
-	mcr	p15, 0, r11, c7, c6, 2		@ invalidate by set/way
-	subs	r9, r9, #1			@ decrement the way
-	bge	inval_loop3
-	subs	r7, r7, #1			@ decrement the index
-	bge	inval_loop2
-skip_inval:
-	add	r10, r10, #2			@ increment cache number
-	cmp	r3, r10
-	bgt	inval_loop1
-finished_inval:
-	mov	r10, #0				@ swith back to cache level 0
-	mcr	p15, 2, r10, c0, c0, 0		@ select current cache level
-						@ in cssr
-	mcr	p15, 0, r10, c7, c5, 4		@ flush prefetch buffer,
-						@ with armv7 this is 'isb',
-						@ but we compile with armv5
-
-	ldmfd	r13!, {r0 - r5, r7, r9 - r12, pc}
+.global ca8_l2_cache_enable
+.global ca8_l2_cache_disable
 
-l2_cache_enable:
+ca8_l2_cache_enable:
 	push	{r0, r1, r2, lr}
 	mrc	15, 0, r3, cr1, cr0, 1
 	orr	r3, r3, #2
 	mcr	15, 0, r3, cr1, cr0, 1
 	pop	{r1, r2, r3, pc}
 
-l2_cache_disable:
+ca8_l2_cache_disable:
 	push	{r0, r1, r2, lr}
 	mrc	15, 0, r3, cr1, cr0, 1
 	bic	r3, r3, #2
diff --git a/arch/arm/cpu/armv7/s5pc1xx/clock.c b/arch/arm/cpu/armv7/s5pc1xx/clock.c
index 98a27e5..da8b2d7 100644
--- a/arch/arm/cpu/armv7/s5pc1xx/clock.c
+++ b/arch/arm/cpu/armv7/s5pc1xx/clock.c
@@ -26,6 +26,8 @@ 
 #include <asm/io.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/clk.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/armv7.h>
 
 #define CLK_M	0
 #define CLK_D	1
@@ -328,3 +330,13 @@  void s5p_clock_init(void)
 	get_uart_clk = s5pc1xx_get_uart_clk;
 	get_pwm_clk = s5pc1xx_get_pwm_clk;
 }
+
+#ifndef CONFIG_SYS_NO_DCACHE
+void v7_setup_outer_cache_ops(void)
+{
+#ifndef CONFIG_L2_OFF
+	v7_outer_cache.enable = ca8_l2_cache_enable;
+	v7_outer_cache.disable = ca8_l2_cache_disable;
+#endif
+}
+#endif
diff --git a/arch/arm/include/asm/arch-s5pc1xx/sys_proto.h b/arch/arm/include/asm/arch-s5pc1xx/sys_proto.h
index 3078aaf..23144da 100644
--- a/arch/arm/include/asm/arch-s5pc1xx/sys_proto.h
+++ b/arch/arm/include/asm/arch-s5pc1xx/sys_proto.h
@@ -26,7 +26,7 @@ 
 
 u32 get_device_type(void);
 void invalidate_dcache(u32);
-void l2_cache_disable(void);
-void l2_cache_enable(void);
+void ca8_l2_cache_disable(void);
+void ca8_l2_cache_enable(void);
 
 #endif