new file mode 100644
@@ -0,0 +1,154 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <dt-bindings/clock/bcm3380-clock.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/reset/bcm3380-reset.h>
+#include "skeleton.dtsi"
+
+/ {
+ compatible = "brcm,bcm3380";
+
+ cpus {
+ reg = <0x14e00000 0x4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ u-boot,dm-pre-reloc;
+
+ cpu@0 {
+ compatible = "brcm,bcm3380-cpu", "mips,mips4Kc";
+ device_type = "cpu";
+ reg = <0>;
+ u-boot,dm-pre-reloc;
+ };
+
+ cpu@1 {
+ compatible = "brcm,bcm3380-cpu", "mips,mips4Kc";
+ device_type = "cpu";
+ reg = <1>;
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ clocks {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ u-boot,dm-pre-reloc;
+
+ periph_osc: periph-osc {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <50000000>;
+ u-boot,dm-pre-reloc;
+ };
+
+ periph_clk0: periph-clk@14e00004 {
+ compatible = "brcm,bcm6345-clk";
+ reg = <0x14e00004 0x4>;
+ #clock-cells = <1>;
+ };
+
+ periph_clk1: periph-clk@14e00008 {
+ compatible = "brcm,bcm6345-clk";
+ reg = <0x14e00008 0x4>;
+ #clock-cells = <1>;
+ };
+ };
+
+ ubus {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ u-boot,dm-pre-reloc;
+
+ memory-controller@12000000 {
+ compatible = "brcm,bcm6328-mc";
+ reg = <0x12000000 0x1000>;
+ u-boot,dm-pre-reloc;
+ };
+
+ periph_rst0: reset-controller@14e0008c {
+ compatible = "brcm,bcm6345-reset";
+ reg = <0x14e0008c 0x4>;
+ #reset-cells = <1>;
+ };
+
+ periph_rst1: reset-controller@14e00090 {
+ compatible = "brcm,bcm6345-reset";
+ reg = <0x14e00090 0x4>;
+ #reset-cells = <1>;
+ };
+
+ pll_cntl: syscon@14e00094 {
+ compatible = "syscon";
+ reg = <0x14e00094 0x4>;
+ };
+
+ syscon-reboot {
+ compatible = "syscon-reboot";
+ regmap = <&pll_cntl>;
+ offset = <0x0>;
+ mask = <0x1>;
+ };
+
+ wdt: watchdog@14e000dc {
+ compatible = "brcm,bcm6345-wdt";
+ reg = <0x14e000dc 0xc>;
+
+ clocks = <&periph_osc>;
+ };
+
+ wdt-reboot {
+ compatible = "wdt-reboot";
+ wdt = <&wdt>;
+ };
+
+ gpio0: gpio-controller@14e00100 {
+ compatible = "brcm,bcm6345-gpio";
+ reg = <0x14e00100 0x4>, <0x14e00108 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ status = "disabled";
+ };
+
+ gpio1: gpio-controller@14e00104 {
+ compatible = "brcm,bcm6345-gpio";
+ reg = <0x14e00104 0x4>, <0x14e0010c 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <3>;
+
+ status = "disabled";
+ };
+
+ uart0: serial@14e00200 {
+ compatible = "brcm,bcm6345-uart";
+ reg = <0x14e00200 0x18>;
+ clocks = <&periph_osc>;
+
+ status = "disabled";
+ };
+
+ uart1: serial@14e00220 {
+ compatible = "brcm,bcm6345-uart";
+ reg = <0x14e00220 0x18>;
+ clocks = <&periph_osc>;
+
+ status = "disabled";
+ };
+
+ leds: led-controller@14e00f00 {
+ compatible = "brcm,bcm6328-leds";
+ reg = <0x14e00f00 0x1c>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+ };
+};
@@ -2,6 +2,7 @@ menu "Broadcom MIPS platforms"
depends on ARCH_BMIPS
config SYS_SOC
+ default "bcm3380" if SOC_BMIPS_BCM3380
default "bcm6328" if SOC_BMIPS_BCM6328
default "bcm6348" if SOC_BMIPS_BCM6348
default "bcm6358" if SOC_BMIPS_BCM6358
@@ -10,6 +11,17 @@ config SYS_SOC
choice
prompt "Broadcom MIPS SoC select"
+config SOC_BMIPS_BCM3380
+ bool "BMIPS BCM3380 family"
+ select SUPPORTS_BIG_ENDIAN
+ select SUPPORTS_CPU_MIPS32_R1
+ select MIPS_TUNE_4KC
+ select MIPS_L1_CACHE_SHIFT_4
+ select SWAP_IO_SPACE
+ select SYSRESET_WATCHDOG
+ help
+ This supports BMIPS BCM3380 family.
+
config SOC_BMIPS_BCM6328
bool "BMIPS BCM6328 family"
select SUPPORTS_BIG_ENDIAN
new file mode 100644
@@ -0,0 +1,25 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_BMIPS_BCM3380_H
+#define __CONFIG_BMIPS_BCM3380_H
+
+/* CPU */
+#define CONFIG_SYS_MIPS_TIMER_FREQ 166500000
+
+/* RAM */
+#define CONFIG_NR_DRAM_BANKS 1
+#define CONFIG_SYS_SDRAM_BASE 0x80000000
+
+/* U-Boot */
+#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + 0x100000
+
+#if defined(CONFIG_BMIPS_BOOT_RAM)
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SYS_INIT_SP_OFFSET 0x2000
+#endif
+
+#endif /* __CONFIG_BMIPS_BCM3380_H */
new file mode 100644
@@ -0,0 +1,23 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * Derived from Broadcom GPL Source Code:
+ * Copyright (C) Broadcom Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_BCM3380_H
+#define __DT_BINDINGS_CLOCK_BCM3380_H
+
+#define BCM3380_CLK0_DDR 0
+#define BCM3380_CLK0_FPM 1
+#define BCM3380_CLK0_CRYPTO 2
+#define BCM3380_CLK0_EPHY 3
+#define BCM3380_CLK0_PCIE 16
+#define BCM3380_CLK0_SPI 17
+#define BCM3380_CLK0_ENET0 18
+#define BCM3380_CLK0_ENET1 19
+#define BCM3380_CLK0_PCM 27
+
+#endif /* __DT_BINDINGS_CLOCK_BCM3380_H */
new file mode 100644
@@ -0,0 +1,16 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * Derived from Broadcom GPL Source Code:
+ * Copyright (C) Broadcom Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __DT_BINDINGS_RESET_BCM3380_H
+#define __DT_BINDINGS_RESET_BCM3380_H
+
+#define BCM3380_RST0_SPI 0
+#define BCM3380_RST0_PCM 13
+
+#endif /* __DT_BINDINGS_RESET_BCM3380_H */
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> --- v2: no changes. arch/mips/dts/brcm,bcm3380.dtsi | 154 ++++++++++++++++++++++++++++++ arch/mips/mach-bmips/Kconfig | 12 +++ include/configs/bmips_bcm3380.h | 25 +++++ include/dt-bindings/clock/bcm3380-clock.h | 23 +++++ include/dt-bindings/reset/bcm3380-reset.h | 16 ++++ 5 files changed, 230 insertions(+) create mode 100644 arch/mips/dts/brcm,bcm3380.dtsi create mode 100644 include/configs/bmips_bcm3380.h create mode 100644 include/dt-bindings/clock/bcm3380-clock.h create mode 100644 include/dt-bindings/reset/bcm3380-reset.h