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[v4,2/6] target/alpha: optimize cvtlq() using extract op

Message ID 20170512233843.27713-3-f4bug@amsat.org
State Changes Requested
Headers show

Commit Message

Philippe Mathieu-Daudé May 12, 2017, 11:38 p.m. UTC
Patch created mechanically using Coccinelle script via:

    $ spatch --macro-file scripts/cocci-macro-file.h --in-place \
        --sp-file scripts/coccinelle/tcg_gen_extract.cocci --dir target

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/alpha/translate.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

Comments

Richard Henderson May 13, 2017, 12:04 a.m. UTC | #1
On 05/12/2017 04:38 PM, Philippe Mathieu-Daudé wrote:
> Patch created mechanically using Coccinelle script via:
> 
>      $ spatch --macro-file scripts/cocci-macro-file.h --in-place \
>          --sp-file scripts/coccinelle/tcg_gen_extract.cocci --dir target
> 
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
>   target/alpha/translate.c | 3 +--
>   1 file changed, 1 insertion(+), 2 deletions(-)
> 
> diff --git a/target/alpha/translate.c b/target/alpha/translate.c
> index df5d695344..531af4f5b8 100644
> --- a/target/alpha/translate.c
> +++ b/target/alpha/translate.c
> @@ -747,9 +747,8 @@ static void gen_cvtlq(TCGv vc, TCGv vb)
>       /* The arithmetic right shift here, plus the sign-extended mask below
>          yields a sign-extended result without an explicit ext32s_i64.  */
>       tcg_gen_sari_i64(tmp, vb, 32);
> -    tcg_gen_shri_i64(vc, vb, 29);
> +    tcg_gen_extract_i64(vc, vb, 29, 30);
>       tcg_gen_andi_i64(tmp, tmp, (int32_t)0xc0000000);
> -    tcg_gen_andi_i64(vc, vc, 0x3fffffff);
>       tcg_gen_or_i64(vc, vc, tmp);

While this is accurate, looking at the broader context I think it would be 
better to use a deposit operation for this case.

   tcg_gen_shri_i64(tmp, vb, 29);
   tcg_gen_sari_i64(vc, vb, 32);
   tcg_gen_deposit_i64(vc, vc, tmp, 0, 30);


r~
diff mbox

Patch

diff --git a/target/alpha/translate.c b/target/alpha/translate.c
index df5d695344..531af4f5b8 100644
--- a/target/alpha/translate.c
+++ b/target/alpha/translate.c
@@ -747,9 +747,8 @@  static void gen_cvtlq(TCGv vc, TCGv vb)
     /* The arithmetic right shift here, plus the sign-extended mask below
        yields a sign-extended result without an explicit ext32s_i64.  */
     tcg_gen_sari_i64(tmp, vb, 32);
-    tcg_gen_shri_i64(vc, vb, 29);
+    tcg_gen_extract_i64(vc, vb, 29, 30);
     tcg_gen_andi_i64(tmp, tmp, (int32_t)0xc0000000);
-    tcg_gen_andi_i64(vc, vc, 0x3fffffff);
     tcg_gen_or_i64(vc, vc, tmp);
 
     tcg_temp_free(tmp);