From patchwork Thu May 11 12:20:33 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joakim Tjernlund X-Patchwork-Id: 761042 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3wNsdZ6fPnz9sDB for ; Thu, 11 May 2017 22:20:50 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755499AbdEKMUo (ORCPT ); Thu, 11 May 2017 08:20:44 -0400 Received: from smtp.transmode.se ([31.15.61.139]:50486 "EHLO smtp.transmode.se" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755489AbdEKMUn (ORCPT ); Thu, 11 May 2017 08:20:43 -0400 Received: from gentoo-jocke.infinera.com (gentoo-jocke.infinera.com [10.210.73.34]) by smtp.transmode.se (Postfix) with ESMTP id 9786A1186FD9; Thu, 11 May 2017 14:20:35 +0200 (CEST) Received: from gentoo-jocke.infinera.com (gentoo-jocke.infinera.com [127.0.0.1]) by gentoo-jocke.infinera.com (8.14.9/8.14.9) with ESMTP id v4BCKZH3022550; Thu, 11 May 2017 14:20:35 +0200 Received: (from jocke@localhost) by gentoo-jocke.infinera.com (8.14.9/8.14.9/Submit) id v4BCKZ8L022546; Thu, 11 May 2017 14:20:35 +0200 From: Joakim Tjernlund To: linux-i2c@vger.kernel.org, Wolfram Sang , Scott Wood Cc: Joakim Tjernlund Subject: [PATCHv2] i2c-mpc: Correct I2C reset procedure Date: Thu, 11 May 2017 14:20:33 +0200 Message-Id: <20170511122033.22471-1-joakim.tjernlund@infinera.com> X-Mailer: git-send-email 2.10.2 Sender: linux-i2c-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-i2c@vger.kernel.org Current I2C reset procedure is broken in two ways: 1) It only generate 1 START instead of 9 STARTs and STOP. 2) It leaves the bus Busy so every I2C xfer after the first fixup calls the reset routine again, for every xfer there after. This fixes both errors. Signed-off-by: Joakim Tjernlund Acked-by: Scott Wood --- v2 - Remove io barrier call. drivers/i2c/busses/i2c-mpc.c | 23 +++++++++++++++-------- 1 file changed, 15 insertions(+), 8 deletions(-) diff --git a/drivers/i2c/busses/i2c-mpc.c b/drivers/i2c/busses/i2c-mpc.c index 8393140..6b5e6ce4 100644 --- a/drivers/i2c/busses/i2c-mpc.c +++ b/drivers/i2c/busses/i2c-mpc.c @@ -104,23 +104,30 @@ static irqreturn_t mpc_i2c_isr(int irq, void *dev_id) /* Sometimes 9th clock pulse isn't generated, and slave doesn't release * the bus, because it wants to send ACK. * Following sequence of enabling/disabling and sending start/stop generates - * the 9 pulses, so it's all OK. + * the 9 pulses, each with a START then ending with STOP, so it's all OK. */ static void mpc_i2c_fixup(struct mpc_i2c *i2c) { int k; - u32 delay_val = 1000000 / i2c->real_clk + 1; - - if (delay_val < 2) - delay_val = 2; + unsigned long flags; for (k = 9; k; k--) { writeccr(i2c, 0); - writeccr(i2c, CCR_MSTA | CCR_MTX | CCR_MEN); + writeb(0, i2c->base + MPC_I2C_SR); /* clear any status bits */ + writeccr(i2c, CCR_MEN | CCR_MSTA); /* START */ + readb(i2c->base + MPC_I2C_DR); /* init xfer */ + udelay(15); /* let it hit the bus */ + local_irq_save(flags); /* should not be delayed further */ + writeccr(i2c, CCR_MEN | CCR_MSTA | CCR_RSTA); /* delay SDA */ readb(i2c->base + MPC_I2C_DR); - writeccr(i2c, CCR_MEN); - udelay(delay_val << 1); + if (k != 1) + udelay(5); + local_irq_restore(flags); } + writeccr(i2c, CCR_MEN); /* Initiate STOP */ + readb(i2c->base + MPC_I2C_DR); + udelay(15); /* Let STOP propagate */ + writeccr(i2c, 0); } static int i2c_wait(struct mpc_i2c *i2c, unsigned timeout, int writing)