| Message ID | 1292630381-23022-3-git-send-email-yorksun@freescale.com |
|---|---|
| State | Superseded |
| Delegated to: | Kumar Gala |
| Headers | show |
On Dec 17, 2010, at 5:59 PM, York Sun wrote: > diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/options.c b/arch/powerpc/cpu/mpc8xxx/ddr/options.c > index 774c0e4..38260f5 100644 > --- a/arch/powerpc/cpu/mpc8xxx/ddr/options.c > +++ b/arch/powerpc/cpu/mpc8xxx/ddr/options.c > @@ -81,10 +81,13 @@ unsigned int populate_memctl_options(int all_DIMMs_registered, > /* Operational Mode Paramters */ > > /* Pick ECC modes */ > -#ifdef CONFIG_DDR_ECC > - popts->ECC_mode = 1; /* 0 = disabled, 1 = enabled */ > -#else > popts->ECC_mode = 0; /* 0 = disabled, 1 = enabled */ > +#ifdef CONFIG_DDR_ECC > + if (hwconfig_sub("fsl_ddr", "ecc")) { > + if (hwconfig_subarg_cmp("fsl_ddr", "ecc", "on")) > + popts->ECC_mode = 1; > + } else > + popts->ECC_mode = 1; > #endif > popts->ECC_init_using_memctl = 1; /* 0 = use DMA, 1 = use memctl */ You'll need to update to use hwconfig_sub_f() & hwconfig_subarg_cmp_f() - k
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/options.c b/arch/powerpc/cpu/mpc8xxx/ddr/options.c index 774c0e4..38260f5 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/options.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/options.c @@ -81,10 +81,13 @@ unsigned int populate_memctl_options(int all_DIMMs_registered, /* Operational Mode Paramters */ /* Pick ECC modes */ -#ifdef CONFIG_DDR_ECC - popts->ECC_mode = 1; /* 0 = disabled, 1 = enabled */ -#else popts->ECC_mode = 0; /* 0 = disabled, 1 = enabled */ +#ifdef CONFIG_DDR_ECC + if (hwconfig_sub("fsl_ddr", "ecc")) { + if (hwconfig_subarg_cmp("fsl_ddr", "ecc", "on")) + popts->ECC_mode = 1; + } else + popts->ECC_mode = 1; #endif popts->ECC_init_using_memctl = 1; /* 0 = use DMA, 1 = use memctl */ diff --git a/doc/README.fsl-ddr b/doc/README.fsl-ddr index 1657ef6..9e3c539 100644 --- a/doc/README.fsl-ddr +++ b/doc/README.fsl-ddr @@ -78,6 +78,13 @@ If the DDR controller supports address hashing, it can be enabled by hwconfig. Syntax is: hwconfig=fsl_ddr:addr_hash=true +Memory controller ECC on/off +============================ +If ECC is enabled in board configuratoin file, i.e. #define CONFIG_DDR_ECC, +ECC can be turned on/off by hwconfig. + +Syntax is +hwconfig=fsl_ddr:ecc=off Memory testing options for mpc85xx ==================================
Add fsl_ddr:ecc=on in hwconfig. If ECC is enabled in board configuration file, ECC can be turned on/off by this switch. If this switch is omitted, it is ON by default. Syntax is hwconfig=fsl_ddr:ecc=on Signed-off-by: York Sun <yorksun@freescale.com> --- arch/powerpc/cpu/mpc8xxx/ddr/options.c | 9 ++++++--- doc/README.fsl-ddr | 7 +++++++ 2 files changed, 13 insertions(+), 3 deletions(-)