Patchwork [U-Boot,15/15] powerpc/85xx: Rework SBC8548 pci_init_board to use common FSL PCIe code

login
register
mail settings
Submitter Kumar Gala
Date Dec. 17, 2010, 11:50 p.m.
Message ID <1292629858-10233-15-git-send-email-galak@kernel.crashing.org>
Download mbox | patch
Permalink /patch/76039/
State Accepted
Commit 2d0a054d55665dee16343468b2ae8a0f8387dae1
Delegated to: Kumar Gala
Headers show

Comments

Kumar Gala - Dec. 17, 2010, 11:50 p.m.
Remove duplicated code in SBC8548 board and utliize the common
fsl_pcie_init_board().  We also now dynamically setup the LAWs for PCI
controllers based on which PCIe controllers are enabled.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
CC: Paul Gortmaker <paul.gortmaker@windriver.com>
---
 board/sbc8548/law.c     |    8 -------
 board/sbc8548/sbc8548.c |   50 ++++++++++++----------------------------------
 2 files changed, 13 insertions(+), 45 deletions(-)
Paul Gortmaker - Jan. 6, 2011, 9:12 p.m.
[[PATCH 15/15] powerpc/85xx: Rework SBC8548 pci_init_board to use common FSL PCIe code] On 17/12/2010 (Fri 17:50) Kumar Gala wrote:

> Remove duplicated code in SBC8548 board and utliize the common
> fsl_pcie_init_board().  We also now dynamically setup the LAWs for PCI
> controllers based on which PCIe controllers are enabled.
>
> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
> CC: Paul Gortmaker <paul.gortmaker@windriver.com>

Tested-by: Paul Gortmaker <paul.gortmaker@windriver.com>

Tested with Peter's anti-NULL patch on top of the mpc85xx dev branch.
Board has both PCI-X and PCI-e slots, with e1000 and skge respectively.

P.

-----------------------

U-Boot 2010.12-00426-ged7ea8f (Jan 06 2011 - 15:43:08)

CPU:   8548E, Version: 2.0, (0x80390020)
Core:  E500, Version: 2.0, (0x80210020)
Clock Configuration:
       CPU0:990  MHz,
       CCB:396  MHz,
       DDR:198  MHz (396 MT/s data rate), LBC:99   MHz
L1:    D-cache 32 kB enabled
       I-cache 32 kB enabled
Board: Wind River SBC8548 Rev. 0x2
I2C:   ready
DRAM:      SDRAM: 128 MiB
DDR: 256 MiB (DDR2, 64-bit, CL=4, ECC off)
       DDR Chip-Select Interleaving Mode: CS0+CS1
FLASH: 72 MiB
L2:    512 KB already enabled
*** Warning - bad CRC, using default environment

PCI: Host, 64 bit, 66 MHz, sync, arbiter
  00:01.0     - 8086:1026 - Network controller
PCI1: Bus 00 - 00

PCIe1: Root Complex, x1, regs @ 0xe000a000
  02:00.0     - 1148:9e00 - Network controller
PCIe1: Bus 01 - 02
In:    serial
Out:   serial
Err:   serial
Net:   eTSEC0, eTSEC1
Hit any key to stop autoboot:  0
=> pci 0
Scanning PCI devices on bus 0
BusDevFun  VendorId   DeviceId   Device Class       Sub-Class
Kumar Gala - Jan. 9, 2011, 8:49 p.m.
On Dec 17, 2010, at 5:50 PM, Kumar Gala wrote:

> Remove duplicated code in SBC8548 board and utliize the common
> fsl_pcie_init_board().  We also now dynamically setup the LAWs for PCI
> controllers based on which PCIe controllers are enabled.
> 
> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
> CC: Paul Gortmaker <paul.gortmaker@windriver.com>
> ---
> board/sbc8548/law.c     |    8 -------
> board/sbc8548/sbc8548.c |   50 ++++++++++++----------------------------------
> 2 files changed, 13 insertions(+), 45 deletions(-)

applied to 85xx, fixed commit typo s/utliize/utilize/

- k

Patch

diff --git a/board/sbc8548/law.c b/board/sbc8548/law.c
index 6d1efc0..5fa9db0 100644
--- a/board/sbc8548/law.c
+++ b/board/sbc8548/law.c
@@ -50,14 +50,6 @@  struct law_entry law_table[] = {
 #ifndef CONFIG_SPD_EEPROM
 	SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR),
 #endif
-#ifdef CONFIG_SYS_PCI1_MEM_PHYS
-	SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
-	SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCI),
-#endif
-#ifdef CONFIG_SYS_PCIE1_MEM_PHYS
-	SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1),
-	SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_1),
-#endif
 	/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
 	SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
 };
diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c
index 06c1eea..f0e591b 100644
--- a/board/sbc8548/sbc8548.c
+++ b/board/sbc8548/sbc8548.c
@@ -310,33 +310,19 @@  long int fixed_sdram (void)
 static struct pci_controller pci1_hose;
 #endif	/* CONFIG_PCI1 */
 
-#ifdef CONFIG_PCIE1
-static struct pci_controller pcie1_hose;
-#endif	/* CONFIG_PCIE1 */
-
-
 #ifdef CONFIG_PCI
 void
 pci_init_board(void)
 {
 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	struct fsl_pci_info pci_info[2];
-	u32 devdisr, pordevsr, porpllsr, io_sel;
 	int first_free_busno = 0;
-	int num = 0;
-
-#ifdef CONFIG_PCIE1
-	int pcie_configured;
-#endif
-
-	devdisr = in_be32(&gur->devdisr);
-	pordevsr = in_be32(&gur->pordevsr);
-	porpllsr = in_be32(&gur->porpllsr);
-	io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
-
-	debug("   pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
 
 #ifdef CONFIG_PCI1
+	struct fsl_pci_info pci_info;
+	u32 devdisr = in_be32(&gur->devdisr);
+	u32 pordevsr = in_be32(&gur->pordevsr);
+	u32 porpllsr = in_be32(&gur->porpllsr);
+
 	if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
 		uint pci_32 = pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32;
 		uint pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
@@ -350,8 +336,13 @@  pci_init_board(void)
 			pci_clk_sel ? "sync" : "async",
 			pci_arb ? "arbiter" : "external-arbiter");
 
-		SET_STD_PCI_INFO(pci_info[num], 1);
-		first_free_busno = fsl_pci_init_port(&pci_info[num++],
+		SET_STD_PCI_INFO(pci_info, 1);
+		set_next_law(pci_info.mem_phys,
+			law_size_bits(pci_info.mem_size), pci_info.law);
+		set_next_law(pci_info.io_phys,
+			law_size_bits(pci_info.io_size), pci_info.law);
+
+		first_free_busno = fsl_pci_init_port(&pci_info,
 					&pci1_hose, first_free_busno);
 	} else {
 		printf("PCI: disabled\n");
@@ -364,22 +355,7 @@  pci_init_board(void)
 
 	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI2); /* disable PCI2 */
 
-#ifdef CONFIG_PCIE1
-	pcie_configured = is_serdes_configured(PCIE1);
-
-	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
-		SET_STD_PCIE_INFO(pci_info[num], 1);
-		printf("PCIE: base address %lx\n", pci_info[num].regs);
-		first_free_busno = fsl_pci_init_port(&pci_info[num++],
-					&pcie1_hose, first_free_busno);
-	} else {
-		printf("PCIE: disabled\n");
-	}
-
-	puts("\n");
-#else
-	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
-#endif
+	fsl_pcie_init_board(first_free_busno);
 }
 #endif